Parasitic Inductance Effect on Switching Losses for
a High Frequency Dc-Dc Converter
Thomas Meade†, Dara O’Sullivan∗ , Raymond Foley∗, Cristian Achimescu†, Michael Egan∗ and Paul McCloskey†
∗ Department
of Electrical Engineering,
University College Cork,
Cork, Ireland
† Tyndall National Institute,
Lee Maltings,
Cork, Ireland
Email: paul.mccloskey@tyndall.ie
parallel wires is given in (2) for l > d, where d is the
separation distance and l is the length.
Abstract— This work examines the impact of packaging parasitics on the efficiency of a synchronous DC-DC buck converter.
An anaytical model of the losses in the converter is developed
and this is compared to practical results at switching frequencies
in the range of 1-2 MHz. The effect that the packaging parasitic
inductance has on efficiency is highlighted by predicting the
expected losses from a converter with optimised packaging
parasitics.
Lself =
ln
Lmutual
I. I NTRODUCTION
2l
+ 0.5 + 0.22
w+t
µ0 l
2l
=
ln − 1 +
2π
d
d
l
w+t
l
(1)
(2)
It follows from (1), that to minimise the parasitic inductance
value, the length through which the current passes must be
minimised and the cross sectional area through which current
flows maximised.
Simulations were carried out in order to determine whether
a strategy of placing wire-bonds in parallel was more effective
at reducing the parasitic inductance value as opposed to using
a block of copper occupying the same total cross sectional area
of the wire-bonds. It was found that while placing wire-bonds
in parallel reduces the overall self inductance, the effect of
mutual inductance between the wires results in a higher overall
inductance. The formula for calculating the overall inductance
for two wire-bonds in parallel with current flowing in the same
direction is
The steady decrease in IC system voltages along with the
sharp rise in power requirements result in significant current
being delivered from the power supply [1]. This trend coupled
with the increase in switching speeds of power semiconductor
devices, due to the technology transfer from bipolar to MOS
based devices and the reduction in Rds(on) means that the
effect of packaging parasitics on power converter performance
is increasingly significant. As switching speeds increase, the
limiting factor in power device performance is shifting from
the silicon characteristics to the path inductance. This paper
uses an analytical approach to model converter losses and
efficiency. The effect of packaging inductance is included in
the model by incorporating inductance values extracted from
the packaging geometry using Ansoft Q3D. The analytical
model of a discrete component converter, in the frequency
range of 1-2 MHz, is verified with practical efficiency results.
The model is then applied to predict the efficiency of a 3 MHz,
1V, 20A converter using three different packaging techniques.
One technique is to use discrete devices on PCB, the next
technique is to use an integrated power-train incorporating
wire-bonds and the final technique is to use an innovative
wire-bond-free power train.
Lself + Lmutual
.
(3)
2
In summary, packaging inductance is minimised by minimising current path length, maximising current path crosssectional area, and, where possible using a solid path, as
opposed to parallel paths. Such considerations have led to
innovative packaging techniques in power MOSFET design,
such as the DirectFET from International Rectifier [3].
Ltotal =
III. MOSFET S WITCHING E QUATIONS
II. PACKAGING I NDUCTANCE
The circuit diagram of a synchronous buck converter with
the main power loop parasitics included is shown in Fig.1. It is
important to note that the loop includes the input decoupling
capacitor and its associated parasitic inductance. The parasitic
inductances shown are those which contribute to the switching
losses of the converter. In recent integrated converter power
trains [4], the inductances LS1 and LS2 have been effectively
The self inductance of a wire with rectangular cross section
can be derived using electromagnetic field theory and ‘geometry mean distance’ as in [2]. The equation for self inductance
is given in (1), where l is the length of the wires, w and t
are the width and thickness of the rectangular cross section,
respectively. The equation for mutual inductance between two
978-1-4244-1874-9/08/$25.00 ©2008 IEEE
µ0 l
2π
3
Ls1 Ld2
Ld1
VD
Cin
Ld4
Io
Cout
Low Side
Driver
IDS
Current
&
Voltage
Ld3
High Side
Driver
+
-
Io
Load
VDS
Ls2
VGS
VGH
Fig. 1.
t
Buck converter circuit with included parasitic inductance
t1
Time
Interval 1
LD
Fig. 3.
CGD
RG
CDS
+ V
D
-
Current and voltage waveforms during MOSFET turn-on
2) Time interval 2: In this time interval VGS (t) is greater
than Vth . Drain current, IDS (t) now rises. The change in
switching loop current induces a voltage across the parasitic
inductance and causes the drain to source voltage, VDS (t)
(which in idealised switching waveforms [8] remains constant)
to fall. Writing equations around the switching loop as in [5]
yields:
LS
Fig. 2.
Time
Interval 4
t4
time interval ends when the gate to source voltage equals the
threshold voltage.
−t
RG (CGD +CGS )
VGS (t) = VGH × 1 − e
(6)
CGS
VGH
Time
Interval 2
t2 t3
Time
Interval 3
Equivalent circuit for the main transition period
VGS (t) = A
eliminated from the gate drive loop by connecting the source
terminal of the MOSFET directly to the driver inside an
integrated driver-MOSFET package, thus reducing the switching losses. In the analytical model developed, this source
inductance is included in the analysis but can be given a zero
value in the drive loop equations as the application requires.
In order to examine the effect of the parasitic inductances on
the switching losses of the high side MOSFET, the parasitic
inductances are grouped into two lumped values, with
LD = Ld1 + Ld2 + Ld3 + Ld4 + Ls2
(4)
LS = LS1 .
(5)
δ 2 VGS (t)
dVGS (t)
+B
+ VGS (t)
dt2
dt
(7)
where
A = RG gf s CGD (LD + LS )
(8)
B = RG (CGD + CGS ) + LS gf s .
(9)
Solving (7) and piecing it together with the equation for
VGS (t) in time interval 1 [Eqn. (6)], yields:
−(t−t1 )
VGS (t) = VB1 − VB2 e T1
sin ω1 (t − t1 )
if 4A − B 2 ≥ 0
× cos ω1 (t − t1 ) +
ω1 T 1
(10)
and
Each switching sequence, either from the off to the on state
or vice versa is divided into a number of separate intervals,
for which different conditions and constraints apply [5] [6].
The non-linear characteristics of the internal MOSFET capacitances [7] are included in the analysis.
and
A. Upper MOSFET Turn On Waveforms
where
VB2
VGS (t) = VB1 −
T
− T3
2
−(t−t1 )
−(t−t1 )
T2
T3
× T2 e
if 4A − B 2 < 0
− T3 e
4A − B 2
,
4A2
2A
,
T1 =
B
2A
√
T2 =
,
B + B 2 − 4A
ω12 =
Fig. 3 shows current and voltage waveforms during the turn
on of the upper MOSFET. This has four distinct time intervals,
described below.
1) Time interval 1: In this time period the gate voltage
rises to its threshold value. No drain current flows as long as
the gate voltage is less than the threshold voltage Vth . The
4
(11)
(12)
(13)
(14)
and
2A
√
.
B − B 2 − 4A
(15)
VB1 = VGH
(16)
VB2 = VGH − Vth ,
(17)
T3 =
Current
&
Voltage
VGH is the applied gate voltage and gf s is the forward
transconductance of the MOSFET. During turn-on
IDS
Vpeak
VDS
and
VGS
while during the turn-off transient
t
VB1 = 0
and
VB2 = −
t1
(18)
Io
gf s + Vth
Time
Time
Time
Interval 1 Interval 2 Interval 3
Fig. 4.
(19)
where I0 is the full load current. IDS (t) and VDS (t) of the
MOSFET for this time period can be calculated using (20) and
(21) based on VGS (t). This time interval comes to an end at
time t2 when IDS (t) rises to I0 or VDS (t) falls to I0 RDSon ,
whichever occurs first.
IDS (t) = gf s (VGS (t) − Vth )
VDS (t) = VD − (LD + LS )
dIDS (t)
dt
I0
.
gf s
t3
Time
Interval 4
t4
Current and voltage waveforms during MOSFET turn-off
Ls
VGH − VGS (t2 ) −
VD
L + LS
D
−(t−t2 )
× 1 − e RG (CGD +CGS ) + VGS (t2 )
VGS (t) =
(20)
(25)
4) Time interval 4: In this time interval the gate to source
voltage completes its charge to the level of applied drive
voltage VGH .
(21)
VGS (t) = (VGH − VGS (t3 ))
−(t−t3 )
RG (CGD +CGS )
+ VGS (t3 )
× 1−e
3) Time interval 3: In this time interval either VDS (t)
completes its fall or IDS (t) completes its rise. Consider first
the drain voltage completing its fall, IDS (t) having risen to
I0 . Since the drain current is constant, VGS (t) must also be
constant:
VGS (t) = Vth +
t2
(26)
B. Upper MOSFET Turn Off Waveforms
A similar analysis may be performed during the turn-off
transition of the upper MOSFET, using the waveforms shown
in Fig. 4.
1) Time interval 1: In time interval 1, the gate source
voltage, VGS (t) falls at a rate determined by the time constant
RG (CGD + CGS ). There is no change to the drain current
or drain to source voltage until the value of VGS (t) falls to
VGS(th) + I0 /gf s . This is the gate voltage needed to sustain
drain current I0 . The gate to source voltage during this period
is given by:
(22)
The drain to source voltage in this time period is given by:
!
VGH − (Vth + gIf0s )
(t − t2 ) (23)
VDS (t) = VDS (t2 ) −
RG CGD
where VDS (t2 ) is the drain to source voltage at the start of
this time period, and t2 is the time at which IDS rises to full
load current. The time period ends at time t3 when VDS (t)
completes its fall to I0 RDSon .
Consider now the situation where the current completes its rise
during the third time interval,VDS (t) having already completed
its fall. IDS (t) and VGS (t) are given by:
VD
IDS (t) = IDS (t2 ) +
(t − t2 )
(24)
LD + LS
−t
VGS (t) = VGH e RG (CGS +CGD ) .
(27)
This interval ends at time t1 when VGS (t) falls to a value of
VGS(th) + gIf0s .
2) Time Interval 2: In this time period the drain to source
voltage rises to VD , the applied dc input voltage. The drain
current remains constant at I0 and the gate to source voltage
stays constant at VGS(th) + gIf0s . The drain to source voltage
during this time period rises according to the following equation:
gf s VGS(th) + I0
(t − t1 ).
(28)
VDS (t) =
(1 + gf s RG )CGD + CDS
where VD is the applied dc input voltage and IDS (t2 ) is the
drain to source current at the start of this time period, and t2
in this case is the time at which the drain voltage drops to
I0 RDSon .
5
This time period comes to an end at time t2 when VDS (t)
rises to VD .
3) Time Interval 3: As with the second time interval during
turn-on, both the drain current and drain voltage change. A
change in the drain current produces a change in the voltage
across the parasitic inductances LS and LD . A current flow
through the capacitance CGD is produced. This current flow
restrains the rate of decrease of the gate voltage, which in
turn restrains the original rate of change of drain current. The
gate to source voltage during this period is given by (29) or
(30). During this time interval IDS (t) falls from I0 to zero
according to (20) and VDS (t) changes in accordance with (21).
This time interval comes to an end at time t3 when VGS (t)
falls to the threshold voltage VGS(th) .
IV. S OURCES
OF
A. Crossover Switching Loss
The turn-on switching loss can be calculated using the turnon switching waveforms derived in Section III
Pon(loss) = FSW
t3
Z
t1
Pof f (loss) = FSW
−(t−t2 )
VGS (t) = VB1 − VB2 e T1
sin ω1 (t − t2 )
if 4A − B 2 ≥ 0
× cos ω1 (t − t2 ) +
ω1 T 1
(29)
× T2 e
− T3 e
−(t−t2 )
T3
if 4A − B 2 < 0
Z
t3
VB2 = −(I0 /gf s + VGS(th) ).
(32)
Pcond−lower
and
−(t−t3 )
T4
∆I02
2
DRDS(on−upper)
= I0 +
12
(39)
∆I02
2
(1 − D)RDS(on−lower) . (40)
= I0 +
12
C. Gate Drive Loss
Most of the switch losses associated with charging and
discharging the MOSFET gate are dissipated in the driver IC
since the source and sink resistances of the driver IC are much
greater than the MOSFET’s internal gate resistance. The gate
drive loss of the upper MOSFET is given, as in [9], by:
4) Time interval 4: At the end of time interval 3, the drain
current has fallen to zero, but the drain voltage VDS (t3 ) is
greater than the circuit voltage VIN . The drain capacitance
CDS “rings” with the stray circuit inductance. The stray circuit
resistance Rl damps the oscillation. The drain voltage is given
by:
VDS (t) = VIN + (VDS (t3 ) − VIN )e
(38)
where ∆I0 is the ripple of the load current I0 , D is the duty
cycle and RDS(on−upper) is the is the on-state resistance of
the top switch.
The lower MOSFET conduction loss is given by:
T1 , T2 , T3 and ω1 are as given previously for turn-on interval
2. Also
(31)
VDS (t) · IDS (t)dt.
The upper MOSFET conduction loss is given by:
(30)
VB1 = 0
(37)
B. Conduction Loss
Pcond−upper
−(t−t2 )
T2
VDS (t) · IDS (t)dt
where FSW is the switching frequency of the converter.
Similarly, the turn-off switching losses are calculated from
t1
VB2
VGS (t) = VB1 −
T2 − T3
P OWER L OSS
PG−upper = Qg VGH F sw.
(41)
A similar equation holds for the gate drive of the lower
MOSFET.
cos(ω4 (t − t3 ))
(33)
where
T4 =
2LD
Rl
D. Reverse Recovery and Ringing Turn On
(34)
The reverse recovery and ringing power loss is calculated
as in [7], via
1
PRRR(on) = FSW VD QRR(lower) + Qoss(lower) VD
2
(42)
where QRR(lower) is the reverse recovery charge for the lower
MOSFET, which is dependant on the loop inductance [7], and
Qoss(lower) is the charge stored in CGD + CDS of the lower
MOSFET.
and
p
2 R2
4LD CDS − CDS
l
ω4 =
.
2LD CDS
(35)
The gate voltage decays to zero with time constant RG (CGD +
CGS ). The gate to source voltage is given by:
−(t−t3 )
VGS (t) = VGS (t3 )e RG (CGD +CGS ) .
(36)
6
IIN (cap)RMS
v"
u
u
= t (I
SW (pk)
− IIN (avg) )2 +
E. Reverse Recovery and Ringing Energy Turn Off
The reverse recovery ringing power loss during MOSFET
turn-off is given by
1
Qoss(V peak) Vpeak − Qoss(VD ) VD
PRRR(of f ) = FSW
2
(43)
where Qoss(V peak) is the charge stored in CGS + CGD of
the upper MOSFET when the voltage reaches its peak value,
Vpeak . Qoss(VD ) is the charge stored in CGS + CGD of the
upper MOSFET when the voltage reaches its steady state
value, VD .
2
∆ISW
(pp)
12
#
4.0
Power Loss (W)
3.5
3.0
2
· D + IIN
(avg) · (1 − D)
(46)
534 kHz
1.5 MHz
1.9 MHz
2.5
2.0
1.5
1.0
0.5
U
pp
e
Lo r M
rs
e we OS
Re r
C
co MO on
d
ve
S
ry
C uc
an on tion
d
d
Ri uct Lo
Bo
ng ion ss
dy
in
D Rin g T Los
io
de gin urn s
Co g T O
ur n
n
G duc n O
at
e- tion ff
G Dri Lo
at
e - ve ss
D Up
r
In ive per
pu L
o
t
Iu Ca we
r
tp
ut pa c
Ca ito
r
pa
ci
to
r
P
on
In
du
ct Po
or ff
W Los
ire s
Lo
ss
0.0
Re
ve
F. Diode Conduction Loss
The average power loss in the synchronous diode is given
by:
Pdiode = Vf r I0−v Td1 FSW + Vf r I0−p Td2 FSW
(44)
Fig. 5. Theoretical breakdown of power-converter losses at three different
frequencies
where Vf r is the forward voltage drop, Td1 and Td2 are the
dead-times when the diode is conducting, I0−v is the valley
value of the load current I0 and I0−p is the peak value of the
load current I0 .
V. P RACTICAL D C - DC C ONVERTER
A practical DC-DC converter as shown in Fig. 8 was built in
order to verify the analytical power loss equations. The output
voltage is 1V, the input voltage is 12V and the inductor value
is 300 nH. The parasitic inductances were extracted from the
layout diagram, shown in Fig. 9, using the software package
Ansoft Q3D. The extracted inductances are LD =6.03 nH and
LS =1.65 nH. Oscilliscope plots of VGS and VDS during the
MOSFET turn-on and turn-off transitions with a 20 A output
current are shown in Figs. 6 and 7 respectively.
Graphs of the efficiency versus load current for three
different switching frequencies are shown in Fig. 10. These
results show good correlation between the analytical model
that has been developed (theoretical values) and the measured
practical values.
G. Other Losses
Losses in the input and output capacitors as well as the
power inductor must also be considered to accurately model
the overall converter loss. The input capacitor power loss can
be calculated from
2
PIN (cap) = IIN
(cap)RMS Resr−IN (cap)
(45)
where the rms capacitor current, IIN (cap)RMS , is calculated
from (46) above and
Vout Iout
.
(47)
IIN (avg) =
ηVIN
ISW and η are the top-switch current and converter powertrain efficiency respectively. The ac component of the load
current generates a power loss in the output capacitors. This
is given by
2
POUT (cap) = ∆I0(RMS)
Resr−OUT (cap)
A. Effect of Parasitic Inductance on a 3 MHz converter
Having validated the analytical model in a discretecomponent converter, it is possible to utilise the model for
predicting the converter efficiency at higher switching frequencies, and to examine the effect of using alternative packaging
technologies at these frequencies. A similar power converter
is modelled at a switching frequency of 3 MHz, with packaging parasitic inductances corresponding to (a) discrete power
devices, (b) currently available wire-bonded power trains, and
(c) an innovative wire-bond-free packaging technique using
copper as the interconnect medium. A comparison between the
switching losses of the three converters is shown in Fig. 11. As
is evident from Fig. 11, a higher parasitic inductance slightly
reduces the turn-on switching losses (with LS = 0), but
(48)
The power inductor losses comprise of hysteresis and eddycurrent losses in the core and winding resistive losses. Total
losses are calculated using a vendor-specified procedure [10]
for the inductor used in the design.
Fig. 5 shows the theoretical loss breakdown of the designed
converter operating at three different frequencies. The most
notable difference between the loss breakdowns as the frequency is increased is the change in the switching loss of the
converter, and in particular, the upper MOSFET turn-off power
loss, Pof f .
7
Fig. 6.
MOSFET turn on voltage waveforms
Fig. 8.
Fig. 7.
Buck converter as implemented
MOSFET turn off voltage waveforms
Fig. 9.
significantly increases the turn-off loss. The overall effect of
the changes in parasitic inductance on converter efficiency can
be seen in Fig. 12. Clearly, currently available wire-bonded
co-packaged power trains offer a significant advantage—in
terms of efficiency at a 3MHz switching frequency—over
designs using discrete components; however, the residual
parasitic inductance of even this approach limits the overall
converter efficiency. The plot predicts that the most appropriate
packaging strategy for a power converter at this frequency is
one which uses a wire-bond-free approach.
Layout diagram for the power stage of the converter
parasitic inductance on the switching losses has been examined
in detail. A loss model for a high frequency converter is
proposed in order to outline the impact of parasitic inductance
on efficiency and to highlight the deficiencies of using discrete
devices and a layout which are not optimised for minimum
parasitic inductance. The guidelines needed to reduce the
critical parasitic inductance values are also presented.
VI. C ONCLUSION
This paper has presented an analytical model for a buck
converter which has been verified experimentally. The effect of
8
85
80
10
Power Loss (W)
75
Efficiency (%)
70
65
60
55
50
Theoretical
Practical
45
8
6
4
2
0
P off
40
0
0
2
4
6
8
Discrete Power
Devices
Wire-bonded
Power Train
Wire-bond-fre
e Packaging
P on
10 12 14 16 18 20 22 24
Io (A)
Fig. 11. The effect of parasitic inductance on switching losses at 3MHz with
Io = 20 A
(a) FSW =534 kHz
85
80
80
75
75
70
65
60
Efficiency (%)
Efficiency (%)
70
55
50
Theoretical
Practical
45
40
0
0
2
4
6
8
10 12 14 16 18 20 22 24
Io (A)
65
60
55
50
(b) FSW =1.5 MHz
40
0
85
80
10
75
12
14
16
18
20
22
24
26
28
30
Io (A)
70
Efficiency (%)
Discrete Power Devices
Wire-bonded Power Train
Wire-bond-free Packaging
45
65
Fig. 12.
60
Efficiency comparison at 3 MHz for three packaging techniques
55
50
Theoretical
Practical
45
[3]
40
0
0
2
4
6
8
10 12 14 16 18 20 22 24
Io (A)
[4]
(c) FSW =1.9MHz
Fig. 10.
[5]
Efficiency vs. load current
[6]
[7]
R EFERENCES
[8]
[1] D. Staffiere and M. Mankikar, “Power technology roadmap for IT power
supplies,” in Proc. IEEE Appl. Power Electron. Conf., Mar. 2001, pp.
49–53.
[2] X. Qi, G. Wang, Z. Yu, R. W. Dutton, T. Young, and N. Chang, “Onchip inductance modeling and RLC extraction of VLSI interconnects for
[9]
[10]
9
circuit simulation,” in Proc. Custom Int. Circuits Conf., May 2000, pp.
487–490.
A. Sawle, M. Standing, T. Sammon, and A. Woodworth. Directfet a proprietary new source mounted power package for board mounted
power. International Rectifier. Surrey, England. [Online]. Available:
http://www.irf.com/technical-info/whitepaper/directfet.pdf
Philips PIP212-12M datasheet. [Online]. Available: http://www.nxp.
com/acrobat/datasheets/PIP212-12M 4.pdf
Y. Xiao, H. Shah, T. Chow, and R. Gutmann, “Analytical modeling
and experimental evaluation of interconnect parasitic inductance on
MOSFET switching characteristics,” 2004, pp. 516–521.
“Hexfet power MOSFET designer’s manual,” International Rectifier, ch.
11.
Y. Rena, M. Xu, J. Zhou, and F. C. Lee, “Analytical loss model of power
MOSFET,” IEEE Trans. Power Electron., vol. 21, no. 2, pp. 310–319,
Mar. 2006.
N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics
Converters, Applications and Design. John Wiley and Sons, ch. 22.
L. Balogh, “A design and application guide for high speed power
MOSFET gate drive circuits,” 2001, Unitrode Power Supply Design
Seminar.
“IHLP-5050 application note,” Vishay Dale, 2006, unpublished.