EE247
Lecture 20
ADC Converters
- Comparator architecture examples
– Flash ADC sources of error
• Sparkle code
• Meta-stability
– Techniques to reduce flash ADC
complexity
• Interpolating
• Folding
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 1
Voltage Comparator
Architectures
Comparator architectures
• High gain amplifier with differential analog input & single-ended large
swing output
– Output swing compatible with driving digital logic circuits
– Open-loop amplificationà no frequency compensation required
– Precise gain not required
•
Latched comparators; in response to a strobe, input stage disabled &
digital output stored in a latch till next strobe
– Two options for implementation :
• High-gain amplifier + simple digital latch
• Low-gain amplifier + a high-sensitivity latch
•
Sample-data comparators
– S/H input
– Offset cancellation
– Pipelined stages
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 2
Latched Comparator
fs
Vi+
Vi-
Av
Do+
Latch
Do-
Preamp
•
•
•
•
•
•
•
•
Clock rate fs
Resolution
Overload recovery
Input capacitance (and linearity!)
Power dissipation
Input common-mode range
Kickback noise
…
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 3
Comparators Overdrive Recovery
Linear model for a single-pole amplifier:
Uà amplification after time ta
During reset amplifier settles
exponentially to its zero input
condition with τ0=RC
Assume Vm à maximum input
normalized to 1/2lsb (=1)
EECS 247 Lecture 20: Data Converters
Example: Worst case input/output waveforms
à Limit output voltage swing by
1. Passive clamp
2. Active restore
3. Low gain/stage
© 2004 H.K. Page 4
Comparators Overdrive Recovery
Limiting Output
Clamp
Adds parasitic capacitance
Active Restore
After outputs are latchedà Activate φR &
equalize output nodes
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 5
CMOS Comparator Example
•Flash ADC: 8bits, +-1/2LSB INL @ fs=15MHz (Vref=3.8V)
•No offset cancellation
A. Yukawa, “A CMOS 8-Bit High-Speed A/D Converter IC,” JSSC June 1985, pp. 775-9.
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 6
Comparator with Auto-Zero
I. Mehr and L. Singer, “A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications,” JSSC
July 1999, pp. 912-20.
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 7
Auto-Zero Implementation
Ref:I. Mehr and L. Singer, “A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC,” JSSC March 2000, pp. 31825.
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 8
Comparator Example
•Variation on Yukawa latch used
w/o preamp
•No dc power when φ high
•Good for low resolution ADCs
•M11 & M12 added to vary
comparator threshold
•To 1st order, for W1=W2 &
W11=W12
Vthlatch = W11/W1 x VR
where VR=VR+ - V RRef: T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter," IEEE Journal of Solid-State
Circuits, vol. 30, pp. 166 - 172, March 1995.
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 9
Comparator Example
•Used in a pipelined ADC with
digital correction
àno offset cancellation
•Input buffers suppress kick-back
•Note differential reference
•M7, M8 operate in triode region
•Preamp gain ~10
•Current in MB2 switches by
LATCH signal to flow either in the
preamp or the latch.
Ref: S. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE JSSC ,NO. 6, Dec. 1987
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 10
Bipolar Comparator Example
•Used in 8bit 400Ms/s & 6bit
2Gb/s flash ADC
•Signal amplification during
φ1 high, latch operates
when φ1 low
•Input buffers suppress kickback & input current
•Separate ground and
supply buses for front-end
preamp à kick-back noise
reduction
Ref: Y. Akazawa, et al., "A 400MSPS 8b flash AD conversion LSI," IEEE International Solid-State Circuits Conference,
vol. XXX, pp. 98 - 99, February 1987.
Ref: T. Wakimoto, et al, "Si bipolar 2GS/s 6b flash A/D conversion LSI," IEEE International Solid-State Circuits
Conference, vol. XXXI, pp. 232 - 233, February 1988.
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 11
Flash Converter Sources of Error
Vref
•
Vin
– Offset
– Nonlinear input capacitance
– Kickback noise (disturbs
reference)
– Signal dependent sampling
time
R/2
R
Encoder
R
R
Digital
Output
R
R/2
EECS 247 Lecture 20: Data Converters
Comparator input:
•
Comparator output:
– Sparkle codes (… 111101000
…)
– Metastability
© 2004 H.K. Page 12
Typical Flash Output Encoder
Binary Output (negative)
VDD
b3
b2
b1
b0
0
0
0
•
Thermometer
code à 1-of-n
decoding
•
Final encoding
à NOR ROM
1
1
0
1
0
1
Thermometer to Binary decoder ROM
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 13
Typical Flash Output Decoder
Binary Output (negative)
VDD
b3
b2
b1
b0
0
0
0
1
b3 b2 b1 b0
1
Outputà 0 1 1 1
0
1
0
1
Thermometer to Binary decoder ROM
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 14
Sparkle Codes
VDD
Erroneous 0
(comparator
offset?)
b3
b2
b1
b0
0
Correct Output:
0111 … 1000
1
1
0
0
Erroneous
Output:
0000
1
1
0
1
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 15
Sparkle Tolerant Encoder
0
0
0
1
1
0
0
0
1
0
Protects against a single sparkle.
Ref: C. Mangelsdorf et al, “A 400-MHz Flash Converter with Error Correction,” JSSC February 1990, pp. 9971002.
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 16
Meta-Stability
Different gates interpret
metastable output X differently
0
Correct output: 0111 or 1000
0
0
Erroneous output:
1
0000
X
Solutions:
–Latches (high power)
–Gray encoding
1
1
0
1
Ref: C. Portmann and T. Meng, “Power-Efficient Metastability Error Reduction in CMOS Flash A/D Converters,”
JSSC August 1996, pp. 1132-40.
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 17
Gray Encoding
Thermometer Code
Gray
Binary
T1
T2
T3
T4
T5
T6
T7
G3
G2
G1
B3
B2
B1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
0
0
1
0
0
1
1
1
1
1
1
0
0
0
1
1
0
1
0
0
1
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
•
Each Ti affects only one Gi
à Avoids disagreement of interpretation by multiple gates
Protects also against sparkles
Follow Gray encoder by (latch and) binary encoder
•
•
EECS 247 Lecture 20: Data Converters
G1 = T1T3 + T5 T7
G2 = T2 T6
G3 = T4
© 2004 H.K. Page 18
Reducing Flash ADC Complexity
E.g. 10-bit “straight” flash
–
–
–
–
–
Input range: 0 … 1V
LSB = ∆: ~ 1mV
Comparators: 1023 with offset << LSB
Input capacitance: 1023 * 100fF = 102pF
Power: 1023 * 3mW = 3W
Techniques:
–
–
–
–
Interpolation
Folding
Folding & Interpolation
Two-step, pipelining
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 19
Interpolation
• Idea
– Interpolation between preamp outputs
• Reduces number of preamps
– Reduced input capacitance
– Reduced area, power dissipation
• Same number of latches
• Important “side-benefit”
– Decreased sensitivity to preamp offset
à improved DNL
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 20
Simulink Model
Vin
1
Vin
Vi
A2
Preamp2
2*Delta
2
Vref2
Y
A1
Preamp1
1*Delta
Vref1
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 21
Preamp Output
Vin
A1
A1
A2
0.5
A2
Preamp Output
0.4
0.3
0.2
0.1
0
-0.1
Zero crossings (to be
detected by latches) at Vin =
-0.2
-0.3
-0.4
-0.5
0
0.5
1
1.5
Vin / ∆
2
2.5
EECS 247 Lecture 20: Data Converters
3
Vref1 = 1 ∆
Vref2 = 2 ∆
© 2004 H.K. Page 22
Preamp Output
Differential Preamp Output
0.6
0.4
0.2
0
-0.2
-0.4
A1
-A1
A2
-A 2
0
0.5
1
1.5
2
0.6
0.4
0.2
0
-0.2
-0.4
2.5
Zero crossings at Vin =
3
A1+A 2
A1+A2
0
0.5
1
1.5
Vin / ∆
2
EECS 247 Lecture 20: Data Converters
2.5
Vref1 = 1 ∆
Vref12 = 0.5*(1+2) ∆
Vref2 = 2 ∆
3
© 2004 H.K. Page 23
Interpolation in Flash ADC
Vin
A1
Half as many reference voltages
and preamps
Interpolation factor:x2
A2
Possible to accomplish higher
interpolation factor
à Resistive interpolation
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 24
Resistive Interpolation
• Resistors produce
additional levels
• With 4 resistors, the
“interpolation factor”
M=8
(ratio of
latches/preamps)
Ref: H. Kimura et al, “A 10-b
300-MHz InterpolatedParallel A/D Converter,”
JSSC April 1993, pp.
438-446.
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 25
DNL Improvement
•
Preamp offset distributed over
M resistively interpolated
voltages:
à impact on DNL divided by M
•
Latch offset divided by gain of
preamp
à use “large” preamp gain …
Ref: H. Kimura et al, “A 10-b
300-MHz InterpolatedParallel A/D Converter,”
JSSC April 1993, pp.
438-446.
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 26
Preamp Output
Preamp Input Range
0.6
0.4
0.2
0
-0.2
-0.4
A1
-A1
A2
-A2
0
0.5
1
1.5
2
2.5
0.6
0.4
0.2
0
-0.2
-0.4
3
Linear preamp input ranges
must overlap
i.e. range > ∆
A1+A 2
A1 +A2
Sets upper bound on gain
<< VDD / ∆
0
0.5
1
1.5
Vin / ∆
2
2.5
EECS 247 Lecture 20: Data Converters
3
© 2004 H.K. Page 27
Interpolated-Parallel ADC
Ref: H. Kimura et al, “A 10-b 300-MHz Interpolated-Parallel A/D Converter,” JSSC April 1993, pp. 438-446.
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 28
Measured Performance
(7+3)
Ref:
H. Kimura et al, “A 10-b 300-MHz Interpolated-Parallel A/D Converter,” JSSC April 1993, pp.
438-446.
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 29
Folding Converter
MSB
ADC
VIN
Digital
Output
LSB
ADC
Folding Circuit
• Significantly fewer comparators than flash ~2B/2+1
• Fast
• Nonidealities in folder limit resolution to ~10Bits
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 30
Folding
•
Folder maps input to
smaller range
1.2
1
MSB ADC determines
which fold input is in
•
Folder Output
•
LSB ADC determines
position within fold
0.8
LSB
ADC
0.6
0.4
0.2
0
-0.2
0
•
0.5 1
1.5 2
2.5 3
3.5 4
Logic circuit combines
LSB and MSB results
MSB ADC
Analog Input
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 31
Generating Folds
A1-A2
A1
0.5
0
-0.5
0
0
-0.5
A1-A2+A3
-0.5
A1-A2
0
0.5
A3
A2
0.5
1
0.5
0.5
0
1
0.5
0
0.5
1
1.5
2
Vin / ∆
2.5
3
3.5
EECS 247 Lecture 20: Data Converters
4
0
-0.5
0
0.5
1
1.5
2
Vin / ∆
2.5
3
3.5
4
© 2004 H.K. Page 32
Folding Circuit
3V
3V
R1
1kOhm
R2
1kOhm
Vo1
M1
10 / 1
M2
10 / 1
Vo2
Vref1
M3
10 / 1
M4
10 / 1
I1
Vref2
M5
10 / 1
I2
M6
10 / 1
Vref3
M7
10 / 1
I3
M8
10 / 1
Vref4
I4
Vin
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 33
CMOS Folder Output
Folder Output
0.5
-0.5
Accurate only at
zero-crossings
Ideal Folder
CMOS Folder
0
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
Vin / ∆
2.5
3
3.5
4
0.1
Error
0.05
0
-0.05
-0.1
EECS 247 Lecture 20: Data Converters
Lowdown à
Most folding ADCs
do not actually use
the folds, but only the
zero-crossings!
© 2004 H.K. Page 34
Parallel Folders
Fine Flash
ADC 4
Folder 4
Vref + 3/4 * ∆
Fine Flash
ADC 3
Folder 3
Vref + 2/4 * ∆
Logic
Fine Flash
ADC 2
Folder 2
Vref + 1/4 * ∆
Fine Flash
ADC 1
Folder 1
Vref + 0/4 * ∆
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 35
Parallel Folder Outputs
0.5
F1
F2
F3
F4
0.4
0.3
• 4 Folders
• 16 Zero crossings
• à only 4 LSB bits
Folder Output
0.2
0.1
0
• Better resolution
• More folders
-0.1
-0.2
à Large complexity
-0.3
• Interpolation
-0.4
-0.5
0
1
2
3
4
5
Vin / ∆
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 36
Folding & Interpolation
Folder 4
Vref + 3/4 * ∆
Folder 3
Fine
Flash
ADC
Vref + 2/4 * ∆
Encoder
Folder 2
Vref + 1/4 * ∆
Folder 1
Vref + 0/4 * ∆
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 37
Folder / Interpolator Output
0.5
F1
F2
I1
I2
I3
0.4
F1
F2
I1
I2
I3
0.05
0.04
0.2
Folder / Interpolator Output
Folder / Interpolator Output
0.3
0.1
0
-0.1
0.03
0.02
0.01
0
-0.01
-0.02
-0.2
-0.03
1.45
-0.3
1.5
1.55
1.6
1.65
Vin / ∆
1.7
1.75
1.8
-0.4
-0.5
0
1
2
3
4
5
Vin / ∆
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 38
Folder / Interpolator Output
0.5
0.06
F1
F2
I1
I2
I3
Folder / Interpolator Output
0.3
F1
F2
I1
I2
I3
0.04
Folder / Interpolator Output
0.4
0.2
0.1
0.02
0
-0.02
-0.04
0
-0.06
1.5
-0.1
1.6
1.7
1.8
Vin / ∆
1.9
2
2.1
-0.2
-0.3
-0.4
-0.5
0
1
2
3
4
Vin / ∆
EECS 247 Lecture 20: Data Converters
5
Interpolate only
between closely
spaced folds to avoid
nonlinear distortion
© 2004 H.K. Page 39
A 70-MS/s 110-mW 8-b CMOS Folding
and Interpolating A/D Converter
Ref: B. Nauta and G. Venes, JSSC Dec 1985, pp. 1302-8
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 40
A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D Converter
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 41
A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D Converter
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 42
Pipelined ADCs
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 43
Pipelined A/D Converters
• Ideal Operation
• Errors and Correction
– Redundancy
– Digital Calibration
• Implementation
– Practical Circuits
– Stage Scaling
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 44
Block Diagram
Vin
Stage 1
B1 Bits
Vres1
Stage 2
B2 Bits
Vres2
MSB...
Stage k
Bk Bits
...LSB
Align and Combine Data
Digital output
(B1 + B2 + ... + Bk) Bits
• Idea: Cascade several low resolution stages to obtain
high overall resolution
• Each stage performs coarse A/D conversion and
computes its quantization error, or "residue"
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 45
Characteristics
• Number of components (stages) grows
linearly with resolution
• Pipelining
– Trading latency for conversion speed
– Latency may be an issue in e.g. control systems
– Throughput limited by speed of one stage → Fast
• Versatile: 8...16bits, 1...200MS/s
• Many analog circuit non-idealities can
be corrected digitally
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 46
Concurrent Stage Operation
φ1
φ2
Vin
acquire
convert
convert
acquire
Stage 1
B1 Bits
Stage 2
B2 Bits
...
...
Stage k
Bk Bits
CLK
φ1
φ2
φ1 ...
Align and Combine Data
Digital output
(B1 + B2 + ... + Bk) Bits
• Stages operate on the input signal like a shift register
• New output data every clock cycle, but each stage
introduces ½ clock cycle latency
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 47
Data Alignment
φ1
φ2
Vin
acquire
convert
convert
acquire
Stage 1
B1 Bits
Stage 2
B2 Bits
...
...
Stage k
Bk Bits
CLK
φ1
φ2
φ1 ...
+
CLK
Dout
+
CLK
CLK
• Digital shift register aligns sub-conversion
results in time
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 48
Latency
[Analog Devices, AD 9226 Data Sheet]
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 49
Pipelined ADC Analysis
• Ignore timing and use simple static model
Vin
Stage 1
B1 Bits
Vres1
Stage 2
B2 Bits
+
Vres2
Stage k
Bk Bits
+
Dout
• Let's first look at "two-stage pipeline"
– E.g.: Two cascaded 2-bit ADCs to get 4 bits of
total resolution
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 50
Two Stage Example
2-bit ADC
2-bit ADC
Vin
???
+
Dout= Vin + εq1
• Using only one ADC: Output contains large
quantization error
• "Missing voltage" or "residue" (-εq1)
• Idea: Use second ADC to quantize and add -εq1
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 51
Two Stage Example
2-bit ADC
Vin
2-bit DAC
“Coarse“
2-bit ADC
-
+
-εq1
“Fine“
− εq1+εq2
+
Dout= Vin+ εq1 − εq1+ εq2
• Use DAC to compute missing voltage
• Add quantized representation of missing voltage
• Why does this help? How about εq2 ?
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 52
Two Stage Example
−εq1
11
10
Vref1/22
Vref1 Vin
01
Vref2
Second ADC
“Fine“
00
00
01
10
11
First ADC
“Coarse“
• Fine ADC is re-used 22 times
• Fine ADC's full scale range needs to span only 1 LSB
of coarse quantizer
Vref 2
Vref 1
ε q2 = 2 = 2 2
2
2 ⋅2
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 53
Two Stage Transfer Function
Dout
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Vref1
Coarse
Bits
(MSB)
Vin
Fine
Bits
(LSB)
EECS 247 Lecture 20: Data Converters
© 2004 H.K. Page 54