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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 6, JUNE 2001
0.18-m CMOS 10-Gb/s Multiplexer/Demultiplexer
ICs Using Current Mode Logic with Tolerance to
Threshold Voltage Fluctuation
Akira Tanabe, Masato Umetani, Ikuo Fujiwara, Takayuki Ogura, Kotaro Kataoka, Masao Okihara,
Hiroshi Sakuraba, Member, IEEE, Tetsuo Endoh, Member, IEEE, and Fujio Masuoka, Fellow, IEEE
Abstract—A feedback MOS current mode logic (MCML) is
proposed for the high-speed operation of CMOS transistors.
This logic is more tolerant to the threshold voltage fluctuation
than the conventional MCML and is suitable for gigahertz
operation of deep-submicron CMOS transistors. Using this logic,
8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) ICs
for optical-fiber-link systems have been fabricated with 0.18- m
CMOS transistors. The ICs are faster than conventional CMOS
MUX and DEMUX ICs and their power consumption is less than
1/4 of that of the conventional 10-Gb/s MUX and DEMUX ICs
made using Si bipolar or GaAs transistors.
Index Terms—CMOSFETs, current-mode logic, optical communication.
I. INTRODUCTION
G
IGAHERTZ optical-fiber-link systems have become
more important because of the increasing demand for
high-speed communications. The key components of these systems are a multiplexer (MUX, parallel-to-serial converter) and
a demultiplexer (DEMUX, serial-to-parallel converter). These
ICs must handle high-frequency signals whose frequencies are
half of the data rate. Fast switching speed is therefore necessary.
ICs operating at speeds greater than 10 Gb/s using GaAs
MESFETs, GaAs HBTs, Si bipolar transistors, SiGe bipolar
transistors, and Si BiCMOS transistors have been reported
[1]–[6]. The power consumption of these ICs, however, is
relatively large ( 0.4 W) because their supply voltage is high
and their penetration current is large.
On the other hand, CMOS transistors have the advantages of
low power consumption and low cost. They have nonetheless
rarely been used in such high-speed systems because their opManuscript received September 1, 2000; revised February 2, 2001.
A. Tanabe is with Silicon Systems Research Labs, NEC Corporation,
Kanagawa 229-1198, Japan (e-mail: a-tanabe@ak.jp.nec.com), and also with
the Telecommunications Advancement Organization of Japan, Sendai Research
Center, Miyagi, Japan.
M. Umetani, I. Fujiwara, K. Kataoka, and M. Okihara are with the Telecommunications Advancement Organization of Japan, Sendai Research Center,
Miyagi, Japan.
T. Ogura is with Sharp Corporation, Nara, Japan, and also with the Telecommunications Advancement Organization of Japan, Sendai Research Center,
Miyagi, Japan.
H. Sakuraba, T. Endoh, and F. Masuoka are with the Research Institute of
Electrical Communication, Tohoku University, Miyagi 980-8577, Japan, and
also with the Telecommunications Advancement Organization of Japan, Sendai
Research Center, Miyagi, Japan.
Publisher Item Identifier S 0018-9200(01)04125-7.
eration speed is too low. Recently, several CMOS communication ICs [transceiver, receiver, multiplexer, demultiplexer, and
phase-locked loop (PLL)] with data rates greater than 1 Gb/s
have been reported [7]–[16]. For example, an 8-Gb/s transceiver
IC using multilevel signaling (four levels) has been reported
[16]. That chip, however, is for serial links using copper cables
and is not applicable to optical-fiber-link systems because of
its multilevel signaling. A 4-Gb/s chip in 0.6- m CMOS using
oversampling technique has been reported [12], but the error
rate of this chip is not small because of the oversampling algorithm. The maximum data rates of the other chips, using CMOS
flip-flop circuits, are limited by the toggle frequency of CMOS
logic. For example, the maximum clock frequency of a 0.18- m
CMOS chip is 3.1 GHz [15] and that of a 0.15- m CMOS chip
is 3.0 GHz [9].
A differentially operating logic such as the MOS current
mode logic (MCML) [17] is capable of faster operation than
the conventional CMOS logic and would be suitable for use
in 10-Gb/s systems. The maximum operation frequency of the
MCML, however, is reduced by the fluctuation of the threshold
) of the differential pair transistors [17]. Because
voltages (
fluctuation increases as the gate length decreases,
this
it becomes a serious problem for deep-submicron CMOS
transistors.
To overcome this problem, a feedback MCML is proposed.
fluctuation than is the
This logic is more tolerant to the
conventional MCML. In this paper, the advantages of the feedback MCML are discussed, then 10-Gb/s multiplexer and demultiplexer ICs with this logic are described. These chips were
fabricated using 0.18- m CMOS transistors.
II. MCML CIRCUITS
Fig. 1 shows inverters of the CMOS logic and the conventional MCML [17]. The CMOS logic has the advantage of low
power consumption, but its operation is relatively slow. For
example, the maximum toggle frequency of a conventional
0.18- m CMOS inverter is only about 3.5 GHz.
Simulated inverter delay time as a function of fanout and
power consumption as a function of a operation frequency for
the CMOS logic and the MCML are shown in Fig. 2. The data
plotted there was obtained by SPICE simulations using the parameters of 0.18- m CMOS transistors with a 1.8-V supply
0018–9200/01$10.00 ©2001 IEEE
TANABE et al.: 0.18- m CMOS 10-Gb/s MULTIPLEXER/DEMULTIPLEXER ICS
989
(a)
(a)
Fig. 1.
(b)
Inverter circuits of the (a) CMOS logic and (b) MCML.
(b)
Fig. 3. Diagram of the MCML output waveforms. (a) is without and (b) is with
V fluctuation.
(a)
is the same as the drain current of the current source transistor
. Since MC1 operates at saturation region, this drain
MC1
, and the
current is mainly determined by the gate bias
contribution of the voltage at the common-source node NC is
small. Moreover, the operation frequency has little effect on
the voltage at NC because of the differential operation of the
MCML. Therefore, the power consumption of the MCML is
nearly independent of the operation frequency.
In Fig. 1, there are two MOSFETs in the CMOS logic and
five in the MCML. In addition, the MCML requires two lines for
each signal. Therefore, a chip area with a given function is about
two to four times larger in the MCML than in the CMOS logic.
However, in the gigahertz frequency range, the power consumption of the CMOS logic become larger than that of the MCML,
as shown in Fig. 2(b). This means that the MCML is suitable for
low-power operation in the gigahertz frequency range.
III. EFFECT OF THE
FLUCTUATION
(b)
Fig. 2. Comparison of the MCML and CMOS logic. (a) Delay time as a
function of fanout. (b) Power consumption as a function of operation frequency.
SPICE simulation were performed using the parameters of 0.18-m CMOS
transistors.
voltage. The MCML is faster than the CMOS logic because of
its smaller input capacitance and smaller signal amplitude.
Because the CMOS logic uses power only when charging and
discharging, its power consumption is generally smaller than
that of the MCML. The power consumption of this CMOS logic
is the product of the operation frequency and the charging and
discharging power per unit switching. On the other hand, the
power consumption of the MCML is the sum of the penetraand MN2
in Fig. 1(b), which
tion currents of MN1
The
fluctuation of MOSFETs is caused by the fluctuation of the gate-oxide thickness, gate length, etc. The random
flucplacement of the channel dopant [18] also causes the
tuation. If the gate width is large enough ( 1 m), the effect of
the random placement is not severe. Because of the severe short
lowering, the
fluctuation of
channel effect with the
deep-submicron MOSFETs becomes great because of the fluctuation of the gate length.
Fig. 3 shows diagrams of the output waveforms of the MCML
fluctuainverter. Fig. 3(a) shows the waveform without the
fluctuation. As shown
tion and Fig. 3(b) shows that with the
values of the differential pair transistors
in Fig. 3(b), if the
[MN1 and MN2 in Fig. 1(b)] differ, the output waveform will
be unbalanced.
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The differential pair transistors in the MCML operate in the
are generally given
saturation region, so their drain currents
by
(1)
where
mobility;
gate capacitance;
gate width;
gate length.
Then the transconductance
is given by
(2)
and
(a)
is given by
(3)
The dc gain
of the MCML circuit is given by
(4)
is the total load resistance of MN1 or MN2 and the
Here,
input signal amplitude is assumed to be much smaller than the
(small-signal analysis). If the fluctuation of the
gate voltage
is assumed to be much smaller than the
threshold voltage
, the bias offset voltage
[see Fig. 3(b)] is
gate voltage
given by
(b)
(5)
increases, the minimum differential output voltage
[see Fig. 3(b)] decreases and the operation of the circuit
is proportional to the dc gain
becomes faulty. From (5),
of the MCML circuit. Therefore, a small dc gain is preferable.
fluctuation will also affect the output amplitude of
The
the MCML circuit. This effect is compensated for by the differential operation, because the common-mode rejection ratio
(CMRR) of the MCML circuit is large enough.
Fig. 4. Inverter circuits of the (a) conventional MCML and (b) feedback
MCML.
If this
Here,
is the dc gain of this circuit and is the pole of
the circuit. The pole is a function of the load resistance and load
capacitance of the transistors (MN1 or MN2 in Fig. 4) [19].
If the feedback transistors are assumed to be purely resistive,
is given by
the gain of the feedback MCML circuit
IV. FEEDBACK MCML CIRCUIT
The problem due to the
fluctuation can be reduced by
using a feedback MCML. Fig. 4 shows the inverters of the conventional MCML and the feedback MCML. In the feedback
MCML, transistors MF1 and MF2 are added as feedback resistances. The effect of those feedback resistances for the fluctuation is described below.
Because the MCML circuit is a simple source-coupled pair
at a frequency
circuit, differential-mode voltage gain
of the conventional MCML circuit is generally given by [19]
(6)
(7)
is a feedback function and represents the gain of the
Here,
feedback transistors (MF1 and MF2) [19]. If we define loop gain
, then
is given by
(8)
, (8) gives the gain of the conventional MCML cirWhen
, and when
, it gives the gain of the feedback
cuit,
.
MCML circuit,
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991
Fig. 5. Simulated frequency responses of the conventional and feedback
MCML inverters. The vertical axis is the voltage gain of differential mode and
common mode.
1
Fig. 6. Calculated maximum tolerable V
fluctuation V
of the
conventional and feedback MCML inverters as a function of the frequency.
The values shown are normalized by the amplitude of the input signal.
Fig. 5 shows the simulated differential-mode and
common-mode voltage gains of the conventional and feedback
MCML inverters as a function of the frequency using 0.18- m
CMOS parameters. The bandwidth of the feedback MCML inis wider than that of the conventional MCML
verter
. If we design
,
inverter
is a maximum operation frequency, the dc gain
where
of the feedback MCML inverter will be less than that of the
.
conventional MCML inverter, that is,
fluctuation,
If we assume the maximum tolerable
, is the
at which
becomes
[see
is given by
Fig. 3(b)], and
(9)
Here,
is the amplitude of the input signal. Using (5)
(10)
is then given by (11), shown at the bottom
Using (8),
and
,
increases
of the page. If
curves, calculated using
with . Fig. 6 shows the
Fig. 7. Circuits of the D-type flip-flop using (a) the CMOS logic and (b) the
feedback MCML.
(11), for the circuits shown in Fig. 4. The
of the feedback MCML is larger than that of the conventional MCML at
frequencies above several gigahertz because of its wider bandwidth. This means that the feedback MCML is more tolerant to
fluctuation than is the conventional MCML.
the
fluctuation of the paired feedback transistors MF1
The
and MF2 also give rise to an unbalanced output amplitude. However, by making the gate length of feedback transistors greater
fluctuation
than that of the differential pair transistors, the
of MF1 and MF2 can be suppressed. For example, in the fabricated chips described below, 0.25- m gate length transistors
were used as feedback transistors although 0.18- m transistors
were used for differential pair transistors.
V. MCML FLIP-FLOP
Fig. 7 shows D-type flip-flops (D-F/Fs) using the CMOS
(sampling
logic and the feedback MCML. When
mode), these flip-flops store the input data , and when
(holding mode), they hold that internal data regardless of any
(11)
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 6, JUNE 2001
Fig. 8. Simulated relation between the V fluctuation and the maximum data
rate of 1:2 DEMUXs using conventional and feedback MCMLs.
(a)
Fig. 9.
Block diagram of the 1:2 DEMUX.
input data. When
, the differential pair MN1 and
MN2 are activated and the gain of these circuits is given by (8).
, the differential pair MN3 and
In contrast, when
MN4 are activated and the output signals are constant. There, the effect of the
fluctuation
fore, since
for the feedback MCML circuit at this mode is small.
Fig. 8 shows a simulated relation (using 0.18- m CMOS paand the maximum data rate of the 1:2
rameters) between
DEMUX circuits (shown in Fig. 9), composed of conventional
MCMLs and feedback MCMLs. The maximum data rate here is
defined as the highest input data rate at which the output pattern
is correct, regardless of the output data amplitude. Fig. 8 shows
fluctuation twice as
that the feedback MCML can tolerate
large as that tolerated by the conventional MCML.
(b)
VI. MULTIPLEXER AND DEMULTIPLEXER CIRCUITS
Using feedback MCMLs, MUX and DEMUX ICs for optical-fiber-link systems have been fabricated. Fig. 10(a) and (b)
shows block diagrams of the 1:8 DEMUX and 8:1 MUX circuits. Each is a tree-type circuit made up of 1:2 DEMUX or
2:1 MUX circuits. Since each utilizes both the rising and falling
edges of the input clock, the operation frequency of these circuits at 10-Gb/s data rate is 5 GHz. Feedback MCMLs were
used for the first 1:2 DEMUX, the final 2:1 MUX, and the first
Fig. 10. Block diagram of the circuits of the fabricated (a) 1:8 DEMUX and
(b) 8:1 MUX.
1/2 dividers whose clock frequency is 5 GHz. The 2:1 MUX has
a MCML selector circuit similar to the D-F/F.
In these circuits, MCMLs are only used in the 5-GHz blocks.
This is because the power consumption [shown in Fig. 2(b)] of
the CMOS logic and the MCML at 2.5 GHz is not very different, thus CMOS F/Fs can operate at up to 2.5 GHz and the
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TABLE I
SPECIFICATIONS OF MOSFETS
(a)
(a)
(b)
Fig. 12. Measured waveforms of (a) 1:8 DEMUX and (b) 8:1 MUX at 10-Gb/s
data rate.
The emitter-coupled logic (ECL) level interfaces were used
at the input and output terminals. Each input terminal had an
on-chip 50- terminator made of polysilicon.
VII. FABRICATION
A 0.18- m CMOS process was used in the fabrication of
these ICs. Table I lists the major specifications of the transistors.
The gate-oxide thickness was 3.8 nm and a Co salicide process
was used to reduce the gate and source–drain sheet resistances
. The number of metal layers was two. The
to about 10
impedance of the on-chip signal lines was not adjusted. Fig. 11
shows photographs of the fabricated 1:8 DEMUX and 8:1 MUX
mm .
ICs. The chip area of each chips was
(b)
Fig. 11.
1:5 mm .
Chip photographs. (a) 1:8 DEMUX. (b) 8:1 MUX. Each chip is 1:5
2
chip area of the CMOS F/F is smaller than that of the MCML
F/F. Therefore, to optimize power consumption and chip area
of these circuits, a hybrid structure of the CMOS logic and the
MCML is suitable.
VIII. MEASUREMENTS
The measurement of these chips were performed on-wafer
using air coplanar probes. Fig. 12(a) shows the measured waveforms of the 1:8 DEMUX. The supply voltage was 2.0 V, input
clock was 5 GHz, and the input pattern was a 10-Gb/s 2
pseudorandom bit sequence (PRBS). The upper waveform is the
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 6, JUNE 2001
TABLE II
CHARACTERISTICS OF THE DEMUX
TABLE III
CHARACTERISTICS OF THE MUX
Fig. 13. Data rate and power consumption of the fabricated (a) 1:8 DEMUX
and (b) 8:1 MUX. The power consumption does not include the output buffers.
Fig. 14.
Power-delay products of reported MUX and DEMUX circuits.
input clock (5 GHz), the middle waveform is the 1/4-divided
output clock (1.25 GHz), and the lower waveform is an eye diagram of the output data (1.25 Gb/s). The error rate was less than
10 , and the timing margin between input data and clock was
about 63 ps. Fig. 12(b) shows the measured waveforms of the
8:1 MUX at a 2.2-V supply voltage. The upper waveform is an
eye diagram of the output data (10 Gb/s) and the lower one is
the input clock (5 GHz). The eye opening of the output data was
610 mV, 72 ps.
The maximum data rate and power consumption of the 1:8
DEMUX and the 8:1 MUX as functions of the supply voltage
are shown in Fig. 13(a) and (b), respectively. They were 10 Gb/s,
48 mW (at 2.0 V) for the DEMUX and 10.2 Gb/s, 112 mW (at
2.2 V) for the MUX. The power consumption was measured at
the maximum data rate, and the values do not include the power
consumption of the ECL output buffer. Tables II and III list the
characteristics of the DEMUX and the MUX. Values for the
DEMUX were not measured at data rates over 10 Gb/s because
of the limitations in the method of measurement.
In Fig. 12(b), the jitter of the MUX’s output waveform is
not small. This is because the bandwidth of the output buffer
[shown in Fig. 10(b)] is insufficient. Since the output data pattern “101 010…” has frequency components up to 5 GHz while
the output data pattern “110 011…” has that up to 2.5 GHz, the
output amplitude of the former signal becomes smaller than that
of latter and this difference in amplitude creates jitter. This jitter
can be minimized by improvement of the output buffer.
Fig. 14 shows the power-delay products of the reported MUX
and DEMUX circuits. The MUX and DEMUX chips fabricated
in this work are faster than conventional CMOS logic chips
[8]–[12], [14]–[16], and the power consumption is less than 1/4
of that of 10-Gb/s MUX and DEMUX Si bipolar or GaAs transistor chips [1]–[6]. This is because of the MCML–CMOS hybrid structure. As shown in Fig. 2(b), the power consumption of
TANABE et al.: 0.18- m CMOS 10-Gb/s MULTIPLEXER/DEMULTIPLEXER ICS
the MCML is much smaller than that of the CMOS logic in the
gigahertz frequency range. Therefore, the power consumption
of the first 1:2 DEMUX and the final 2:1 MUX, which operate
at 5 GHz, is comparatively low. This result shows that this hybrid structure is suitable for high-speed communication ICs.
IX. CONCLUSION
The feedback MCML has been proposed for high-speed
operation of CMOS transistors. This logic is more tolerant to
threshold voltage fluctuation than the conventional MCML and
is suitable for gigahertz operation of deep-submicron CMOS
transistors.
Using this logic, the 1:8 DEMUX and 8:1 MUX ICs for
optical-fiber-link systems have been fabricated with 0.18- m
CMOS process. These ICs are faster than conventional CMOS
MUX and DEMUX ICs and their power consumption is less
than 1/4 of that of conventional 10-Gb/s MUX and DEMUX
Si bipolar or GaAs transistor ICs. This result shows that the
MCML-CMOS hybrid structure is suitable for high-speed
operation of CMOS transistors.
ACKNOWLEDGMENT
The authors would like to thank F. Shirai and J. Nishizawa for
encouragement.
REFERENCES
[1] K. Ishida, H. Wakimoto, K. Yoshikawa, M. Konno, S. Shimizu, Y. Kitaura, K. Tomita, T. Suzuki, and N. Uchitomi, “A 10-GHz 8 B-multiplexer/demultiplexer chip set for SONET STS-192 system,” IEEE J.
Solid-State Circuits, vol. 26, pp. 1936–1943, Dec. 1991.
[2] M. Bagheri, D. T. Kong, J. Hacker, K. Schneider, and J. Chow, “10-Gb/s
framer/demultiplexer IC for SONET STS192 applications,” in Proc.
IEEE CICC, 1995, pp. 427–429.
[3] S. Shioiri, M. Soda, T. Hashimoto, F. Sato, and K. Emura, “A 10-Gb/s
SiGe bipolar framer/demultiplexer for SDH systems,” in ISSCC Dig.
Tech. Papers, 1998, pp. 202–203.
[4] L. I. Anderson, B. G. R. Rudberg, P. T. Lewin, M. D. Reed, S. M. Planner,
and S. L. Sundaram, “Silicon bipolar chipset for SONET/SDH 10-Gb/s
fiber-optic communication links,” IEEE J. Solid-State Circuits, vol. 30,
pp. 210–218, Mar. 1995.
[5] J. Hauenschild, C. Dorschky, T. W. von Mohrenfels, and R. Seitz, “A
10-Gb/s BiCMOS clock and data recovering 1:4-demutiplexer in a standard plastic package with external VCO,” in ISSCC Dig. Tech. Papers,
1996, pp. 202–203.
[6] N. Yoshida, M. Fujii, T. Atsumo, K. Numata, S. Asai, M. Kohno, H.
Oikawa, H. Tsutsui, and T. Maeda, “Low-power-consumption 10-Gb/s
GaAs 8:1 multiplexer/1:8 demultiplexer,” in IEEE GaAs IC Symp., 1997,
pp. 113–116.
[7] A. Tanabe, M. Umetani, I. Fujiwara, T. Ogura, K. Kataoka, M. Okihara,
H. Sakuraba, T. Endoh, and F. Masuoka, “A 10-Gb/s demultiplexer IC in
0.18-m CMOS using current mode logic with tolerance to the threshold
voltage fluctuation,” in ISSCC Dig. Tech. Papers, 2000, pp. 62–63.
[8] S. Yasuda, Y. Ohtomo, M. Ino, Y. Kado, and T. Tsuchiya, “3-Gb/s CMOS
1:4 MUX and DEMUX ICs,” IEICE Trans. Electron., vol. E78-C, pp.
1746–1753, Dec. 1995.
[9] M. Kurisu, M. Kaneko, T. Suzaki, A. Tanabe, M. Togo, A. Furukawa,
T. Tamura, K. Nakajima, and K. Yoshida, “2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mW bit-interleaved 8:1 multiplexers,” in
ISSCC Dig. Tech. Papers, 1996, pp. 122–123.
[10] A. Tanabe, M. Togo, M. Soda, H. Tezuka, T. Suzaki, A. Furukawa,
and K. Emura, “High-performance CMOS for gigahertz communication
IC,” in Symp. VLSI Tech. Dig. Tech. Papers, 1996, p. 134.
[11] M. Soda, H. Tezuka, S. Shioiri, A. Tanabe, A. Furukawa, M. Togo, T.
Tamura, and K. Yoshida, “A 2.4-Gb/s CMOS clock recovering 1:8 demultiplexer,” in Symp. VLSI Circuits Dig. Tech. Papers, 1997, pp. 69–70.
995
[12] C. K. Yang, R. Farjad-Rad, and M. Horowiz, “A 0.6-m CMOS 4-Gb/s
transceiver with data recovery using oversampling,” in Symp. VLSI Circuits Dig. Tech. Papers, 1997, pp. 71–72.
[13] A. Tanabe, M. Soda, Y. Nakahara, T. Tamura, K. Yoshida, and A. Furukawa, “A single-chip 2.4-Gb/s CMOS optical receiver IC with low
substrate crosstalk preamplifier,” in ISSCC Dig. Tech. Papers, 1998, pp.
304–305.
[14] M. Fukaishi, N. Nakamura, M. Sato, T. Tsutsui, S. Kishi, and M.
Yotsuyanagi, “A 4.25-Gb/s CMOS fiber channel transceiver with
asynchronous binary tree-type demultiplexer and frequency conversion
architecture,” in ISSCC Dig. Tech. Papers, 1998, pp. 306–307.
[15] K. Nakamura, M. Fukaishi, H. Abiko, A. Matsimoto, and M. Yotsuyanagi, “A 6-Gb/s CMOS phase-detecting DEMUX module using
half-frequency clock,” in Symp. VLSI Circuits Dig. Tech. Papers, 1998,
pp. 196–197.
[16] R. Farjad-Rad, C. K. Yang, M. Horowitz, and T. Lee, “A 0.3-m CMOS
8-Gb/s 4-PAM serial link transceiver,” in Symp. VLSI Circuits Dig. Tech.
Papers, 1999, pp. 41–44.
[17] M. Yamashina and H. Yamada, “An MOS current mode logic (MCML)
circuit for low-power sub-gigahertz processors,” IEICE Trans. Electron.,
vol. E75-C, pp. 1181–1187, Oct. 1992.
[18] K. Takeuchi, T. Tatsumi, and A. Furukawa, “Channel engineering for the
reduction of random-dopant-placement-induced threshold voltage fluctuation,” in IEDM Tech. Dig., 1997, pp. 841–844.
[19] P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated
Circuits. New York: Wiley, 1984, ch. 9.
Akira Tanabe was born in Osaka, Japan, in 1963. He
received the B.E. and M.E. degrees in electrical engineering from Kyoto University, Kyoto, Japan, in 1987
and 1989, respectively, and the Ph.D. degree in electrical engineering from Tohoku University, Sendai,
Japan, in 1998.
In 1989, he joined NEC Corporation, where he
has engaged in the research and development of
high-density DRAMs and scaled silicon MOSFETs.
Since 1997, he has also been engaged in the research
and development of high-speed communication
ICs in the Telecommunications Advancement Organization of Japan, Sendai
Research Center, Miyagi, Japan.
Dr. Tanabe is a member of the Japan Society of Applied Physics and Institute
of Electronics, Information and Communication Engineers.
Masato Umetani was born in Kobe, Japan, in 1963.
He received the B.E. degree in material engineering
from Osaka University, Osaka, Japan, in 1987.
In 1987, he joined Oki Electric Industry Company,
Ltd., where he was engaged in the research and development of high-speed silicon bipolar devices. Since
1997, he has also been engaged in the research and
development of high-speed communication ICs in the
Telecommunications Advancement Organization of
Japan, Sendai Research Center, Miyagi, Japan.
Ikuo Fujiwara received the B.S. degree in physics
and the M.S. degree in physical engineering from the
University of Tsukuba, Ibaragi, Japan, in 1989 and
1992, respectively.
He joined the Toshiba Research and Development
Center, Kawasaki, Japan, in 1992, where he has
been engaged in research on GaAs MESFET ICs
for high-frequency mobile communication systems.
From 1997 to 1999, he was a Research Scientist
at the Telecommunications Advancement Organization of Japan, Sendai Research Center, Miyagi,
Japan, where he was engaged in research and development on high-speed
communication ICs. He has been with the Toshiba Advanced LSI Technology
Laboratory, Kawasaki, Japan, since 1999, where he is currently working on the
ultra-short-channel CMOS device with high-k gate insulators.
Mr.Fujiwara is a member of the Japan Society of Applied Physics and the
Institute of Electronics, Information and Communication Engineers.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 6, JUNE 2001
Takayuki Ogura was born in Osaka, Japan, in 1970.
He received the B.S. degree from Nagoya University,
Nagoya, Japan, in 1995.
He joined Advanced Technology Research
Laboratories, Sharp Corporation, Nara, Japan, in
1995. From 1995 to 1997, he was engaged in the
research and development of low-power LSIs in
the Advanced Technology Research Laboratories.
From 1997 to 1999, he was engaged the research of
high-speed MOS devices with the Telecommunications Advancement Organization of Japan, Sendai
Research Center, Miyagi, Japan. He is currently with the Advanced Technology
Research Laboratories, Sharp Corporation.
Kotaro Kataoka was born in Osaka, Japan, in 1971.
He received the M.S. degree from the Department
of Chemistry, University of Tokyo, Tokyo, Japan, in
1996.
From 1996 to 1998 and currently, he has been
engaged in the development of low-power LSIs with
the Advanced Technology Research Laboratories,
Sharp Corporation, Nara, Japan. From 1998 to 1999,
he researched high-speed MOS devices with the
Telecommunications Advancement Organization of
Japan, Sendai Research Center, Miyagi, Japan.
Masao Okihara received the B.S. and M.S. degrees
from Ehime University, Ehime, Japan, in 1986 and
1990, respectively.
He joined Oki Electric Industry Company, Ltd.,
in 1990, and has been engaged in the research
and development of VLSI process technologies
and analysis technologies for materials utilizing Si
semiconductor devices. He is currently with the
Telecommunications Advancement Organization
of Japan, Sendai Research Center, Miyagi, Japan,
where he has been engaged in the research of
high-speed Si LSI devices for opto-electronics telecommunications.
Hiroshi Sakuraba (M’00) was born in Akita, Japan,
in 1961. He received the B.E., M.E., and Ph.D. degrees in electrical engineering from Tohoku University, Sendai, Japan, in 1987, 1989, and 1992, respectively.
From 1992 to 1996, he was a Research Associate with the Faculty of Engineering of Tohoku
University, where he was engaged in research of
the surface reaction mechanism of semiconductor
crystal growth. Since 1996, he has been with the
Research Institute of Electrical Communication,
Tohoku University. His current research interest is the device and process
technology of ULSI.
Dr. Sakauraba is a member of the Institute of Electronics, Information and
Communication Engineers (IEICE).
Tetsuo Endoh (M’89) was born in Tokyo, Japan, in
1962. He received the B.S. degree in physics from
the University of Tokyo in 1987, and the Ph.D. degree in electronic engineering from Tohoku University, Sendai, Japan, in 1995.
He joined the Research and Development Center,
Toshiba Corporation, Kawasaki, Japan, in 1987,
where he was engaged in research on CMOS device
design. Since 1988, he has been engaged in research
on high-density flash EEPROMs and reliability of
flash EEPROMs at the ULSI Research Laboratories
Research and Development Center, Toshiba Corporation. He was a Lecturer
of the Research Institute of Electrical Communication, Tohoku University, in
1995, where he became an Assistant Professor in 1997. He has been engaged
in research on CMOS device design, low-power and high-speed LOGIC
technology, and clean room technology.
Dr. Endoh is a member of the Institute of Electronics, Information and Communication Engineers (IEICE) and the Japan Society of Applied Physics.
Fujio Masuoka (A’88–SM’94–F’95) was born in
1943 in Gunma, Japan. He received the B.E., M.E.
and Ph.D. degrees in electrical engineering from
Tohoku University, Sendai, Japan, in 1966, 1968,
and 1971, respectively.
In 1971, he joined the Toshiba Research and
Development Center, Kawasaki, Japan, where in
1972 he developed the stacked-gate-avalanche injection-type MOS read-only memory (SAMOS), which
is the origin of current EPROM and flash memory.
In 1976, he developed the dynamic memory cell
with double poly-Si structure. In 1977, he moved to Toshiba Semiconductor
Business Division, where he developed 1-Mbit DRAM, and in 1980, he applied
for the flash memory patent for the first time. In 1984, he presented flash
memory for the first time at the IEDM, and again in 1985 at the ISSCC. In
1987, he returned to Toshiba Research and Development Center, where he
began to develop NAND structured flash memory, which was presented in 1987
at the IEDM. He moved to Tohoku University as a Professor in 1994. He has
authored and co-authored approximately 150 papers. He has 170 registered
patents in the U.S., Germany, France, and the U.K., 100 registered patents in
Japan, and 71 patents pending.
Dr. Masuoka received the Watanabe Award and the National Invention Award
in 1977 and 1978, respectively. He also received the 1997 IEEE Morris N. Liebmann Memorial Award and the Ichimura Award for the development of flash
memory in 2000. He is a member of the Institute of Electronics, Information
and Communication Engineers (IEICE).