Figure No.
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1.4
1.5
1.6
1.7
1.8
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2 . 1 5
2 . 1 6
2 . 1 7
Details Page
Basic two converter Interline Power Flow Controller (IPFC) scheme 4
Indian map showing the location of the FACTS system being installed and other electrical grids in the region
Initial stages of the project at Raipur
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21
Pulse waveform 24
Circuit model to be Modeled with Simpower systems
Simulink Window
Parallel RLC branch
Simple circuit model of transmission line
Simple circuit model of transmission line with measurement block
Interfacing of electrical circuit using Simulink
Power flow relation
Control of power flow between regions
Power in Normal Flow
Power flow with regulator
Upgrading of series capacitor in TCSC
Power oscillations damped out by means of TCSC
Overview of Fact controllers
Basic two machine system with synchronous voltage source
Functional representation of the synchronous voltage source based on a voltage sourced converter
TCSC with thyristor switched capacitance
TCSC with fixed capacitor
Static var compensator
Typical configuration of SVC
TCR current and firing angle
TCS current and firing angle
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5.
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2.18 Static Compensator (STATCOM) and voltage /current characteristic 59
Basic circuit arrangement of Unified Power Flow Controller
Phasor diagrams illustrating the transmission control capabilities of the
Unified Power Flow Controller
(a)simple two machine system, (b) related voltage phasors, (c)real and reactive power vs. transmission angle, and (d) sending end and receiving end reactive power vs. transmission angle
General schematic of IPFC
IPFC prime converter and corresponding phasor diagram
Q-P diagram illustrating the operation of IPFC variation of receiving end real and reactive power as a function ofthe injected compensating voltage in line 1
Basic control scheme for a two converter IPFC
Waveforms showing the operation of the IPFC with the " prime"
Converter I emulating real (resistive), capacitive, and inductive compensations of line 1
Waveforms showing the operation of Converter 2providing real power demand of Converter 1 and capacitive series compensation for
Line 2
Illustration of the operation of a two-converter IPFC by coordinated phasor diagrams ans P-Q plots.
Real and reactive power in lines 1 and 2 when the lPFC is controlling the real power in line 1 at unity power factor and maintaining constant real power flow in line2
Block diagram of UPFC
Equivalent Circuit of UPFC
Conceptual representation of the UPFC in two machines power system
Range of transmittable real power P and receiving end reactive power demand Q vs 6
Phasor diagram representation of the UPFC
Variation of the receiving end
- real and reactive power and the active and reactive power supplied by the UPFC, with the angular rotation of the injected voltage phasor)
Six bus system without compensator
Voltage across load-1,load-2, and load-3
Reactive power across load-1 , load-2, and load-3
Six bus system with one shunt capacitor
Voltage across load-1,load-2 and load-3

4.4(f)
4.4(g)
4.4(h)
4.4(i)
5. 1
3.7 (c)
3.8(a)
3.8(b)
3.8 (c)
3.9(a)
3.9(b)
3.9(c)
3.9(d)
4.1 (a)
4.1 (b)
4.2(a)
4.2(b)
4.3(a)
4.3(b)
4.3(c)
4.3(d)
4.4(a)
4.4(b)
4.4(c)
4.4(d)
4.4(e)
Reactive Power across load-1, loadd and load-3
Six bus system with three capacitors
Voltage across load-1,load-2, and load3
Reactive power across load-1, load-2, and load3
Circuit model with UPFC
Model of UPFC
Voltage across load-], load-2, and load-3
Reactive power across load-1, load-2, and load-3
Line without series compensation
Line with series compensation
Line without shunt compensation
Line with shunt compensation
Uncompensated System
Load Voltage Waveform of Line - 1 and Line - 2
Real Power Waveforms of Line - 1 and Line - 2
Reactive Power Waveforms of Line - I and Line - 2
Compensated System of 33KV and 32KV
Load Voltage Waveform across Line - 1 and Line - 2 at Alpha = 0
Degree
Real Power Waveform at Alpha = 0 Degree
Reactive Power Waveform at Alpha = 0 Degree
Driving Pulses
Inverter Output Without Filter
Inverter Outpur With Filter
Firing angle vs Real Power
Firing angle vs Reactive Power
Simplified schematic of the IPFC model
Basic Two-inverter Interline Power Flow Controller
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5.6(b)
5.6(c)
5.6(d)
6.1
6.2
6.3
6.4
6.5
6.6
6.7 (a)
6.7 (b)
6.8
6.9
6.10
5.4(a)
5.4(b)
5.4(c)
5.4(d)
5.4(e).
5.4(f).
5.5(a)
5.5(b)
5.6(a)
6.1 1
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5 3.
Phasor diagram of System, variation of the receiving end real and reactive power and the compensating real and reactive power, with the angular rotation of the injected voltage phasor
4-bus system with equal loads and different voltages
4-bus system with equal loads and different voltages
(i) Current through line 1, (ii) Receiving end voltage
Real and reactive powers in Line-l
Voltage of Line-2 with sag
Real and reactive powers in Line-2
4-Bus system with IPFC
Rectifier Inverter subsystem
Model for Closed loop system
(i) Voltage across load-1 , and load-2
FFT analysis without LC filter
FFT analysis with LC filter
Power circuit
Block diagram of 8 bit microcontroller 8 9 ~ 2 0 5
Pin diagram of AT89C205 1
Optocouplers
Pin Diagram
Simple model of an N-channel enhancement type MOSFET
Overall Control Circuit
Top view of Hardware
Ac input voltage
Rectifier output voltage
Driving pulses for inverter
Load voltage waveform after compensation
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