Fatih University
Electrical and Electronics Engineering Department
EEE 316 - Communications I
EXPERIMENT 6
FM DEMODULATORS
6.1 OBJECTIVES
1. Studying the principle of phase-locked loop.
2. Understanding the characteristics of the PLL LM565.
3. Demodulating FM signal using PLL.
6.2 PRELIMINARY WORK
Read chapter 5 in the textbook.
6.3 EQUIPMENT AND MATERIALS
The equipment list that will be used in this experiment is shown in Table 6.1. Before
starting the experiment, record the model, serial number and office stock number of the
equipment that will be used throughout the experiment. Also, record any damages.
Table 6.1 Equipment list for experiment 6.
Item
Equipment
No
Digital Oscilloscope (DO)
1
Function Generator
2
DC Power Supply
4
Connecting Probes and Cables
5
LM565 PLL Circuit
6
LM566 FM Modulator Circuit
7
Record of damages or other comments:
Model
Serial No
Office Stock
No
6.4 THEORY
Frequency demodulator, also called frequency discriminator, is a circuit, which
converts instantaneous frequency variations to linear voltage changes. There are many types
of circuit used in communication system such as FM to AM conversion, balanced, and
phase-shift discriminators and phase-locked loop (PLL) frequency demodulator. In this
experiment we will introduce the operations of PLL frequency demodulator and FM to
AM conversion discriminator.
EEE 316 - Communications I
Experiment 6
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6.4.1 Phase-Locked Loop (PLL) operation
The PLL is an electronic feedback control system, as illustrated by the block diagram
in Fig. 6.1, of locking the output and input signals in good agreements in both frequency and
phase. In radio communication, if a carrier frequency drifts due to transmission, the PLL in
receiver circuit will track the carrier frequency automatically.
Figure 6.1 PLL block diagram.
The PLL in the following experiments is used in two different ways: (1) as a
demodulator, where it is used to follow phase or frequency modulation and (2) to track a
carrier signal which may vary in frequency with time. In general, a PLL circuit includes the
following block diagrams:
a) Phase Detector (PD)
b) Low Pass Filter (LPF)
c) Voltage Controlled Oscillator (VCO)
The phase detector within the PLL locks at its two inputs and develops an output that
is zero if these two input frequencies are identical. If the two input frequencies are not
identical, then the output of detector, when passed through the low-pass filter removing the ac
components, is a DC level applied to the VCO input. This action closes the feedback loop
since the dc level applied to the VCO input changes the VCO output frequency in an attempt
to make it exactly match the input frequency. If the VCO output frequency equals the input
frequency, the PLL has achieved lock, and the control voltage will be zero for as long as the
PLL input frequency remains constant. The parameters of PLL shown in Fig. 6.1 are as
follows:
K d = phase detector gain in volts/radian
K a = amplifier gain in volt/volt
K o = VCO gain in kHz/volt
K L = K d K a K o =closed loop gain in kHz/volt
A better understanding of the operation of phase detector may be obtained by
considering that the simple Exclusive OR (XOR) gate is used as a phase detector. The XOR
gate can be thought of as an inequality detector which compares the inputs and produces a
pulse output when these inputs are unequal. The width of the output pulse is proportional to
EEE 316 - Communications I
Experiment 6
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the phase error of the input signals. As shown in Fig. 6.2, the width of the output pulse of (b)
is larger than that of (a) and is smaller than that of (c). When the output of phase detector
is applied to the input of low-pass filter, the output of low-pass filter should be a dc level
that is directly proportional to the pulse width. In other words, the output dc level is
proportional to the phase error of input signals. Fig. 6.2 (d) shows the relationship between the
input phase error and the output DC level.
Figure 6.2 Phase detection.
For a further understanding of the operation of the PLL can be obtained by
considering that initially the PLL is not in lock. The VCO has an input voltage of 2 V and is
running at its free-running frequency, say 1 kHz. Consider the signals shown in Fig. 6.3. If
the VCO frequency and the signal A with the lower frequency 980 Hz are applied to the
inputs of the phase detector XOR, the narrower width of output pulse will cause the lowpass filter obtaining the smaller output voltage of 1V. This smaller voltage decreases the
VCO frequency close to the input frequency. If the VCO output frequency equals the input
frequency, lock will result. On the contrary, the higher frequency 1.2 KHz of input signal B
causes the larger filter output of 3V that increases the VCO frequency output to lock at the
input frequency.
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Experiment 6
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Figure 6.3 Operation of frequency locking.
6.4.2 LM565 PLL Basic Characteristics
The LM565 is a general-purpose phase-locked loop and is widely used in frequency
demodulation. In designing with the LM565, the important parameters of interest are as
follows:
6.4.2.1 Free-running Frequency
Fig. 6.4 shows a PLL circuit with LM565. In the absence of the input signal, the
output frequency of the VCO is called the free-running frequency fo, In the PLL circuit of
Fig. 6.4, the free-running frequency of LM565 is determined by the timing components C2
and VR-, and can be found by
1
Free-running frequency : f o =
(6.1)
3.7 VR1C 2
33.6 f o
Closed-loop gain : K L = K d K a K o =
(6.2)
Vc
where Vc = total supply voltage to the circuit = Vcc − (− Vcc ) = 5V − (− 5V ) = 10 V .
Figure 6.4 LM565 PLL circuit.
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Experiment 6
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6.4.2.2 Lock Range
Initially, the PLL is in already-locked state and the VCO is running at some
frequency. If the input frequency f i is away from the VCO frequency f o , locking may still
occur. When the input frequency reaches a specific frequency where the PLL loses lock, the
frequency difference of f i and f o is called the lock range of the loop. The lock range of
LM565 can be found by (see Fig. 6.5)
fL =
8 fO
VC
(6.3)
6.4.2.3 Capture Range
Initially, the loop is unlocked and the VCO is running at some frequency. If the input
frequency f i is close to the VCO frequency f o , unlocking may maintain. When the input
frequency reaches a specific frequency where the PLL locks, the frequency difference of f i
and f o is called the capture range of the loop. The capture range of LM565 can be found by
(see Fig. 6.5)
fc =
1
2π
2π x f L
3.6 x 10 3 x C 2
(6.4)
Figure 6.5 Illustration of lock and capture ranges.
6.4.3 Frequency Demodulator Based on LM565 PLL
The PLL circuit of Fig. 6.4 can be used as a frequency demodulator. When the input
signal increases in frequency, the output signal decreases in voltage. Inversely, if the input
signal decreases in frequency, the output signal will increase in voltage.
The VCO circuit of the LVI565 is equivalent to that of the LM566. The freerunning frequency f o of the VCO is determined by the values of external components C 2
and VR1 . The internal resistor 3.6 kΩ (pin7) and the external capacitor C 3 form a low-pass
filter. The capacitor C 4 connected between pins 7 and 8 is a frequency compensation
capacitor.
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Experiment 6
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6.5 EXPERIMENT AND RECORDS
Note: When using digital oscilloscope (DO), record the critical data related with any
observation on DO, for example DC level, peak values, period and frequency for different
regions; then draw the waveform based on this data on scale. The critical data should appear
just below the associated figure. You can take the DO display by holding and taking it in
storage.
6.5.1 LM565 PLL Characteristic Measurements
1. Locate LM565 PLL Circuit. Set SW1 to OFF position. Set SW2 to position C 2 = 0.1µF .
2. Adjust the VR1 to obtain the maximum free-running frequency f oh and the minimum
free-running frequency f ol at VCO OUTPUT. Record the results in Table 6.2.
3. Adjust the VR1 to obtain the VCO free-running frequency f o = 2 KHz.
4. Set SW1 to ON position. Connect a 0.5Vp-p, 2 KHz square wave to INPUT.
5. Observe the INPUT and the VCO OUTPUT signals and slowly increase the input
frequency until the output signal just unlocks. Record the input frequency as f Lh in
Table 6.2.
6. Return the input frequency to the free-running frequency f o of VCO. Slowly decrease
the input frequency until the output signal just unlocks and record the input frequency as
f Ll in Table 6.2.
7. Using the equation f L = ( f Lh − f Ll ) / 2 , calculate the lock range.
8. Increase the input frequency to force the VCO output unlocked. Slowly decrease the
input frequency until the PLL just locks. Observe the input frequency f Ch and record
the result in Table 6.2.
9. Decrease the input frequency to force the VCO output unlocked. Slowly increase the
input frequency until the PLL just locks. Observe the input frequency f Cl and record the
result in Table 6.2.
10. Using the equation f C = ( f Ch − f Cl ) / 2 , calculate the capture range.
11. Set SW1 to OFF position. Set SW2 to position C5 = 0.01µF . Repeat step 2.
12. Turn the VR1 to get the VCO free-running frequency f o of 20 kHz. I Set SW1 to
ON position and connect a 0.5Vp-p, 20 kHz square to INPUT. Repeat steps 6 to 11.
6.5.2 LM565 V-F Characteristic Measurement
1. Locate LM565 PLL Circuit. Set SW1 to OFF position. Set SW2 to position C 2 = 0.1µF .
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Experiment 6
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2. Adjust the VR1 to obtain a free-running frequency f o of 2 kHz at VCO OUTPUT.
3. Set SW1 to ON position.
4. Connect a 0.5Vp-p, 2 kHz square wave to INPUT. Measure and record the PLL
OUTPUT in Table 6.3.
5. Change the input frequencies of 0.5 kHz, 1 kHz, 1.5 kHz, 2.5 kHz, 3 kHz and 3.5 kHz
sequentially and measure the output voltages corresponding to the input frequencies.
Record the results in Table 6.3.
6. Plot output voltage vs. input frequency curve in Figure 6.9.
7. Set SW2 to position C5 = 0.01µF .
8. Set SW1 to OFF position. Turn the VR1 to get a free-running frequency f o of 20 kHz at
VCO OUTPUT.
9. Set SW1 to ON position.
10. Connect a 0.5Vp-p, 20 kHz square wave to INPUT. Measure and record the VCO
OUTPUT in Table 6.4.
11. Change the input frequencies of 16.5 kHz, 17.5 kHz, 18.5 kHz, 21.5 kHz, 22.5 kHz
and 23.5 kHz sequentially and measure the output voltages corresponding to the input
frequencies. Record the results in Table 6.4.
12. Plot output voltage vs. input frequency curve in Figure 6.10.
6.5.3 PLL Frequency Demodulator
1. Locate LM566 FM Modulator circuit. Set SW2 to C4 = 0.01 µF . Turn VR1 to get the
output free-running frequency f o of 20 kHz.
2. Complete LM565 PLL Circuit by setting SW2 to position C5 = 0.01µF . Turn VR1 to get
the free-running frequency f o of 20 kHz at VCO OUTPUT.
3. Connect the LM566 FM Modulator output to the LM565 PLL Circuit INPUT and set
SW1 to ON position.
4. Connect a 300 mVp-p, 1 kHz sine wave to the AUDIO INPUT of the LM566 FM
Modulator. Using the oscilloscope, observe the output waveform of LM565 PLL Circuit
and record the result in Table 6.5.
5. Repeat step 4 for the input frequencies of 2 kHz and 3 kHz.
6. Change the AUDIO INPUT amplitude to 500 mVp-p. Repeat steps 4 and 5, and record
the results in Table 6.6.
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Experiment 6
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Table 6.2
fo
C
f Oh
f Ol
f Lh
f Ll
Hz.
C 2 = 0.1 µF
2 kHz.
Hz.
Hz.
fL =
20 kHz.
Hz.
Hz.
fL =
f Ch
f Cl
fC =
Hz.
Hz.
Hz.
Hz.
C5 = 0.01 µF
Capture Range
fC
Lock Range
fL
Free-running
Frequency Range
Hz.
Hz.
Hz.
fC =
2.5
3.0
Hz.
Hz.
Table 6.3
( Vm = 0.5V pp , f o = 2 kHz , C2 = 0.1 µF )
Input
Frequency
(kHz)
Output
Voltage
(V)
0.5
1.0
1.5
2.0
3.5
Output
Voltage
(V)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Input
Frequency
(kHz)
Figure 6.9 Variation of output voltage by frequency.
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Experiment 6
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Table 6.4
Vm = 0.5V pp , f o = 20 kHz , C2 = 0.01 µF
Input
Frequency
(kHz)
Output
Voltage
(V)
16.5
17.5
18.5
20
21.5
22.5
23.5
Output
Voltage
(V)
16.5
17.5
18.5
20
21.5
22.5
23.5
Input
Frequency
(kHz)
Figure 6.10 Variation of output voltage by frequency.
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Experiment 6
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Table 6.5
( Vm = 300 mV pp , f 0 = 20 kHz )
Input
Frequency
Input Waveform
Output Waveform
1 kHz
2 kHz
3 kHz
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Experiment 6
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Table 6.6
( Vm = 500 mV pp , f 0 = 20 kHz )
Input
Frequency
Input Waveform
Output Waveform
1 kHz
2 kHz
3 kHz
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Experiment 6
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