Design Check
#1
Avoid Placing Vias at the End of SMT Pads:
This is especially important if the vias are not masked-over. Placing vias
too close to SMT pads will allow solder to migrate off the pad and through
the via, resulting in a poor solder joint. Edge of via to edge of SMT pad
should be .025” or greater whenever possible, and masking over the via
pad is recommended.
Note how the mask openings for vias and SMT pads run into one another. There is
nothing to block assembly solder flow.
Here the openings for the SMT pads are reduced in size, and the via openings are
eliminated. All solder will now stay on the SMT pads.
“
EDGE OF VIA TO EDGE OF SMT PAD SHOULD
BE .025” OR GREATER WHENEVER POSSIBLE.
- AL WRIGHT
Design Check
#2
Do Not Route Wide Traces Into Narrow SMT Pads:
Traces which terminate at surface mount pads should be narrower than the
pad itself. If the trace is wider, the soldermask aperture, rather than the pad
area, will define the area to which surface finish will be applied to the PCB.
The result will be insufficient paste coverage, because the stencil aperture
size will match that of the pad only. Using narrow traces also reduces the
heat sink effect which can occur when wide traces are present.
Paste will be applied only to the pad areas, but the mask opening exposes the toowide traces. Solder will spread to the traces on the 1st, 3rd, and 4th pads, resulting in
a poor solder joint.
“
TRACES WHICH TERMINATE AT SURFACE
MOUNT PADS SHOULD BE NARROWER THAN
THE PAD ITSELF.
- AL WRIGHT
Design Check
#3
Do Not Route Traces Along Sides of SMT Pads:
Route traces into SMT pads midway along one edge or the other. Some
CAD systems will allow a small gap between the pad and the trace, with
a short (.005” or less) 90 degree connection to the pad. This can act as a
trap for etchant, which will continue to eat away at the trace after the rinse
cycle. In some cases these connections will pass bare PCB continuity test,
but will fail after thermal shock during assembly. When using tight minimum
spacing values, check for such connections and correct the routing
manually if necessary.
Routing traces in this manner can also have the effect of creating an
oversized “soldermask-defined” pad, similar to the problem caused by wide
traces (described above).
The pad marked X does not need to be routed so close to the pad. Routing it like the
checked pad will eliminate the process problem.
“
WHEN USING TIGHT MINIMUM SPACING
VALUES, CHECK FOR SUCH CONNECTIONS
AND CORRECT THE ROUTING MANUALLY IF
NECESSARY.
- AL WRIGHT
Design Check
#4
Route All Traces at 90 Degrees or Greater:
Never route a circuit trace a less than a 90 degree angle. Acute angle trace
junctions can cause manufacturing problems, and can fail later. If you need
to double-back in order to complete a connection, use multiple segments.
Acute angle traces can act as acid traps, and can concentrate stress. Re-route such
corners gradually, with a series of segments.
“
ACUTE ANGLE TRACE JUNCTIONS CAN CAUSE
MANUFACTURING PROBLEMS, AND CAN FAIL
LATER.
- AL WRIGHT
Design Check
#5
Don’t Place Components Too Close to the PCB
Outline:
Place components a safe distance from v-scored edges and breakaway
tab locations, so they will not be damaged during de-panelization. Add
reference tab locations into your design so that you will be able to see
immediately if a component needs to be moved.
Keep SMT devices at least .100” from the PCB edge (more whenever
possible) and avoid hand-flexing when singulating after assembly.
SMT pad is .036” from the PCB edge. OK for a completely routed edge, but increase the
distance to >.100” if the edge is a tab or a v-score.
“
ADD REFERENCE TAB LOCATIONS, SO THEY
WILL NOT BE DAMAGED DURING
DE-PANELIZATION.
- AL WRIGHT
Design Check
#6
Never Export English-Unit Gerber or Drill Files at 2:3
Decimal Resolution:
2:3 was a default setting back in the days when file size needed to be kept
small, for moving data files on flexible disks of limited capacity. It is not
appropriate for today’s dense designs.
Low resolution truncates off the last significant digit of your feature’s
location. Particularly on designs which use 0.5mm (.0197”) surface mount
devices, or large numbers of randomly-placed vias, the loss of this digit
can cause a design which is perfect in its native CAD environment to yield
from dozens to hundreds of Gerber spacing violations as your .0197” pad
spacing is rounded to either .019” or .020” because of the missing digit.
Inadequate resolution can also play havoc with arc endpoints and polygon
borders. Always use at least 2:5 inch, or 3:3 metric.
Insufficient drill resolution rounding errors cause small shifts between holes and
pads. These in turn become DRC / annular ring violations.
“
LOW RESOLUTION TRUNCATES OFF THE
LAST SIGNIFICANT DIGIT OF FEATURE’S
LOCATION.
- AL WRIGHT
Design Check
#7
Size Your Soldermask Openings Consistently:
Set up your padstack definitions so that all of your components use the
same amount of oversizing. Doing so will eliminate a host of design rule
errors that your fabricator will need to repair before manufacturing. Using
(copper pad size + .004”) will enable your fabricator to avoid mask-on-pads,
while still depositing mask material between pins of SMT components down
to 0.5mm (.0197”) pitch, with no editing. (Example: .012” x .040” copper
pad, .016” x .044” soldermask opening.)
Notice the oversized openings for the vias, and the inconsistent sizing LXW of the
rectangular pads. Some openings merge.
Now all mask openings are consistently and appropriately sized. Previously
overlapping openings are now separated.
“
SETUP YOUR PAD STACK DEFINITIONS SO THAT
ALL OF YOUR COMPONENTS USE THE SAME
AMOUNT OF OVERSIZING.
- AL WRIGHT
Design Check
#8
Always Use Direct Connect for Vias:
Do not use thermal pads or location dots at via hole locations on internal
plane layers. They are unnecessary, and in the case of tightly-spaced
vias, multiple thermal pads may overlap to the extent that all of the tie
connections may be removed from one or more vias. The result will be an
open circuit (“starved thermal”) condition.
Your fabricator’s pre-production CAM department typically fills location
dots before the artwork is plotted for manufacturing. Since the dots are
not useful for production, and may actually create problems if they are not
filled, it is best to omit them at the design stage.
All vias in the violet plane areas are direct-connect, with no thermal pads and no
small location dots. This is the correct appearance for vias connecting to planes.
“
DO NOT USE THERMAL PADS OR LOCATION
DOTS AT VIA HOLE LOCATIONS ON INTERNAL
PLANE LAYERS.
- AL WRIGHT
Design Check
#9
Size Your Component Hole Thermal Pads
Appropriately:
As with vias, multiple, closely-spaced thermal pads on component holes
can end up overlapping to cause an open.
Another issue is that if the inner diameter is grossly oversized, there will
be so much copper present that the pad will no longer serve its thermal
function (that of maintaining an appropriately high temperature in the barrel
of the hole during the solder cycle.) The inner diameter of your thermal
pads should typically match the diameter of your external layer pads.
Top and bottom thermals are correct. They will function better, and will be easier to
read in a cross section than the one in the center.
“
THE INNER DIAMETER OF YOUR THERMAL
PADS SHOULD TYPICALLY MATCH THE
DIAMETER OF YOUR EXTERNAL LAYER PADS.
- AL WRIGHT
Design Check
#10
Allow Enough Clearance Between Unsupported PTHs
and Adjacent Copper Features on Internal Layers:
As design rules become increasingly tighter, this DRC error is becoming
more common. Multilayer PCBs need a minimum of .006” clearance
from edge of trace to barrel of hole. There are many factors which affect
dimensional accuracy of multilayers (drill runout, material movement,
artwork scaling, multiple pinning setups) so design-in at least .006”, and
more whenever possible.
This hole is only .005” from the trace, and shows up as a min space violation. Hole to
trace needs to be .006” min (more when possible).
“
MULTILAYER PCB’S NEED A MINIMUM OF .006”
CLEARANCE FROM EDGE OF TRACE TO BARREL
OF HOLE.
- AL WRIGHT
Bonus: Design Check
#11
Remove Mask Openings for Vias in Dog-Bone BGA
Areas:
The openings serve no purpose other than to allow solder bridge formation.
Fabricators will ask for permission to remove openings. It is one of the most
frequent reasons for delays in pre-production.
Avoid delays, and avoid rework, by removing the openings completely. If
you don’t want mask in the via barrel, at least encroach the mask onto the
pad, leaving only the barrel open.
Solder can bridge under BGA in top view, resulting in difficult repair. Bottom view vias
are masked-over, so that this cannot occur.
Bonus: Design Check
#12
Don’t Place Text on Multiple Layers in the Same Text
Location, Even if the Characters are Identical:
Text which is present in both the copper and the silkscreen will not print
correctly – it will be offset and uneven, with a double-struck appearance.
Remove redundant text from the layers where you do not need it.
Silkscreened text applied over soldermask typically offers the best legibility
on the finished PCB.
About The Author
Al Wright
PCB Field Applications Engineer
Epec Engineered Technologies
Al has been in the industry for over 32
years and has been with Epec for more
than12 years. As field application engineer,
he handles a wide range of responsibilities
including reviewing PCB designs for
manufacturability during the quoting and
design stage, interacting with off-site
manufacturing facilities to solve technical
issues during production, and programming
CNC machines for in-house projects,
reworks, and modifications. Al’s technical
expertise is essential to Epec’s engineering
department and provides valuable insight
when working with customers.
Previous to working at Epec, Al spent 20 years with CPC Incorporated, a
medium-sized PCB manufacturer, learning hands-on about PCB processing
before moving into front end engineering. Al brings impressive expertise to
Epec and has worked with over 50,000 different PCB designs from his start
in 1982 to the present day. He works with Epec’s team to get all designs
right ahead of time so that products will be correct the first time.
Visit Our Website @ www.epectec.com
Contact Us
Our knowledgeable staff has over 60 years of experience in the industry.
We welcome the opportunity to put our skills to work for you! Please
contact us with any questions or requests.
North American Headquarters
174 Duchaine Blvd.
New Bedford, MA 02745
Toll Free: (888) 995-5171
Tel: (508) 995-5171
Contact Us By Email:
Sales
Quotes
Engineering
Quality
sales@epectec.com
quoting@epectec.com
engineering@epectec.com
quality@epectec.com
Social Community
Join our Social Community and keep in touch with all our latest technology
investments, current news, upcoming events, and promotions.
Visit Our Website @ www.epectec.com