1. MOS Transistor Inverter: Static Characteristics I
1.1 Resistively Loaded Common-Source Amplifier
The schematic diagram of a common-source amplifier with a resistive
load is shown in Fig. 1.1. The FET is biased into conduction with a d.c.
bias voltage, VGS, and an input signal, vgs, is superimposed on this bias.
The output voltage is observed across the drain-source of the
transistor.
VDD
iD
RD
D
G
input signal Vgs
~
VO = VDS output voltage
S
VGS = Vi
gate bias VGS
Fig. 1.1 Schematic Diagram of a Resistively Loaded MOSFET Amplifier
The amplifier has then
characterised as follows:
both
an
input
Input Circuit
and
output
circuit
Output Circuit
Vi = vGS = VGS + vgs
Vo = vDS = VDD – iD RD
Rearranging the second expression gives:
So that:
an
iD = −
VDS
V
= DD − iD
RD
RD
V
1
VDS + DD
RD
RD
This is a straight-line relationship of the form y = mx + C, where m = 1/RD and C = VDD/RD. This straight line defines the locus of the
operating point for the output circuit of the amplifier. This is referred
1
to as the “load-line” of the amplifier and can be plotted from two
extreme points:
If
iD = 0,
If
VDS = 0,
V
1
VDS + DD
RD
RD
∴
VDS = VDD , iD = 0
VDD
= ID MAX
RD
∴
VDS = 0 , iD =
0= −
iD =
VDD
RD
point 1
point 2
This relationship can be superimposed onto the set of characteristic
curves of iD vs VDS for the transistor, as shown in Fig. 1.2.
1.2 Operation as an Amplifier
Fig. 1.2 shows the locus of the operating point of the transistor on the
load line when a signal is applied to the gate of the transistor. When
the gate voltage is increased above the bias point the drain current
increases in response. This in turn increases the voltage drop across
RD and consequently the output voltage falls. When the input gate
voltage is lowered from the bias value the drain current decreases in
response, the voltage drop across RD falls and so the output voltage
increases. It can be seen that the phase of the output voltage is
opposite to that of the input and so this is an inverting amplifier. From
the values given for the signal levels, it can be seen that this stage
only has a small gain of less than 2.
1.3 Operation as a Switch
Fig.1.3 shows the operation of the resistively loaded MOS transistor as
a logic switch. The input voltage applied to the gate is either logic LO
at 0V or logic HI at VDD. When the input voltage is LO at 0V, then the
VGS applied to the gate is below the threshold voltage of the transistor,
VT, and the transistor is non-conducting or OFF. In this case, the drain
current is zero and there is no voltage drop across the load resistor,
RD, so that the output voltage is pulled up to the supply rail, VDD, as
shown at point A on the characteristic. On the other hand, if the input
voltage applied is a logic HI value of VDD, then the transistor becomes
highly conducting or ON and the drain current rises to its maximum
value, ID MAX. In this case the output voltage goes to its logic LO level,
VOL, as shown at point B on the characteristic. This can be seen to be
some finite voltage above zero, which depends on the properties of the
transistor. With proper design, the value of VOL can be maintained less
than the threshold voltage, VT, so that this logic LO level can be
correctly interpreted by a following logic gate. This will now be
investigated further.
2
nonsaturation
iD
(µA)
100
vGS
(volts)
saturation
6
RD = 100kΩ
Ω
90
80
5
70
60
ID
operating
range
50
id
VGS 4
40
30
vgs
bias
point
3
20
2
1
10
0
1
3
2
4
5
6
7
8
9
10 (volts)
VDS
vds
VDS
Fig. 1.2
Operation of the MOS Transistor as a Voltage Amplifier
VDD = 10V
d.c. Bias Conditions:
input
VGS = 4V
VDS
a.c. Signal Conditions:
vgs = 2Vptp
vds = 3.5 Vptp
Voltage Gain:
output
= 5.8V
ID
v ds
3.5 V
=
= 1.75
v gs
2V
3
id
low gain
= 37µA
= 32µA ptp
iD
(µA)
100
ID MAX
nonsaturation
vGS = VDD
saturation
vGS
(volts)
6
B
90
80
5
RD = 100kΩ
70
60
50
4
40
30
3
20
10
A
0
1
2
3
5
4
VOL
6
7
8
10 (volts)
VOH = VDD
9
2
1
VDS
Fig. 1.3 Operation of the MOS Transistor as a Logic Switch
4
1.4 Logic Voltages
Input Voltages:
For the present, the input logic voltages will be taken as ideal so that:
ViL = 0V
and
ViH = VDD
Output Voltages:
When the input is at the LO logic level, the transistor is OFF and the
output will be pulled up to the supply voltage so that:
VOH = VDD
When the input is at the HI logic level, the transistor is operating in
the non-saturation region with maximum drain current flowing. The
equation describing the current-voltage relationship can be solved
under these conditions in order to determine the output logic LO
voltage. When operating in the non-saturation region the drain current
is described as:
2
ID = Kn[2(VGS − VT )VDS − VDS
]
With the conditions ID = ID MAX , Vi = VGS = VDD and VDS = VOL substituting
gives:
2
IDMAX = Kn[2(VDD − VT )VOL − VOL
]
But from the circuit:
ID MAX =
VDD − VOL
RD
Therefore:
VDD − VOL
2
= Kn[2(VDD − VT )VOL − VOL
]
RD
5
Then:
VDD − VOL
2
= 2(VDD − VT )VOL − VOL
KnRD
Rearranging gives:

VDD  1
2
=
+ 2(VDD − VT )VOL − VOL
KnRD KnRD

 1

V
2
VOL
−
+ 2(VDD − VT )VOL + DD = 0
KnRD
KnRD

2
 1

 1
 4V
+ 2(VDD − VT ) ± 
+ 2(VDD − VT ) − DD

KnRD

KnRD
 KnRD
VOL =
2
If it is assumed that 2(VDD – VT) >> 1/KnRD then this simplifies to:
2
VOL = (VDD − VT ) ± (VDD − VT ) −
VDD
KnRD
One solution will have a value greater than the supply voltage, VDD,
and can be discarded to give the value which lies between 0V and VDD
so that in the example given with VDD = 10V, VT = 1V, RD = 100kΩ and
Kn = 100µAV-2:
VOL = (10 − 1 ) −
(10 − 1)2
−
10
=9−
10 − 410 5
81 − 1 = 0.05V
This value is acceptable as it is much less than the threshold voltage,
VT, and so can be applied as a LO logic level to a similar circuit.
6