A Novel ZVS Full-Bridge Converter
with Auxiliary Circuit
Zhong Chen, Biao Ji, Feng Ji, and Lei Shi
Aero-Power Sci-tech Center
Nanjing University of Aeronautics & Astronautics
Nanjing, 210016, China
Email: chenz@nuaa.edu.cn
Abstract—A novel full-bridge (FB) pulse-width-modulated
(PWM) converter features zero-voltage-switching (ZVS) of all
primary switches in the entire line and load range is described.
In contrast to conventional full bridge converter, ZVS is
achieved by utilizing energy stored in inductive components of
the auxiliary circuit. The auxiliary inductors do not appear as
series inductances in the power transfer path, so they do not
cause severe voltage ringing across the output rectifier or duty
cycle loss. The operation principle of the circuit is analyzed and
design considerations of the converter are discussed. Finally, the
experimental results from a 1-kW (54-V/20-A) prototype are
presented to confirm the operation, validity, and features of the
proposed converter.
I.
INTRODUCTION
The full-bridge (FB) zero-voltage-switching (ZVS) pulsewidth-modulated (FB ZVS-PWM) converter, [1]-[11], is
applied in medium to high power conversion due to high
power density, ZVS operation, high efficiency, low
electromagnetic interference (EMI) and moderate device
stresses. In a conventional phase shifted full bridge (PSFB)
converter, ZVS is achieved by inserting an inductor in series
with the transformer [1]-[4]. However, full ZVS operation
can only be achieved with a limited load and input-voltage
range. The loss of ZVS will result in increased switching loss
and electromagnetic interference. Intentionally by increasing
the leakage inductance or by adding a large external
inductance in series with the primary transformer can help
extend the ZVS range of the lagging leg switches. But the
larger series inductance has a detrimental effect on the
performance of the converter since it results in increased loss
of duty cycle, as well as severe voltage ringing across
secondary-side rectifier diodes due to the resonance between
the inductance and the junction capacitance of the rectifier.
To suppress the ringing, a snubber circuit is required. If a
conventional RC or RCD snubber is used, the conversion
efficiency of the circuit may be significantly degraded [5].
And the large external inductance will cause large circulating
current at full load which adversely affects the conversion
978-1-4244-4783-1/10/$25.00 ©2010 IEEE
efficiency. As a nondissipative method, the secondary-side
voltage oscillation in the FB ZVS converter is virtually
eliminated by employing an active switch in the secondary
side, but an added active switch increases the system
complexity and causes additional switching loss [6]. For
implementations with an external primary inductor, the
ringing can also be effectively controlled by employing
primary-side diodes. While the approaches in [7] offer
practical solutions to the secondary-side ringing problem,
they do not offer any improvement of the secondary-side
duty-cycle loss. Using a saturable external inductor instead of
a linear inductor, ZVS range can be increased without
significantly losing the duty ratio [8]. However, a large-size
core is required to eliminate the thermal problem. And at very
light load current, ZVS operation can still be lost [8]-[9]. The
energy stored in the magnetizing inductance can also be used
to extend the ZVS range. In conventional PSFB converter,
this results in significant increase in the rms switch current
and the conduction loss [10]-[11].
In this paper, a novel full-bridge converter that achieves
ZVS right down to no load without serious conduction loss
penalty is proposed. This constant-frequency, FB ZVS
converter employs an asymmetrical auxiliary circuit
consisting of a few passive components. The proposed
converter and its operating principle are described in Section
II. Section III presents the optimal design considerations for
the proposed converter. The experimental results are
presented in Section IV to verify the validity of the proposed
converter.
II.
OPERATION PRINCIPLE
Fig. 1 shows the proposed ZVS full-bridge converter
topology. The primary side of the converter consists of two
bridges Q1-Q3 and Q2-Q4 connected through two capacitors
Ca1 and Ca2 to the connection of the power transformer Tr and
the auxiliary inductors La1 and La2. The two primary side
capacitors are used to prevent the saturation of the power
transformer and the auxiliary inductor cores by blocking the
flow of any dc current through Tr, La1 and La2. The switching
1448
I1
I2
I3
Fig. 1. Proposed full bridge ZVS converter.
transition of the switches in the Q2-Q4 leg of the bridge is
delayed, phase-shifted, with respect to the switching
transition of corresponding switches in the Q1-Q3 leg.
Generally, these two auxiliary capacitors are selected large
enough so that their voltages are approximately constant
during a switching cycle. Because the average voltages of the
auxiliary inductors and the power transformer during a
switching cycle are zero and the pair of switches in each
bridge leg operate with 50% duty cycle, the magnitude of
voltage sources vca1 and vca2 are equal to 1/2Vin, i.e., vca1=
vca2=1/2Vin. In addition, the auxiliary inductor stores energy
which only be used to achieve ZVS, its size can be small.
The output side of the converter is implemented with a
full-wave rectifier with a tapped secondary. Also, any other
implementation of the secondary side rectification stage is
possible. In terms of power transfer from the input to load,
the power circuit operates in exactly the same way as does a
conventional phase-shifted full-bridge converter, and the
auxiliary circuit hardly interferes with its power transfer.
However, the auxiliary circuit removes the switching losses
from all the switches.
The key waveform of the ZVS PWM full-bridge
converter is shown in Fig. 2. To perform the steady state
analysis, the following assumptions are made.
1) All components and devices have ideal properties and
characteristics.
2) C1= C3= Clead, C2= C4= Clag.
3) The output filter capacitor is large enough to be
treated as a constant voltage source with a magnitude
equal to Vo.
4) The turns ratios of the power transformer is the
primary winding: the secondary winding=Np: Ns.
(where Np: Ns=K)
5) The switching frequency fs is fixed and the inverse of
the switching period Ts.
Fig.3. shows the topological stages of the converter
during a half period. The second half period is similar to the
first half period.
1) Stage 1 [t0, t1] [Refer to Fig. 3(a)]
In the last interval of the previous cycle, diagonal
switches Q1 and Q4 are conducting, primary voltage is
positive so that load current Io flows through DR1 and the
upper secondary of transformer Tr. After switch Q1 is turned
off at t=t0, current i1 starts charging output capacitance C1 of
switch Q1 and discharging output capacitance C3 of switch Q3,
where i1 is the sum of the current iLa1 and the primary current
ip=Io/K. During this interval, the current of the inductor La1
keeps at ILa1 which can be calculated as (1). The voltage of Q1
rises slowly owing to C1. After the capacitor C3 is fully
I La1
I La 2
Fig. 2. Key waveforms of proposed converter power stage.
discharged, current i1 continues to flow through the antiparallel diode of switch Q3. The voltage across switch Q3 is
given in (2) during this interval.
Vin
I La1 =
(1)
8La1 ⋅ f s
I o / K + I La1
(t − t 0 )
(2)
2Clead
2) Stage 2 [t1, t2] [Refer to Fig. 3(b)]
Q3 can be turned on at zero voltage when D3 conducts. In
this topological stage, the potential of point A becomes zero.
Voltage across the power transformer also becomes zero
since the transformer is shorted by the simultaneous
conduction of the body diode of Q3 and switch Q4. The
voltage applied across La2 is －Vin/2. Due to this voltage, the
current iLa2 still decreases until t2. At t2, iLa2 reaches its
minimum value －ILa2. And ILa2 can be expressed as (3).
Vin
I La 2 =
(3)
8La 2 ⋅ f s
And with real components, the primary current will
decrease because of the forward voltage of power switch
Vforward and parasitical impedance. The primary current can be
expressed as
V forward ⎤ − Lrk (t −t1 ) V forward
⎡
i p (t ) = ⎢i p (t1 ) +
−
(4)
⎥e
r ⎦
r
⎣
where r is the equivalent series resistor for the circuit, Lk is
the leakage inductance of power transformer . This interval is
ended when the switch Q4 is turned off.
3) Stage 3 [t2, t3] [Refer to Fig. 3(c)]
Q4 is turned off in ZVS at t2. Current i2 starts charging
output capacitance C4 of switch Q4 and discharging output
1449
vc3 (t ) = Vin −
Io
+ I La 2 ) cos ωr (t − t2 ) − I La 2
K
I
vc4 (t ) = ( I La 2 + o ) Z r sinωr (t − t2 )
K
where Z r = Lk 2Clag , ωr = 1 2 Lk Clag
i p (t ) = (
(5)
(6)
4) Stage 4 [t3, t4] [Refer to Fig.3(d)]
D2 conducts naturally when vc2 decays to zero, and Q2 can
be turned on at zero voltage. At the same time, load current Io
commutates from the upper secondary and rectifier DR1 into
the lower secondary and corresponding rectifier DR2. The rate
of change of the primary current is given by
di p
V
= − in
(7)
dt
Lk
Since the leakage inductance of the power transformer is
smaller, the duty-cycle loss in the converter is decreased.
5) Stage 5[t4, t5] [Refer to Fig.3(e)]
The commutation of the load current from the upper to the
lower secondary is completed at t=t4, the primary current
commutation from the positive to negative direction is also
finished so that the primary is ip=－Io/K. The input energy is
transferred into the secondary side by power switches Q2 and
Q3 and Tr. This stage ends at t5 when switch Q3 turns off.
Then the second half of the switching period begins. In the
second half of the switching period, the operation of the
circuit is exactly the same as the operation in the first half of
the switching period.
(a)
(b)
(c)
III.
DESIGN CONSIDERATIONS
Auxiliary inductors are required in the proposed converter
to achieve ZVS. However, the auxiliary inductor current will
result in additional conduction losses. This can be achieved
by using an asymmetrical auxiliary arrangement.
(d)
(e)
Fig. 3. Topological stages of proposed converter power stage.
capacitance C2 of switch Q2. Since the potential of point B
increases from zero toward Vin, while the potential of point A
is constant at zero. The secondary windings are also shorted
so that rectifiers DR1 and DR2 can conduct the load current
simultaneously. vAB is fully applied to the Lk. Because the
auxiliary inductor La2 is much larger than the leakage
inductance Lk, it can be treated as a constant current source
during the transition time. This stage finishes when vc4 rises
to Vin and vc2 falls to zero at t3. The primary current and the
voltage across Q4 are given by (5) and (6).
A. ZVS Range for the Leading leg and the selection of La1
In order to achieve ZVS turned on, the output capacitance
of the switch shall be completely discharged within the dead
time period td(lead) under all operating conditions. Neglecting
the capacitances of the transformer’s windings, the value of
the current required to achieve ZVS of leading-leg switches
Icharge is calculated as
I
(8)
I ch arg e ⋅ td ( lead ) = La1 ⋅ td ( lead ) ≥ Clead ⋅Vin
2
Expressions (1) and (8) can be used to estimate the
required value of the auxiliary inductance La1. From (1) and
(8), we can get the following equation
td ( lead )
La1 ≤
(9)
16 ⋅ Clead ⋅ f s
Fig. 4 shows an example of the selection curves of the
auxiliary inductor La1 as functions of td(lead) at different output
capacitances. It is seen that with a fixed dead time, smaller
La1 will achieve ZVS much more easily. When the output
capacitance is decided, the dead time can be selected shorter
with smaller La1. The dead time for the leading leg should be
selected together with auxiliary inductor.
1450
vc 4 (V)
La1 (μH)
La 2
Clead
300pF
400pF
500pF
600pF
100μH
120μH
150μH
200μH
I o (A)
Fig. 6. Voltage across the parasitic capacitor of the lagging leg versus load
current at different auxiliary inductances. (Vin=400V, Lk=6μH)
td (lead ) (ns)
Fig. 4. Example design curves for selecting the auxiliary inductors vs. dead
time.
so the primary current can be expressed as Io/K.
Unlike the transition of leading leg, the transition of
lagging leg switches can be divided into two cases according
to the load current Io as shown in Fig. 5.
Under most load current conditions, the transition may
only go through stage I, as shown by Fig. 5(a). The primary
current decreases as the voltage of C4 increases. When the
voltage of C4 reaches Vin, D2 conducts, so Q2 can be turned on
with ZVS. When the transition starts at t=t2, the voltage of C4
can be calculated as (6).
Since the leakage inductance is much smaller compared
with conventional full bridge converter, the resonant time is
relatively shorter. So the load current may complete the
commutation from the upper secondary to the lower
secondary before the voltage of C4 reaches Vin. Then the
converter will enter stage II, as shown by Fig. 5(b). The
current through La2 will go on discharging C2 and charging C4.
Simultaneously this current will compensate the output
current Io.
(a) stage I
(b) stage II
Fig. 5. Transition equivalent circuit of lagging leg.
When the transition enters stage II, the voltage across Q4
can be expressed as (10).
⎛I
⎞
vc 4 (t ) = ⎜ o + I La 2 ⎟ Z r sin ωr (t2 ' − t2 )
⎝K
⎠
⎛ Io
⎞
'
⎜ − K + I La 2 ⎟ ⋅ (t − t2 )
⎠
+⎝
2 ⋅ Clag
(10)
vc 4 (V)
B. ZVS Range for the lagging leg and the selection of La2
Before analyzing the ZVS condition for the lagging leg,
we suppose the dead time td(lag)= Tc/4, where
Tc = 2π 2 ⋅ Lk ⋅ Clag . The output current ripple is neglected,
Lk
7μH
6μH
5μH
4μH
I o (A)
Fig. 7. Voltage across the parasitic capacitor of the lagging leg versus load
current at different leakage inductances.(Vin=400V, La2=100μH)
⎡
⎛ −Io
⎞⎤
⎢
⎜ K + I La 2 ⎟ ⎥
'
where t = t2 + ⎢ arccos ⎜
⎟ ⎥ ωr . t2 is the moment
I
o
⎢
⎜⎜
+ I La 2 ⎟⎟ ⎥
⎝ K
⎠ ⎦⎥
⎣⎢
when the load current completes commutation.
According to (6) and (10), Fig. 6 and Fig. 7 can be plotted.
Fig. 6 shows the voltage across Q4 versus load current Io with
definite leakage inductance under different auxiliary
inductances. Fig. 7 shows the voltage across Q4 in a function
of load current Io with determined auxiliary inductance under
different leakage inductances. From Fig. 6 and Fig. 7, we can
know ZVS can only be achieved when the voltage across Q4
is higher than Vin. As the leakage inductor becomes smaller,
the value of auxiliary inductance La2 should be made smaller.
Smaller La2 will in turn result in larger ILa2. And this will
increase conduction losses in the switches.
If the leakage inductance is minimized, the load current
will commutate fast, as shown in Fig. 5(b). And the current
through auxiliary inductance should be made larger than the
reflected load current. It results in increased conduction
losses. So the leakage inductance should be optimally
selected to simultaneously achieve the entire range ZVS
operation and improve overall efficiency over the entire
conversion range.
'
2
C. The selection of Ca1 and Ca2
The two capacitors are employed to establish dc voltages
and block the flow of any dc current through the magnetic
1451
components. The permitted ripple voltage on these two
capacitors is about 1% of the maximum voltage.
D. Turns ratio of the transformer
Finally, to achieve maximum efficiency improvement, the
turns ratio of the transformer must be maximized. In fact,
since the duty-cycle loss in the converter is negligible due to
the smaller leakage inductance of the transformer, the
converter can be designed with a larger turns ratio compared
to the conventional PSFB converter. Moreover, the
secondary–side ringing between the leakage inductance of the
transformer and the junction capacitance of the rectifier is
significantly reduced because of the smaller leakage
inductance. Any residual parasitic ringing can be damped by
a simple RCD-snubber circuit.
IV.
v DS(Q3 ) :[200V / div]
v GS(Q3 ) :[20V / div]
Time :[0.5μs / div]
(a) the leading leg
EXPERIMENTAL RESULTS
In order to verify the operation principle of converter, a
prototype converter was built in the lab with the following
parameters.
• Input voltage Vin : 300-400VDC;
• Output voltage Vo : 54VDC;
• Maximum output current Io : 20A;
• Switching frequency fs : 100kHz;
• Main switches Q1~Q4 : IRFP460 (International
Rectifier), and its RDS(on)=0.3Ω;
• Rectifier diodes (full-wave rectifier) : DSEI30-06A
(IXYS);
• Turns ratio K : 14:3:3;
• Auxiliary inductor La1 : 250μH (core: PQ2020);
• Auxiliary inductor La2 : 100μH (core: PQ2020);
capacitors
Ca1&Ca2:
2.2μF/250V
• Auxiliary
(polypropylene).
The phase-shift control circuit was implemented using a
UCC3895 controller.
Fig. 8 shows the gate signals of PWM switches Q3 and Q2
along with their drain-to-source voltage waveforms at 5%
load. As seen, the drain voltage reaches zero before the gate
reaches its threshold demonstrating zero-voltage turn-on.
Fig. 9 shows the currents flowing through the two
auxiliary inductors with different peak value. The changing
current can help realize ZVS for both legs from no load to
full load.
Fig. 10 shows the key waveforms of the proposed FB
ZVS converter. As can be seen from the corresponding
waveform in Fig. 10, the proposed converter has a very small
duty cycle loss as well as a very much decreased parasitic
ringing because of the smaller leakage of the power
transformer. And we can see from the active state to the
passive state the primary current has a downward step caused
by the junction capacitance of output rectifier diodes
discharging.
Fig. 11 shows the measured efficiencies as functions of
output current at Vin=400V. Generally, the efficiency
improvement is more pronounced at light loads where the
conventional FB ZVS converter operates with hard switching.
Meanwhile, the ZVS operation is helpful to reduce EMI
problem at very light load. By increasing the turns ratio of the
transformer, both the conduction loss of the primary switches
and the voltage stress on the components at the secondary
side is decreased.
v DS(Q2 ) :[200V / div]
v GS(Q2 ) :[20V / div]
Time :[0.5μs / div]
(b) the lagging leg
Fig. 8. Drive voltage and drain to source voltage of the leading lag and
lagging leg at 5% load current.
i La1
(1A / div)
i La 2
(2A / div)
Time :[2.5μs / div]
Fig. 9. Current through auxiliary inductors at 5% load current.
v AB
(400V / div)
ip
(5A / div)
v rect
(50V / div)
Time :[5μs / div]
Fig. 10. Experimental waveforms of vAB and secondary voltage vrect at full
load.
1452
REFERENCES
[1]
Io / A
Fig. 11. Measured efficiency of proposed converter as a function of output
current.
V.
CONCLUSION
In this paper, a novel FB ZVS converter has been
proposed, which employs auxiliary network to achieve ZVS
in a wide range of load current and input voltage. The
auxiliary network has a simple structure which includes two
auxiliary inductors and two auxiliary capacitors. The
circulating energy and conduction losses have been
substantially reduced. Since the two auxiliary inductors do
not appear as series inductances, they will not cause the duty
cycle loss or severe voltage ringing across the output
rectifiers. In addition, it offers improved electromagnetic
compatibility and higher efficiency. The operation principle
and characteristic of the converter are analyzed in detail.
Experimental results from a 1kW/100-kHz prototype confirm
the advantages of the proposed configuration.
O. D. Petterson and D. M. Divan, “Pseudo-resonant full bridge dc/dc
converter,” in Proc. IEEE Power Electron. Sepc. Conf. 1987, pp. 424430.
[2] L. H. Weene and C. A. Wright, “A 1-kW, 500-kHz front-end converter
for a distributed power supply system,” in Proc. IEEE Appl. Power
Electron. Conf. (APEC’89), 1989, pp. 423-432.
[3] W. Chen, F. C. Lee, M. M. Jovanovic, and J. A. Sabate, “A
comparative study of a class of full bridge zero-voltage-switched PWM
converters,” in Proc. IEEE Appl. Power Electron. Conf. (APEC’95),
1995, pp. 893-899.
[4] B. P. McGrath, D. G. Holmes, P. J. McGoldrick, and A. D. McIve,
“Design of a soft-switched 6-kW battery charger for traction
applications,” IEEE Trans. Power Electron., vol. 22, no. 4, pp. 11361144, Jul. 2007.
[5] S. Y. Lin and C. L. Chen, “Analysis and design for RCD clamped
snubber used in output rectifier of phase shifted full-bridge ZVS
converters,” IEEE Trans. Ind. Electron., vol. 45, no. 2, pp. 358-359,
Apr. 1998.
[6] J. A. Sabate, V. Vlatkovic, R. B. Ridley, and F. C. Lee, “High-voltage,
hign-power, ZVS, full-bridge PWM converter employing an active
snubber,” in Proc. IEEE Appl. Power Electron. Conf. (APEC’91),
1991, pp. 158-163.
[7] R. Redl, N. O. Sokal, and L. Balogh, “A novel soft-switching fullbridge DC/DC converter: analysis, design considerations, at 1.5kW,
100kHz,” IEEE Trans. Power Electron., vol. 6, no. 3, pp. 408-418, Jul.
1991.
[8] G. Hua, F. C. Lee, and M. M. Jovanovic, “An improved full-bridge
zero-voltage-switched PWM converter using a saturable inductor,”
IEEE Trans. Power Electron., vol. 8, no. 4, pp. 530-534, Oct. 1993.
[9] R. Waston and F. Lee, “Analysis, design, and experimental results of a
1-kW ZVS-FB-PWM converter employing magamp secondary-side
control,” IEEE Trans. Ind. Electron., vol. 45, no. 5, pp. 806-813, Oct.
1998.
[10] R. Ayyanar and N. Mohan, “Novel soft-switching DC-DC converter
with full ZVS-range and reduced filter requirement—Part I: regulatedoutput applications,” IEEE Trans. Power Electron., vol. 16, no. 2, pp.
184-192, Mar. 2001.
[11] K. Park, C. Kim, G. Moon, and M. Youn, “Voltage oscillation
reduction technique for phase-shift full-bridge converter,” IEEE Trans.
Ind. Electron., vol. 54, no. 5, pp. 2779-2790, Oct. 2007.
1453