A Control Method in d-q Synchronous Frame for PWM Boost
Rectifier under Generalized Unbalanced Operating Conditions
Yongsug Suh, Pier G. Albano, Valentin Tijeras, and Thomas A. Lipo
University of Wisconsin − Madison
1415 Engineering Drive
Madison, WI 53706, USA
Abstract— This paper proposes a new control scheme of
regulating the instantaneous power for the pwm boost type
rectifier under generalized unbalanced operating conditions. By
nullifying the oscillating components of the instantaneous power
at the poles of the converter instead of the front-end through
solving a set of nonlinear control equations in real time, the
harmonics in the output dc voltage can be eliminated more
effectively under generalized unbalanced operating conditions in
ac input side. The control scheme allows the pwm rectifier to
generate a dc output without substantial even-order harmonics
and to maintain nearly unity power factor under generalized
unbalanced operating conditions, which makes it possible to
reduce the size of the dc-link capacitor and ac inductors leading
to the reduced total cost. Simulation results along with an
experimental result for the open-loop control using a laboratory
prototype converter confirm the feasibility of the new control
method. Experimental verification for the complete closed-loop
control is in progress.
I. INTRODUCTION
The pwm ac/dc converter has been increasingly employed
in the recent years owing to its advanced features including
sinusoidal input current at unity power factor and high quality
dc output voltage with a filter capacitor of small size. These
features are not necessarily achieved under the operating
conditions of unbalanced input supply and unbalanced input
impedances. Such a generalized unbalanced operating
condition is quite common in power systems, particularly in a
weak ac system. Unevenly distributed single-phase loads or
nonsymmetrical transformer windings as well as faults could
lead to a generalized unbalanced network. It has been shown
that unbalanced input voltages or impedances result in the
appearance of even harmonics at the dc output and odd
harmonics in the input currents [1]. Therefore pwm ac/dc
converters under generalized unbalanced operating conditions
necessitate the use of input/output filter of large size and
thereby completely offset several advantages of the pwm
ac/dc converter [5].
Stankovic and Lipo [1] and Enjeti and Choudhury [5] have
proposed methods to eliminate the input-output harmonics of
the boost and buck type rectifier, respectively. These methods
suffer from two disadvantages: the power factor cannot be
adjusted and the methods cannot operate well under the
extreme unbalanced operating conditions such as unbalanced
two-phase input or single-phase systems that often appear
during the faults in power systems. Rioual et al. [4] and Song
and Nam [3] derived control schemes regulating the
instantaneous power at the input of the converter in dq
synchronous frame for eliminating harmonics of the boost
type rectifier under unbalanced input supply. These
approaches only reduce harmonics but do not eliminate them.
In addition, these schemes cannot be applied under the
extreme unbalanced input supply. Stankovic and Lipo [2]
addressed the cases of the generalized unbalanced operating
conditions. However the proposed control algorithm is a
feed-forward method in phasor notation that does not regulate
the instantaneous power explicitly so that it is not suitable for
implementing with the feedback controlled space vector pwm
in a d-q synchronous frame.
This paper proposes a new control scheme for the pwm
boost type rectifier under generalized unbalanced operating
conditions. The positive and negative sequence d-q
components of the input voltages, pole voltages, and currents
in the synchronous frame are employed to accurately describe
the behavior of the ac/dc converter. The proposed technique
nullifies the oscillating components of the instantaneous
power at the poles of the converter so that harmonics in the
output dc voltage can be eliminated under generalized
unbalanced operating conditions in ac input side. Regulating
the instantaneous power at the poles of the converter needs to
compute a set of nonlinear equation in real time in order to
obtain the references of the input currents in the synchronous
frame. The proposed control scheme allows the pwm rectifier
to generate a dc output without substantial even-order
harmonics and to maintain nearly unity power factor under
generalized unbalanced operating conditions, which makes it
possible to reduce the size of the dc-link capacitor and ac
inductor. An unbalanced condition of a transformer
sinusoidal secondary voltage with center tapped neutral and
the unbalanced impedances was chosen to be an example of
the extreme unbalanced operating condition for the purpose
of simulation and experiment. This particular operating
condition is commonly found in the residential area where
both 110Vac and 220Vac input voltages are available.
Simulation and experimental results confirm the proposed
control method.
II. MODEL OF PWM BOOST RECTIFIER UNDER
GENERALIZED UNBALANCED OPERATING CONDITIONS
It is possible to represent an unbalanced three-phase input
voltage without a zero sequence as the orthogonal sum of
n
p
positive and negative sequence. Edq and Edq are transformed
space vectors in the positive and negative synchronous
rotating frame respectively.
-jωt n 2
jωt p
Edq = ( Ea + a Eb + a2 Ec )
Edqs = e Edq + e
3
(1)
p
p
p -jωt
p
p 2 p
= Ed + j Eq
Edq = ( Ea + a E b + a2 Ec ) e
3
(2)
é in ù é
2 êQo ú ê
=
3
in
P
ê s2 ú ê
ë Pc2in û ë
n 2 n
n
n
n jωt
n
Edq = ( Ea + a E b + a2 Ec ) e = Ed + j Eq
3
(3)
-1
[ Idq ] = [ Edq ] [ Sin ]
j(2π/3)
where a = e
.
n
p
p n
Idq, Idq, Vdq, and Vdq can be defined in the same manner
n
p
as in Edq and Edq. The conventional electrical equations on
the ac side of the pwm ac/dc converter are shown in (4), (5).
d p
p
p
p
p
Edq = Vdq + L Idq + jωL Idq + R Idq
dt
(4)
d n
n
n
n
n
Edq = Vdq + L Idq - jωL Idq + R Idq
dt
(5)
in
Po
2 in
P
3 o
0
0
0
ù é
ú= ê
ú ê
û ë
p
Ed
p
Eq
n
Eq
n
Ed
p
Eq
p
-Ed
n
-Ed
n
Eq
n
Ed
n
Eq
p
-Eq
p
Ed
ù
ú
ú
û
(9)
In the specific case of the unbalance condition introduced
in this paper as shown in Fig. 1, this approach cannot be
applied because the matrix of [ Edq ] is singular.
n
n p
p
Ed = -Ed, Eq = -Eq
Þ Det [ Edq ] = (Edp)2 + (Epq)2 - (End)2 - (Enq)2 = 0
SW 1
Ea
La
Ra
(10)
Ein
AC
SW 3
SW 5
Ia
Va
Iin
Eb
Lb
Rb
Ib
Vb
Cdc
Rdc
N
Ec
Lc
Rc
Ic
Vc
*
Sin = Edqs Idqs
SW 4
(6)
in
in in
Sin = (P o +Pc2cos(2ωt)+Ps2sin(2ωt))
in
in in
+ j(Q o +Qc2cos(2ωt)+Qs2sin(2ωt))
n
-Ed
p
Id
p
Iq
n
Id
n
Iq
(8)
Idc
The input complex power of the converter is given in (6).
At most six real and imaginary terms are found in Sin
considering only the first harmonics of the input voltage and
current.
3 jωt p
-jωt n *
jωt p
-jωt n
= ( e Edq + e
Idq )
Edq ) ( e Idq + e
2
ùé
úê
p
Ed ú ê
p
Eq û ë
n
Eq
SW 6
SW 2
Fig. 1. Three-pole pwm ac/dc converter with input center tapped transformer.
III. CONTROL STRATEGY
(7)
in
In order to cancel 120-Hz ripple in the dc output Ps2 and
in
Pc2 are set to zero [3], [4]. The average reactive power
exchanged between the utility source and the converter
in
becomes zero by nullifying Q o leading to unity power factor
[3], [4]. These conditions are incorporated into the following
matrix equation (8). The positive and negative dqcomponents of the currents in the synchronous frame are
regulated to the reference values obtained from (9).
The complex power in the dq reference frame is conserved
not only in the whole but also in each term by term as
expected from the orthogonality among average, cosine, and
sine terms in real and imaginary part of the complex power;
in
in in in in in in
P o , Pc2, Ps2, Q o , Qc2, Qs2. Therefore if the terms of Ps2
out
out
in
and Pc2 are compensated in the inductors then P s2 and P c2
calculated at the three poles of the converter become
vanished resulting in the dc output without 120-Hz ripple.
out
out
This can also be achieved by regulating P s2 and P c2 to zero
directly. Because the even-order harmonic contents in the dc
output voltage are due to the oscillatory active power
components applied through the three-pole ac/dc converter.
The output complex power, Sout is described as the
followings.
*
Sout = Vdqs Idqs
Vdc
=
3 jωt p
-jωt n *
jωt p
-jωt n
Idq ) (11)
Vdq ) ( e Idq + e
( e Vdq + e
2
Therefore,
out out
out
Real[Sout ] = (P o +P c2 cos(2ωt)+P s2 sin(2ωt))
(12)
The equations of (8) and (9) are linear while the equations
of (15) and (16) are nonlinear with respect to the four
unknown input current components. Therefore the following
set of nonlinear equations needs to be solved in real time to
obtain the reference input currents.
é
ù
p
p
n
n
êf2( Id , Iq , Id , Iq )ú
F(X) =
êf ( Ip , Ip , In , In )ú = 0
ê 3 pd pq nd nq ú
ëf4( Id , Iq , Id , Iq )û
p p n n
f1( Id , Iq , Id , Iq )
where
2 out
n p
n p
p n
p n
P
= Vd Id + Vq Iq + Vd Id + Vq Iq
3 c2
(13)
n p
n p
p n
p n
2 out
P
= Vq Id - Vd Iq - Vq Id + Vd Iq
3 s2
(14)
Applying (4) and (5) into (13) and (14) after being
decomposed in dq-axis under the assumptions of the steady
state and zero input resistances yield (15) and (16),
respectively.
n p
n p
n p
n p
p n
2 out
P
= Ed Id - ωL Iq Id + Eq Iq + ωL Id Iq + Ed Id
3 c2
p n
p n
p n
+ ωL Iq Id + Eq Iq - ωL Id Iq
(15)
n p
n p n p
n p p n
2 out
P
= Eq Id + ωL Id Id - Ed Iq + ωL Iq Iq- Eq Id
3 s2
p n
p n
p n
+ ωL Id Id + Ed Iq + ωL Iq Iq
(16)
where f1, f2, f3, and f4 represent (8), (15), and (16) with
in in out
out
the appropriate conditions on P o , Q o , P c2 , and P s2 .
In this paper, the new algorithm of calculating the positive
and negative dq-components of the input voltages in the
p n p n
synchronous frame( Ed, Ed, Eq, Eq ) from the measured abc
input voltages( Ea(t), Eb(t), Ec(t) ) is proposed. The control
block that performs this function is named as “Extractor of
positive & negative sequence dq components in synchronous
frame”. The detailed block diagram of this control algorithm
is described in Fig. 4.
In order to cancel 120-Hz ripple in the dc output voltage,
out
out
P c2 in (15) and P s2 in (16) should be set to zero.
Controller Stage of
AC/DC Converter
Vdc *
DC-link
Voltage
Regulator
Idp *, Iq p*
Pin*
Current
References
Calculating
Block
Positive
Sequence
Current
Regulator
Positive
Sequence
DQ-axes
Decoupler
Space
Vector
PWM
n*
Id , Iq
n*
Negative
Sequence
Current
Regulator
(17)
Gate
Drive
Block
SW 1
~ SW 6
Negative
Sequence
DQ-axes
Decoupler
Idn, Iq n
Id p, Iq p
Edn, Eq n
Ed p, Eq p
Extractor of
positive & negative
sequence
dq components in
synchronous frame
Extractor of
positive & negative
sequence
dq components in
synchronous frame
Ia
Ib
Ea
Eb
Ec
Vdc
Fig. 2. System block diagram.
Power
Stage of
AC/DC
Converter
Idp *
Edp
KpIdp
+KiIdp /s
Idp
ωL
Iqp
ωL
Vdp
ejωt
Iqp *
*
Kp Vdc Idc
+KiVdc/s
Vdc*
KpIqp
+KiIqp /s
Current
References
Calculating
Block
Pin*
Eqp
Id n
ωL
Iq n
ωL
Vdqs
Ed n
KpIdn
+Ki Idn /s
Idn *
Vdc
Vqp
Space
Vector
PWM
Vd n
e-jωt
Ed p, Eq p
Edn, Eq n
Iqn *
Vq n
KpIqn
+KiIqn /s
Eq n
Fig. 3. Detailed control block diagram.
The previous works found in [3], [4] utilized the low pass
filter to obtain the positive and negative dq-components.
However, the use of a filter typically introduces measurement
delay or phase delay of several cycles leading to the
inefficient transient characteristics. The newly proposed
control block in Fig. 4 generates the outputs within at most
2/3 of the input period under any type of unbalanced inputs.
Ea(t)
Eb(t)
Time delay
fb( t + (2π/3)/ω )
Ec(t)
Time delay
fc( t + (4π /3)/ω )
Eap (t)
Clarke
Transformation
Park
Transformation
Edp, Eq p
TABLE I
PARAMETERS USED IN THE SIMULATION & EXPERIMENT
Parameter
La, Lb
Lc
R
f
Value
1.9 mH
11.3 mH
1 mΩ
60 Hz
Parameter
Vdc*
Cdc
Rdc
Ein
Value
300 V
100 uF
100 Ω
100sin(ωt) V
1/3
Ea n(t)
Time delay
fb( t + (4π/3)/ω )
Clarke
Transformation
Park
Transformation
Fig. 4. Extractor of positive & negative sequence dq components in
synchronous frame.
IV. SIMULATION & EXPERIMENTAL RESULTS
The proposed control scheme was simulated using
SABER and Simulink . The simulation conditions are
summarized in Table I. The Broyden method was employed
to solve the nonlinear control equations in real time.
The active and reactive power components at the front
input of the converter, across the inductors, and at the poles
of the converter are calculated using Simulink . It is noted
from Fig. 5-7 that the complex power in the dq reference
frame is conserved not only in the whole but also in each
term by term as expected from the orthogonality among
average, cosine, and sine terms in real and imaginary part of
out
the complex power. The output active power(P (t)) in Fig.
in
7 is almost flat as compared to the P (t) in Fig. 5. This also
â
â
The simulation waveforms in Fig. 9, 10 are obtained using
SABER . It is noted that Vdc is regulated within ±5 V
around the nominal output voltage using Cdc of 100 uF. Ein
and Iin are in-phase leading to almost unity power factor.
These preferred results are accomplished by regulating the
positive and negative dq-components of the input currents to
the references of the currents calculated in (17).
The positive and negative dq-components of the input
p n p n
voltages in the synchronous frame( Ed, Ed, Eq, Eq ) obtained
from the measured abc input voltages( Ea(t), Eb(t), Ec(t) )
through Extractor of positive & negative sequence dq
components in synchronous frame are shown in Fig. 8. The
fluctuation of the output values in Fig. 8 for 2/3 of input
period is due to the intrinsic characteristic of the algorithm
that needs at most 2/3 of input period(16.67 ms × 2/3 = 11.11
p n p n
ms) to generate Ed, Ed, Eq, Eq.
Experimental results on a laboratory prototype pwm
rectifier are shown in Fig. 11 verifying the simulation results.
The DSP processor TMS320F240 was employed in the
control board. The waveforms in Fig. 11 were obtained under
the open-loop control.
â
Edn, Eq n
1/3
Time delay
fc( t + (2π /3)/ω )
â
out
out
confirms the fact that P s2 and P c2 are to be zero in
consistent with (15) and (16).
Input active and reactive power in the dq reference frame
2000
60
Pin(t)
Qin-avg
1800
40
1600
1400
20
1200
V oltage (V )
)
r
a
v(
r
e
w
o
p
e
vti
c
a
e
R
,)
W
(
r
e
w
o
p
e
vti
c
A
1000
800
E dp
E qp
E dn
E qn
0
600
-20
400
200
-40
0
-200
0.06
0.065
0.07
Time (sec)
0.075
0.08
Fig. 5. Input active and reactive power in the dq synchronous reference
frame of the simulation.
-60
0
0.02
0.04
0.06
Time (sec)
0.08
Fig. 8. Positive & negative sequence dq components of the input voltages
derived from the Extractor Block in the simulation.
Active and reactive power dissipated across inductors in the dq reference frame
1000
800
)
r
a
v(
r
e
w
o
p
e
vti
c
a
e
R
),
W
(
r
e
w
o
p
e
vi
ct
A
PL(t)
QL-avg
600
Vdc
400
200
0
Ic
Ia
Ib
-200
-400
Ea
Eb
Ec
-600
-800
-1000
0.06
0.065
0.07
Time (sec)
0.075
0.08
Fig. 9. Waveforms of the simulation.
Fig. 6. Active and reactive power dissipated across the inductors in the
dq synchronous reference frame of the simulation.
Output active and reactive power in the dq reference frame
Iin
1000
Ein
800
)
r
a
v(
r
e
w
o
p
e
vti
c
a
e
R
),
W
(
r
e
w
o
p
e
vi
ct
A
Ea
Pout(t)
Qout-avg
600
Ia
400
Eb
Ib
200
0
Ec
-200
Ic
-400
-600
Fig. 10. Waveforms of the simulation.
-800
-1000
0.06
0.065
0.07
Time (sec)
0.075
0.08
Fig. 7. Output active and reactive power in the dq synchronous reference
frame of the simulation.
0.1
400
Vdc
300
ACKNOWLEDGMENT
4*Ea
200
This work was supported primarily by the Center for
Power Electronics Systems. CPES is a National Science
Foundation ERC under Award Number EEC-9731677.
100
10*Ic
0
-100
-200
REFERENCES
-300
-400
0
0.01
0.02
0.03
Time [sec]
0.04
0.05
Fig. 11. Waveforms of the experiment.
V. CONCLUSION
This paper proposes a new control method for a line side
connected pwm ac/dc converter under generalized
unbalanced operating conditions. By nullifying the oscillating
components of the instantaneous power at the poles of the
converter instead of the front-end, the harmonics in the output
dc voltage can be eliminated under generalized unbalanced
operating conditions in ac input side. A proposed control
scheme needs to solve a set of nonlinear control equations
with respect to the input currents in real time. A nonlinear
equation solving algorithm called Broyden method was
selected and successfully built into the current reference
calculating block to operate in real time. An extreme
unbalanced operating condition of a transformer sinusoidal
secondary voltage with center tapped neutral and the
unbalanced impedances was chosen in this paper. The dc
output without substantial even-order harmonics and nearly
unity power factor in the ac side of the rectifier make it
possible to reduce the size of the output dc-link capacitor and
ac side inductors leading to the reduced total system cost.
Simulation and experimental results confirm the proposed
control method. Experimental verification for the complete
closed-loop control is in progress.
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Output Harmonic Elimination of the PWM Boost Type Rectifier Under
Unbalanced Operating Conditions", in Conf. Rec. APEC 2000, Vol. 1,
pp. 413-419.
[2] Ana V. Stankovic, T. A. Lipo, "A Generalized Control Method for
Input-Output Harmonic Elimination for the PWM Boost Rectifier Under
Simultaneous Unbalanced Input Voltages and Input Impedances", in
Conf. Rec. PESC 2001, Vol. 3, pp. 1309-1314.
[3] Hong-seok Song, Kwanghee Nam, "Dual Current Control Scheme for
PWM Converter Under Unbalanced Input Voltage Conditions", IEEE
Transactions on Industrial Electronics, Vol. 46, No. 5, October 1999, pp.
953-959.
[4] Pascal Rioual, Herve Pouliquen, Jean-Paul Louis, "Regulation of a
PWM Rectifier in the Unbalanced Network State Using a Generalized
Model", IEEE Transactions on Power Electronics, Vol. 11, No. 3, May
1996, pp. 495-502.
[5] Prasad N. Enjeti, Shamin A. Choudhury, "A New Control Strategy to
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[7] L. Moran, P.D. Ziogas, G. Joos, "Design Aspects of Synchronous PWM
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