EE143 F2010
Lecture 4
Electrical Contacts to Si
(1) Schottky (rectifying) contacts:
V
Al
SiO2
SiO2
depletion region
n-type Si
I
conducting
V
non-conducting
Majority carriers cannot move easily from the metal into the n-Si, due to a large potential barrier.
For the same metal, this potential barrier is smaller for contacts to p-type Si.
Al
SiO2
SiO2
p-type Si
Professor N Cheung, U.C. Berkeley
V
I
V
moderately conducting
1
EE143 F2010
Lecture 4
The depth of the depletion region ( xd ) decreases with increasing dopant concentration.
For very high doping, xd is small enough (<10nm) to allow quantum tunneling of carriers.
(2) Tunneling “ohmic” contacts:
V
SiO2
ND  1020 cm-3
n+
Al
SiO2
I
n-type Si
V
SiO2
NA  1020 cm-3
p+
p-type Si
V
Professor N Cheung, U.C. Berkeley
Al
SiO2
2
EE143 F2010
Lecture 4
Monolithic Integration:
Planar Technology
starting
substrate
+
*planar
processing
steps
=
monolithic integration of
multiple devices
Si wafer
n-channel MOSFET
*sequence of additive and subtractive steps with lateral patterning
e.g. oxidation
deposition
ion implantation
Professor N Cheung, U.C. Berkeley
e.g. etching
e.g. lithography
3
EE143 F2010
Process Flow Example #1
Lecture 4
Suspended Beam Array
Doped oxide (PSG) deposition (CVD)
(blanket addition)
Anchor patterning (litho. & etch)
(patterned subtraction)
Poly-Si deposition
(blanket addition)
Poly-Si beam patterning (litho. & etch)
(patterned subtraction)
Selective etch of PSG
(blanket subtraction)
Professor N Cheung, U.C. Berkeley
PSG = PhosphoSilicate Glass
(mixture of Phosphorus oxide and Silicon Oxide
prepared by CVD)
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EE143 F2010
Process Flow Example #2
Hinged Structure
Lecture 4
3 Lithography steps:
1) Hinge pattern
 out-of-plane movement 2) Staple anchor pattern
3) Staple pattern
Top view of masks
Professor N Cheung, U.C. Berkeley
Cross-sectional views
5
EE143 F2010
N-channel MOSFET
Lecture 4
Schematic Cross-Sectional View
Layout (Top View)
4 lithography steps
are required:
1. active area
2. gate electrode
3. contacts
4. metal interconnects
Professor N Cheung, U.C. Berkeley
6
EE143 F2010
Process Flow Example #3
Lecture 4
Simple nMOSFET Process Flow
Read Jaeger (textbook) Chap 1 for narrative description
1) Thermal oxidation
(~10 nm “pad oxide”)
2) Silicon-nitride (Si3N4)
deposition by CVD
(~40nm)
3) Active-area definition
(lithography & etch)
4) Boron ion implantation
(“channel stop” implant)
Professor N Cheung, U.C. Berkeley
7
EE143 F2010
Lecture 4
Process Flow Example #3 - cont
5) Thermal oxidation to grow
oxide in “field regions”
6) Si3N4 & pad oxide
removal
7) Thermal oxidation
(“gate oxide”)
8) Poly-Si deposition by CVD
Doping
Concentration
~1017/cm3
Top view of masks
9) Poly-Si gate-electrode
patterning (litho. & etch)
10) P or As ion implantation
to form n+ source and drain
regions
Professor N Cheung, U.C. Berkeley
Doping
Concentration
~1020/cm3
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EE143 F2010
Process Flow Example #3 cont.
Lecture 4
Top view of masks
11) SiO2 CVD
12) Contact holes
Definition (litho. & etch)
13) Al deposition
by sputtering
14) Al patterning
(litho. & etch)
to form interconnects
Professor N Cheung, U.C. Berkeley
9
EE143 F2010
Lecture 4
Example #4: CMOS Technology
Build both NMOS & PMOS transistors on a single
silicon chip
• N-MOSFETs need a p-type substrate
• P-MOSFETs need an n-type substrate
 What extra process steps will be needed ?
p+
p+
oxide
n-type Si
Professor N Cheung, U.C. Berkeley
n+
n+
p-well
EE143 F2010
Lecture 4
A Simplified Conceptual CMOS Process to illustrate process flow
n-type wafer
p+
*Create “p-well”
p+
oxide
n+
n-type Si
Grow thick oxide
n+
p-well
*Remove thick oxide in transistor areas (“active region”)
Grow gate oxide
Deposit & *pattern poly-Si gate electrodes
*Dope n channel source and drains (need to protect PMOS areas)
*Dope p-channel source and drains (need to protect NMOS areas)
Deposit insulating layer (oxide)
*Open contact holes
→ At least 3 more masks, as
compared to NMOS process
Deposit and *pattern metal interconnects
Professor N Cheung, U.C. Berkeley
**A detailed CMOS Process will be presented later in course when we study Process Integration
EE143 F2010
Additional Process Steps Discussion
Lecture 4
1. Well Formation
Top view of p-well mask
Cross-sectional view of wafer
boron
SiO2
p-well
n-type Si
- grow oxide layer; pattern oxide using p-well mask
- implant boron; anneal to form deep p-type region
Professor N Cheung, U.C. Berkeley
EE143 F2010
Lecture 4
2. Masking the two different Source/Drain Implants
“Select pchannel”
We must protect the n-channel devices during
the boron implantation step, and
“Select nchannel”
We must protect the p-channel devices during
the arsenic implantation step
Example: Select p-channel, use photoresist as boron implantation mask
boron
photoresist
p+
p+
oxide
n-type Si
Professor N Cheung, U.C. Berkeley
n+
n+
p-well