EE143 F2010
Lecture 18
IC Process Integration
Self-aligned Techniques
• LOCOS- self-aligned channel stop
• Self-aligned Source/Drain
• Lightly Doped Drain (LDD)
• Self-aligned silicide (SALICIDE)
• Self-aligned oxide gap
Example IC Process Flows
• Simple resistor
• NMOS - Generic NMOS Process Flow
• CMOS - Generic CMOS Process Flow
Advance MOS Techniques
• Twin Well CMOS , Retrograde Wells , SOI CMOS
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EE143 F2010
Lecture 18
Self-aligned channel stop
with Local Oxidation (LOCOS)
LOCOS Process Flow
Si3N4 CVD
pad oxide
Si
Professor N Cheung, U.C. Berkeley
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EE143 F2010
Lecture 18
B+ channel
stop
implant
dose
~1013/cm2
B
Si
thermal oxidation
(high temperature)
FOX
p
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p
Self-aligned
channel stop
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EE143 F2010
Lecture 18
Comment: Field Oxide Channel Inversion
If poly or metal lines lie on top of the Field Oxide (FOX), they will
form a parasitic MOS structure.If these lines carrying a high voltage,
they may create an inversion layer of free carriers at the Si substrate
and shorts out neighboring devices. The relatively highly doped Si
underneath (the “channel stop”) raises the threshold voltage of
this parasitic MOS. If this threshold voltage value is higher than
the highest circuit voltage, inversion will not occur.
Device 1
metal
Device 2
SiO2
Inversion
Layer
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p-Si
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EE143 F2010
Lecture 18
Comments : Non self-aligned alternative:
B+
2
1
P.R.
SiO2
P+
P+
3
SiO2
P+
Si
P+
Disadvantages
1 Two lithography steps
2 Channel stop doping not FOX aligned
Professor N Cheung, U.C. Berkeley
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EE143 F2010
Lecture 18
Self-aligned Source and Drain
As+
poly-Si gate
Perfect Alignment
n+
n+
As+
Off Alignment
n+
n+
* The n+ S/D always follows gate
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EE143 F2010
Lecture 18
Comment: Non self-aligned Alternative
.
n+
n+
n+
n+
1
.
2
Channel not linked to S/D
n+
.
n+
Solution: Use
gate overlap
to avoid offset
error.
Stray
capacitance
Disadvantages: Two lithography steps, excess gate overlap capacitance
Professor N Cheung, U.C. Berkeley
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EE143 F2010
Lecture 18
Lightly Doped Drain (LDD)
LDD
(1E17-to 1E18/cm3)
Source/Drain
(1E20-to 1E21/cm3)
Professor N Cheung, U.C. Berkeley
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EE143 F2010
Lecture 18
Lightly Doped Source/Drain MOSFET (LDD)
CVD oxide
spacer
n+
n
n
SiO2
n+
p-sub
The n-pockets (LDD) doped to medium conc (~1E18) are used to
smear out the strong E-field between the channel and heavily doped n+
S/D, in order to reduce hot-carrier generation.
Professor N Cheung, U.C. Berkeley
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EE143 F2010
Lecture 18
LDD Process Flow using Ion Implantation
n implant
for LDD
CVD conformal
deposition SiO2
CVD SiO2
SiO2
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EE143 F2010
Lecture 18
Spacer left when CVD SiO2
is just cleared on flat region.
Directional RIE of CVD Oxide
n
n
n+ implant
n+
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n
n
n+
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EE143 F2010
Lecture 18
RIE-based Stringers / Spacers
Leftover material must be removed by overetching
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EE143 F2010
Lecture 18
Self-Aligned Silicide Process (SALICIDE) using Ion
Implantation and Metal-Si reaction
poly-gate
n+
TiSi2 (metal)
n+
Metal silicides are metallic.
They lower the sheet resistance of S/D and the poly-gate
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EE143 F2010
Lecture 18
SALICIDE Process Flow
oxide spacer
n+
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n+
SiO2
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EE143 F2010
Lecture 18
Ti deposition
Ti
n+
n+
SiO2
Si
TiSi2
Ti
Ti
Ti
heat treatment ( 700o C )
Ti  2 Si  TiSi2
Ti will not react with SiO2 .
Selective etch to remove
unreacted Ti only
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EE143 F2010
Lecture 18
Salicide Gate and Source/Drain
Professor N Cheung, U.C. Berkeley
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EE143 F2010
Lecture 18
Self-aligned Oxide Gap
DRAM structure ( MOSFET with a capacitor)
Thermal Oxide grown
conformal on poly-I
small oxide spacing < 30nm
poly-II
poly-I
Gate
oxide
n+
substrate
poly-I
MOSFET
Professor N Cheung, U.C. Berkeley
For a small spacing
between poly-I and
poly-II, inversion
charges between
MOSFET and
Capacitor are
electrically linked. No
need for a separate
n+ island.
inversion
charge layer
MOS
Capacitor
poly-II
V (plate)
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EE143 F2010
Lecture 18
Process Flow Example : Resistor
Three-mask process:
Starting material: p-type wafer with NA = 1016 cm-3
Step 1: grow 500 nm of SiO2
Step 2: pattern oxide using the oxide mask (dark field)
Step 3: implant phosphorus and anneal to form an n-type
layer with ND = 1020 cm-3 and depth 100 nm
Step 4: deposit oxide to a thickness of 500 nm
Step 5: pattern deposited oxide using the contact mask (dark field)
Step 6: deposit aluminum to a thickness of 1 m
Step 7: pattern using the aluminum mask (clear field)
Layout:
Oxide mask (dark field)
Contact mask (dark field)
A
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A
Al mask (clear field)
EE143 F2010
Lecture 18
A-A Cross-Section
Step 2:
Pattern oxide
oxide etchant
SiO2
photoresist
patterned using
mask #1
p-type Si
Step 3: Implant
& Anneal
phosphorus ions
phosphorus implant:
p-type Si
after anneal of
phosphorus implant:
n+ layer
p-type Si
lateral diffusion of phosphorus
under oxide during anneal
Professor N Cheung, U.C. Berkeley
phosphorus
blocked by oxide
EE143 F2010
Lecture 18
Step 4: Deposit
500 nm oxide
2nd layer of SiO2
n+ layer
1st layer of SiO2
p-type Si
Step 5:
Pattern oxide
Open holes for metal contacts
n+ layer
p-type Si
Step 7:
Pattern metal
Al
n+ layer
p-type Si
Professor N Cheung, U.C. Berkeley
EE143 F2010
Lecture 18
Generic NMOS Process Flow Description
Substrate
Boron doped (100)Si
Resistivity= 20 -cm
Thermal
Oxidation
~100Å pad oxide
CVD Si3N4
~ 0.1 um
Lithography
Pattern Field Oxide
Regions
RIE removal of
Nitride and pad
oxide
Channel Stop
Implant:
3x1012 B/cm2
60keV
Thermal Oxidation
to grow 0.45um
oxide
Wet Etch
Nitrdie and
pad oxide
Ion Implant for
Threshold
Voltage control
8x1011 B/cm2 35keV
Thermal Oxidation
To grow 250Å
gate oxide
LPCVD
Poly-Si
~ 0.35um
Dope Poly-Si to n+
with Phosphorus
Diffusion source
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EE143 F2010
Lecture 18
Generic NMOS Process Flow Description (cont.)
Lithography
Poly-Si
Gate pattern
RIE
Poly-Si
gate
Source /Drain
Implantation
~ 1016 As/cm2 80keV
Thermal Oxidation
Grow ~0.1um oxide
on poly-Si
And source/drian
LPCVD
SiO2
~0.35um
Lithography
Contact
Window pattern
RIE removal of
CVD oxide and
thermal oxide
Sputter Deposit
Al metal
~0.7um
Lithography
Al interconnect
pattern
RIE etch of
Al metallization
Professor N Cheung, U.C. Berkeley
Sintering at ~400oC in H2 ambient
to improve contact resistance
and to reduce oxide interface charge
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EE143 F2010
Lecture 18
NMOS Structure
Generic NMOS Process Flow
Boron-doped Si
20 -cm
<100>
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active
device
~5 m
p-Si <100>
500m
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EE143 F2010
Lecture 18
P.R.
nitride
SiO2
Si
nitride
P.R.
SiO2
B : 3  1012 / cm 2
60keV
~0.1m
3  1017 / cm3
Si
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EE143 F2010
Lecture 18
Fox
p+
B
p+
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p+
5 1011 / cm2 35keV
Fox
p+
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EE143 F2010
Lecture 18
As+ 80keV, 1016/cm2
Resist
n+
n+
Thermal oxide
n+
Professor N Cheung, U.C. Berkeley
n+
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EE143 F2010
Lecture 18
intermediate
oxide
Al
CVD oxide
n+
n+
Al
H2 anneal
~ 400oC
(forming gas
is 10% H2
and 90%
N2)
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n+
n+
Si/SiO2 Interface
States Passivation
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EE143 F2010
Lecture 18
Basic Structure of CMOS Inverter
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EE143 F2010
Lecture 18
A Generic
CMOS Process
P-well CMOS
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EE143 F2010
Lecture 18
Pattern mask opening
For p-well implant
Shallow implantation
of boron
Diffusion drive-in
To form p-well in
oxidizing ambient
Remove masking oxide
Professor N Cheung, U.C. Berkeley
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EE143 F2010
Lecture 18
Pad oxide growth and CVD Si3N4.
Pattern field oxide regions
Blanket implant of Boron for p
channel stop inside p-well
Protect p-well regions with
photoresist.
Implant Ph to form n channel
stop outside p-well regions
LOCOS Oxidation
Thermal oxidation of gate SiO2
Professor N Cheung, U.C. Berkeley
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EE143 F2010
Lecture 18
CVD poly-Si
Pattern poly-Si gates and poly lines
Protect ALL n-channel
transistors with photoresist.
Boron implantation to
form source/drain of pchannel transistors and
contacts to p-well
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EE143 F2010
Lecture 18
Protect ALL p-channel
transistors with photoresist.
Arsenic implantation to form
source/drain of n-channel
transistors and contacts to nsubstrate
CVD SiO2
(Low-temperature oxide)
Pattern and etch contact
openings to source/drain, well
contact, and substrate contact.
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EE143 F2010
Lecture 18
Metal 1 deposition
Pattern and etch
Metal 1 interconnects
CVD SiO2
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EE143 F2010
Lecture 18
Pattern and etch contact
openings to Metal 1.
Metal 2 deposition.
Pattern, and etch Metal 2
interconnects.
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