Why Higher Resistivity Wafers?
Normal silicon wafer substrate resistivity ranges for CMOS technologies have typically
spanned from a low of about 5 mohm-cm on heavily doped epi substrates to a high of
around 30 ohm-cm on polished wafers. Although heavily doped substrates have proven
useful for protection against latch-up, digital CMOS device design and performance has
not been strongly coupled directly to substrate resistivity. This is changing in the
emerging area of CMOS integration of radio frequency transceiver devices operating in
the GHz frequency range.
Wireless chip designs can benefit significantly from higher substrate resistivity levels.
Improvements in the performance of passive components, such as inductors, and
substrate electrical isolation between the integrated digital, RF (radio frequency), and
analog components are possible with higher resistivity silicon substrates Substrate
resistivities greater than 40 ohm-cm are required now and in some cases resistivities in
excess of 1000 ohm-cm will be needed.
High Resistivity Wafer Requirements
Key characteristics of a high resistivity or ultra-high resistivity silicon wafer are 1) a
uniform resistivity through the thickness of the wafer, 2) acceptable radial and axial
resistivity gradients, and 3) a resistivity that remains stable throughout device
processing. These characteristics are dependent on crystal growth and the control of
oxygen behavior.
To support RF-CMOS process technologies scaled to the 0.1um design rule and
smaller, wafers must be available in large diameter sizes like 200mm and 300mm, and
must support all the advanced wafer parametrics such as site flatness and
nanotopography. Wafers must also be available in a COP-free form to achieve a very
low wafer defect density for high yielding, highly integrated devices (COP is vacancy
agglomerated defect from crystal growth that intersects final wafer surface). The
additional capability for metallic gettering protection via oxygen precipitates is also
desirable. CZ products such as Optia (COP-free polished wafer enhanced with MDZ),
Aegis (P/P- epi wafer enhanced with MDZ), or Ar-Annealed wafers are best positioned to
satisfy all these requirements for the case of high resistivity wafers up to 100ohm-cm.
High resistivity wafers up to 100 ohm-cm are currently used in RF applications and
satisfy the current performance requirements.
As wireless standards move to even higher GHz range frequencies, ultra-high resistivity
wafers will be needed in order to maintain acceptable inductor quality factors and to
minimize cross-talk between transistors. It’s expected that the ultra-high resistivity
requirement will emerge in the 2004-2005 timeframe. Ultra-high resistivity wafers into
the 1000 ohm-cm range pose some additional challenges for CZ wafers that will be
discussed in the next sections.
High and Ultra-High Resistivity Crystal Growth
Growth of CZ crystals to 100 ohm-cm with acceptable resistivity gradients is easily
achieved using existing growth processes. The amount of dopant added to the crystal
is simply reduced in order to target the higher resistivity range. The rest of the crystal
growth process parameters, as well as final wafer product characteristics, remain
unchanged.
Growth of CZ crystals to the 1000 ohm-cm range presents some additional challenges.
Because the amount of background dopant has to be significantly reduced, additional
emphasis must be placed on the control of dopants, such as boron and phosphorous,
introduced from the raw materials and components used in the crystal puller. These
materials and components include the polysilicon source, the quartz crucible, and the
graphite heater. In addition, the extremely low dopant level in the melt makes control of
dopant mass transfer to, and then through, the boundary layer at the melt-solid interface
important for achieving acceptable radial resistivity variation. By employing high purity
puller components, and by optimizing dopant flow in the melt, MEMC R&D has
successfully developed the capability to grow CZ crystals with maximum resistivities into
the 1000 ohm-cm range using existing 200/300mm crystal pulling equipment. Accurate
and reproducible measurements of these ultra-high resistivities is also a challenge that
must be addressed but will not be discussed in detail here.
Oxygen Challenge for High and Ultra-High Resistivity CZ Wafer
The main challenge for higher resistivity CZ silicon is to control the behavior of the
interstitial oxygen incorporated during crystal growth. The interstitial oxygen
concentration is usually greater than 5E17at/cc (10ppma new-ASTM). Interstitial oxygen
can be converted beneficially into oxygen precipitates below the device area in order to
getter metallic contaminants away from active devices. But residual interstitial oxygen
can form electrically active donor states during the low temperature metal annealing
process performed at the end of the device fabrication process. The formation of
oxygen thermal donors depends strongly on both interstitial oxygen concentration and
annealing time and temperature in the range of 350-500C. The oxygen thermal donors
contribute electrons to conduction which can, depending on the number of donors
generated versus the background carrier concentration of the wafer, alter the resistivity
of the wafer.
In p-type silicon, thermal donors increase the resistivity of the wafer until the thermal
donor concentration exceeds the p-type carrier concentration, at which point the wafer
will appear to be n-type. Calculations made based on experimental data illustrating the
influence of thermal donors on a 50 ohm-cm p-type wafer resistivity for varying interstitial
oxygen levels and 400C annealing times are shown in figure 1. Wafers with <12.5 ppma
of interstitial oxygen can tolerate several hours of 400C annealing and still maintain a
resistivity between 50 and 100 ohm-cm. The highest oxygen case shows the increase in
p-type wafer resistivity with the formation of oxygen thermal donors and eventually a
change in wafer type after several hours of 400C annealing. This example shows that
with proper targetting of initial and final oxygen levels, taking into account the amount of
oxygen consumed to precipitates in the device fabrication thermal processes, that higher
resistivity wafers up to ~ 100 ohm-cm exhibit acceptable resistivity stability.
10000
N-type: thermal
donors > background
Compensation by
thermal donors
1000
Final (Oi)
(Oi)=8.5ppm
(Oi)=10.5ppm
(Oi)=12.5ppm
(Oi)=14.5ppm
100
10
0
2
4
6
8
10
12
Time of anneal 400C (hrs)
Figure 1: resistivity change in 50 ohm-cm p-type wafer with interstitial oxygen and
anneal time at 400C.
As the wafer resistivity is increased well beyond 100 ohm-cm the sensitivity to oxygen
thermal donors becomes more severe. The background carrier concentration in a
1000 ohm-cm p-type wafer is ~ 1E13 at/cc, ten times smaller than for a 100 ohm-cm
wafer. So the change in wafer resistivity induced by thermal donors occurs more rapidly
in low temperature annealing. In order to prevent excessive shifts in very high
resistivity wafers, the interstitial oxygen must be reduced to lower levels. Figure 2
illustrates the sensitivity of a 1000 ohm-cm p-type wafer to varying interstitial oxygen
levels and annealing at 400C. As compared with the earlier 50 ohm-cm example, the
final oxygen level must be much lower, <5ppma new-ASTM, in a 1000 ohm-cm wafer in
order maintain acceptable resistivity stability in the metal anneals performed near the
end of the device fabrication process.
10000
Final Resistivity (ohm cm)
N-type: thermal
donors > background
Compensation by
thermal donors
Final (Oi)
new-ASTM
(Oi)=2.5ppm
1000
(Oi)=5ppm
(Oi)=7.5ppm
(Oi)=10ppm
100
0
2
4
6
8
10
12
Time of anneal 400C (hrs)
Figure 2: resistivity change in 1000ohm-cm p-type wafer with interstitial oxygen and
anneal time at 400C.
As mentioned earlier, a normal CZ crystal has >= 10 ppma interstitial oxygen.
It is
difficult to grow CZ crystals to oxygen levels < 5 pmma. A straightforward approach to
reducing interstitial oxygen to the low level needed for resistivity stability is to precipitate
the interstitial oxygen out of solution. Some oxygen precipitation normally happens
during the thermal cycles in a device fabrication process. But in the low thermal budget
process of today’s advanced CMOS processes there is not sufficient thermal process
time at temperature to achieve the oxygen reduction necessary for ultra-high resistivity
wafers. As a result, the wafer supplier may have to perform the processing to
precipitate out the interstitial oxygen The conventional approach to oxygen
precipitation requires a thermal cycle with hours of nucleation, stabilization, and growth.
Optimization of the wafer and the thermal process are necessary to minimize the costs
associated with furnace annealing and to insure consistency in interstitial oxygen
reduction. Optimizations can include the use of MDZ to greatly accelerate the
nucleation, the addition of nitrogen during crystal growth to enhance oxygen precipitate
formation during crystal growth, and an optimized furnace growth cycle that maximizes
oxygen consumption into the growing oxygen precipitates. Data showing high oxygen
loss using wafers enhanced with MDZ and using an optimized thermal cycle is shown in
figure 3. It shows the initial interstitial oxygen with radial position and the final interstitial
oxygen level following the optimized thermal process. This demonstrates a method for
producing a wafer with final oxygen low enough to insure resistivity stability of a
1000ohm-cm wafer in the low temperature metal anneals.
High (Oi) Loss Thermal Cycle
Oxygen (ppma)
16
14
12
10
Initial Oxygen
8
Final Oxygen
6
4
2
0
0
20
40
60
80
100
Radial Position (mm)
Figure 3: initial oxygen with radial position.
High and Ultra-High Resistivity Products
High resistivity, 40-100ohm-cm, 200mm and 300mm products are being supplied in
volume now for RF applications. COP-free product options include P/P- epitaxial wafer
such as Aegis with MDZ, Optia with MDZ, and Ar-Annealed. For lower device density
applications high resistivity polished wafers with a moderate density of COPs and
enhanced with MDZ have been successfully qualified.
An ultra-high resistivity
200/300mm product, combining crystal growth improvements and wafer annealing, is
also available. All of these products are available with the advanced wafer parametrics
expected for deep submicron CMOS technologies.