Page 1
MOS Models (5/23/00)
1.8 - MOSFET MODELS
INTRODUCTION
Objective
The objective of this presentation is:
1.) Understand how the MOS transistor works
2.) Understand and apply the simple large signal model
3.) Understand and apply the small-signal model
Outline
• MOS Structure and Operation
• Large Signal Model
• Small-Signal Model
• Capacitance
• Short Channel Large Signal Model
• Subthreshold Large Signal Model
• Summary
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 2
MOS Models (5/23/00)
MOS STRUCTURE AND OPERATION
Metal-Oxide-Semiconductor Structure
Bulk/Substrate
,,,
,,,
Source
Gate
Drain
Polysilicon
p+
n+
Thin Oxide
(10-100nm
100Å-1000Å)
n+
p- substrate
Heavily
Doped p
Lightly
Doped p
Intrinsic
Doping
Lightly
Doped n
Heavily Metal
Doped n
Fig1.8-1
Terminals:
• Bulk - Used to make an ohmic contact to the substrate
• Gate - The gate voltage is applied in such a manner as to invert the doping of the material directly
beneath the gate to form a channel between the source and drain.
• Source - Source of the carriers flowing in the channel
• Drain - Collects the carriers flowing in the channel
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 3
MOS Models (5/23/00)
Formation of the Channel for an Enhancement MOS Transistor
Subthreshold (VG<VT)
VB = 0
,,,
,,,
,,,
,,,
VS = 0
VG < VT
VD = 0
Polysilicon
p+
p- substrate
Threshold (VG=VT)
VB = 0
n+
VS = 0
n+
VG =VT
VD = 0
Polysilicon
p+
p- substrate
n+
n+
Inverted Region
Strong Threshold (VG>VT)
VB = 0
VS = 0
VG >VT
VD = 0
Polysilicon
p+
p- substrate
ECE 4430 - Analog Integrated Circuits and Systems
n+
n+
Inverted Region
Fig1.8-2
© Phillip E. Allen 2000
Page 4
MOS Models (5/23/00)
The MOSFET Threshold Voltage
When the gate voltage reaches a value called the threshold voltage (VT), the substrate beneath the gate
becomes inverted (it changes from p-type to n-type).

Qb  QSS


V T = φ MS + -2 φ F Cox +  Cox 

where
φMS = φF(substrate) - φF(gate)
φF = Equilibrium electrostatic potential (Femi potential)
kT
φF(PMOS) = - q ln(NA/ni) = -Vt ln(NA/ni)
kT
φF(NMOS) = q ln(ND/ni) = Vt ln(ND/ni)
Qb ≈
2qNAεsi(|-2φF+vSB|)
QSS = undesired positive charge present in the interface between the oxide and the bulk silicon
Rewriting the threshold voltage expression gives,
Q b0 QSS Q b - Q b0
= V T0 + γ  |-2 φ F + v S B | V T = φ MS -2φ F - C - C Cox
ox
ox
where
Q b0 Q SS
2qεsiNA
V T0 = φ MS - 2φ F and
γ=
Cox - Cox
Cox
ECE 4430 - Analog Integrated Circuits and Systems
|-2φ F |
© Phillip E. Allen 2000
Page 5
MOS Models (5/23/00)
Signs for the Quantities in the Threshold Voltage Expression
Parameter
Substrate
φ MS
Metal
n+ Si Gate
p+ Si Gate
φF
Qb0,Qb
Qss
VSB
γ
ECE 4430 - Analog Integrated Circuits and Systems
N-Channel
p-type
P-Channel
n-type
−
−
+
−
−
+
+
+
−
−
+
+
+
+
−
−
© Phillip E. Allen 2000
Page 6
MOS Models (5/23/00)
Example 1 - Calculation of the Threshold Voltage
Find the threshold voltage and body factor γ for an n-channel transistor with an n+ silicon gate if tox =
200 •, NA = 3 × 1016 cm -3, gate doping, ND = 4 × 1019 cm -3, and if the positively-charged ions at the
oxide-silicon interface per area is 10 10 cm-2.
Solution
From above, φF(substrate) is given as
 3× 10 16

 = −0.377 V
1
0
 1.45 × 1 0 
φF(substrate) = −0.0259 ln 
The equilibrium electrostatic potential for the n+ polysilicon gate is found from as
 4 × 10 1 9 
 = 0.563 V
1.45 × 10 1 0
φF(gate) = 0.0259 ln 
Therefore, the potential φMS is found to be
φF(substrate) − φF(gate) = −0.940 V.
The oxide capacitance is given as
C ox = ε ox /tox =
3.9 × 8.854 × 10 -14
= 1.727 × 10-7 F/cm2
8
200 × 10
The fixed charge in the depletion region, Qb0, is given as
Qb0 = − [2 × 1.6 × 10-19 × 11.7 × 8.854 × 10-14 × 2 × 0.377 × 3 × 1016]1/2 = − 8.66 × 10-8 C/cm2.
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 7
MOS Models (5/23/00)
Example 1 - Continued
Dividing Qb0 by Cox gives −0.501 V. Finally, Qss/Cox is given as
Qss 10 10 × 1.60 × 10 -19
=
= 9.3 × 10-3 V
-7
Cox
1.727 × 10
Substituting these values for VT0 gives
V T0 = - 0.940 + 0.754 + 0.501 - 9.3 x 10-3 = 0.306 V
The body factor is found as
γ =
 2 × 1.6 × 10 -19 × 11.7 × 8.854 × 10 -14 × 3 × 10 1 6 
1.727 × 10
-7
ECE 4430 - Analog Integrated Circuits and Systems
1/2
= 0.577 V1/2
© Phillip E. Allen 2000
Page 8
MOS Models (5/23/00)
SIMPLE LARGE SIGNAL MOSFET MODEL
Large Signal Model Derivation
Derivation+
vGS
-
1.) Let the charge per unit area in the channel inversion
layer be
Q I(y) = -C ox[vGS - v(y) - VT] (coulombs/cm2)
2.) Define sheet conductivity of the inversion layer per
p-
n+
Source
v(y)
0
+
v
- DS
iD
dy
y y+dy
n+
Drain
L
y
square as
amps
1
 cm2  coulombs
σ S = µ oQ I(y)  v·s  cm2  = volt = Ω/sq.



3.) Ohm's Law for current in a sheet is
iD
-iD
-iDdy
dv
JS =
=
σ
E
=
σ
dv
=
dy
=
S y
S dy
→
µoQ I(y)W
W
σ SW
→
iD dy = -Wµ oQ I(y)dv
4.) Integrating along the channel for 0 to L gives
vD S
vD S
L
⌠
⌡iD dy = - ⌠
⌡Wµ oQ I(y)dv = ⌠
⌡Wµ o C ox [v GS -v(y)-V T ] dv
0
0
0
5.) Evaluating the limits gives
WµoCox 
v 2 (y) v D S
iD =
 (v GS -V T )v(y) 
→
L
2  0

ECE 4430 - Analog Integrated Circuits and Systems
W µ oC o x 
v DS 2 
 (v -V )v
iD =
- 2 
L
 GS T DS

© Phillip E. Allen 2000
Page 9
MOS Models (5/23/00)
Saturation Voltage - V D S(sat)
Interpretation of the large signal model:
iD
vDS = vGS - VT
Active Region
Saturation Region
Increasing
values of vGS
vDS
The saturation voltage for MOSFETs is the value of drain-source voltage at the peak of the inverted
parabolas.
diD µoCoxW
[(vGS -V T ) - vDS ] = 0
→
v D S (sat) = v G S - V T
dvDS =
L
Useful definitions:
µoCoxW K’W
= L =β
L
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 10
MOS Models (5/23/00)
Complete Large Signal Model
Regions of Operation of the MOS Transistor:
1.) Cutoff Region:
iD = 0,
v GS - V T < 0
(Ignores subthreshold currents)
2.) Active Region
µoCoxW
0 < v DS < v GS - V T
iD = 2L [ 2(v G S - V T ) - v D S] v DS ,
3.) Saturation Region
µoCoxW
v
- VT) 2 ,
0 < v GS - V T < v D S
iD =
2L ( G S
Output Characteristics of the MOSFET:
iD /ID0
vDS = vGS - VT
1.0
Active
Region
Saturation Region
0.75
Channel modulation effects
0.5
0.25
Cutoff Region
0
0
0.5
1.0
1.5
ECE 4430 - Analog Integrated Circuits and Systems
2.0
vGS-VT = 1.0
VGS0 - VT
vGS-VT = 0.867
VGS0 - VT
vGS-VT = 0.707
VGS0 - VT
vGS-VT = 0.5
VGS0 - VT
vGS-VT = 0
VGS0 - VT
vDS
VGS0 - VT
2.5
© Phillip E. Allen 2000
Page 11
MOS Models (5/23/00)
Influence of VD S on the Output Characteristics
Channel modulation effect:
As the value of vDS increases, it causes the effective L to decrease which causes the current to increase.
Illustration:
,,,
,,,,,,,
VG > VT
B
VD > VDS(sat)
S
Depletion
Region
Polysilicon
p+
,,,,,,,
n+
n+
Leff
p- substrate
Xd
Fig1.8-3
Note that Leff = L - Xd
Therefore the model in saturation becomes,
diD
dL eff
iD dX d
K’W
K’W
2
2
→
iD = 2L (v GS -V T )
dvDS = - 2Leff2 (v GS - V T ) dvDS = Leff dvDS ≡ λiD
eff
Therefore, a good approximation to the influence of vDS on iD is
diD
K’W
iD ≈ iD(vDS=0) + dv vDS = iD (vDS=0)(1 + λvDS) = 2L (v GS -V T )2(1+ λ v DS )
DS
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 12
MOS Models (5/23/00)
Influence of the Bulk Voltage on the Large Signal MOSFET Model
Illustration of the influence of the bulk:
VSB0 =0V
+
V SB0 = 0V:
Source
Bulk
VSB1
+
Gate
VGS>VT
Source
Bulk
Drain
VDS>0
Poly
n+
p+
n+
Substrate/Bulk
V SB2 > V SB1 :
-
VSB2
Gate
VGS>VT
+
Source
Bulk
p+
p-
n+
Substrate/Bulk
V SB1>0V:
p-
Drain
VDS>0
Poly
n+
p+
p-
Gate
VGS>VT
Drain
VDS>0
Poly
n+
n+
Substrate/Bulk
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 13
MOS Models (5/23/00)
Influence of the Bulk Voltage on the Large Signal MOSFET Model - Continued
Bulk-Source (vBS) influence on the transconductance characteristicsiD
Decreasing values
of bulk-source voltage
VBS = 0
vDS
vGS - VT
vGS
VT0
VT1
VT2
VT3
In general, the simple model incorporates the bulk effect into VT by the following empirically developed
equationV T (v BS ) = V T0 + γ
2| φ f | + |v BS | - γ
ECE 4430 - Analog Integrated Circuits and Systems
2| φ f |
© Phillip E. Allen 2000
Page 14
MOS Models (5/23/00)
MOSFET Schematic Symbols
Enhancement:
VBS ≠0V
D
NMOS
PMOS
G
B
Simple
VBS=0V
D
G
D
G
S
S
S
D
D
D
G
B
S
ECE 4430 - Analog Integrated Circuits and Systems
G
G
S
S
Fig1.8-4
© Phillip E. Allen 2000
Page 15
MOS Models (5/23/00)
Summary of the Simple Large Signal MOSFET Model
D
N-channel reference convention:
iD
G
+
+
+
vGS
B vDS
vBS
- -S
Non-saturationWµoCox 
vDS2
 (v
- V T )v D S - 2  (1 + λ vDS )
iD =
L
 GS

SaturationWµoCox 
v DS (sat) 2 
Wµ oC ox
2
 (v GS - V T )v DS (sat)  (1 + λ v DS ) =
iD =
L
2
2L (v GS - V T ) (1 + λ v DS )


where:
µo = zero field mobility (cm2/volt·sec)
Cox = gate oxide capacitance per unit area (F/cm2)
λ = channel-length modulation parameter (volts-1)
V T = V T0 + γ  2| φ f | + |v B S | - 2| φ f|
VT0 = zero bias threshold voltage
γ = bulk threshold parameter (volts-0.5)
2|φf| = strong inversion surface potential (volts)
For p-channel MOSFETs, use n-channel equations with p-channel parameters and invert current.
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 16
MOS Models (5/23/00)
MOSFET
Constants for Silicon:
Constant Symbol
VG
k
ni
ε0
εsi
εox
Constant Description
Silicon bandgap (27°C)
BoltzmannÕs constant
Intrinsic carrier concentration (27°C)
Value
Units
1.205
1.381x10-23
1.45x1010
8.854x10-14
11.7 ε0
Permittivity of free space
Permittivity of silicon
Permittivity of SiO2
V
J/K
cm-3
f/cm
F/cm
F/cm
3.9 ε0
Model Parameters for a Typical CMOS Bulk Process (0.8µm CMOS n-well):
Parameter
Parameter
Symbol
Description
Threshold Voltage
VT0
(VBS = 0)
K'
Transconductance
Parameter (in
saturation)
Bulk threshold
γ
parameter
Channel length
λ
modulation
parameter
Surface potential at
2|φF|
strong inversion
Typical Parameter Value
N-Channel
P-Channel
0.7 ± 0.15
−0.7 ± 0.15
Units
V
110.0 ± 10%
50.0 ± 10%
µA/V2
0.4
0.57
(V)1/2
0.04 (L=1 µm)
0.01 (L=2 µm)
0.05 (L = 1 µm)
0.01 (L = 2 µm)
(V)-1
0.7
0.8
V
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 17
MOS Models (5/23/00)
MOSFET SMALL SIGNAL MODEL
Small-Signal Model
Complete schematic model:
D
G
id
D
B
G
G
+
vgs
B
S
-
S
S
B
+
vbs
-
gmvgs
gmbsvbs
rds
+D
vds
-
S
Fig. 4.2-4
where
diD
| = β (V -V ) =
gm ≡ dv
GS T
GS Q
and
2 β ID
∂ιD
 ∂iD   ∂vGS 

gmbs = ∂v Q = ∂v  ∂v  = BS
 GS  BS  Q

diD
λiD
|
gds ≡ dv
=
≈ λ iD
DS Q 1 + λ v D S
gmγ
∂ i D  ∂vT 

 =
∂vT∂vBSQ 2 2| φ F | - V B S = ηgm
Simplified schematic model:
id
D
D
G
G
S
S
G
+
vgs
S
-
gmvgs
rds
+D
vds
-
S Fig. 4.2-2
Extremely important assumption:
g m ≈ 10g m b s ≈ 100g ds
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 18
MOS Models (5/23/00)
Illustration of the Small-Signal Model Application
DC resistor:
i
v
V
DC resistance = i  =
Q I
AC Resistance
• Useful for biasing - creating current from voltage and
vice versa
VT
Small-Signal Load (AC resistance):
D
G
S
G
v
VDS
Fig. 4-2-2B
id
D
B
DC Resistance
ID
G
B
S
+
vgs
S
-
B
+
vbs
-
gmvgs
gmbsvbs
rds
+D
vds
-
S
Fig. 4.2-4
vds
1
1
AC resistance = i = g + g ≈ g
d
m
ds
m
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 19
MOS Models (5/23/00)
Example 2 - Small-Signal Load Resistance
Find the small signal resistance of the MOS diode
shown using the parameters of Table 3.2-1.
Assume that the W/L ratio is 10µm/1µm.
Solution
If we are going to include the bulk effect, we must first find the dc value
of the bulk-source voltage. Unfortunately, we do not know the threshold
voltage because the bulk-source voltage is unknown. The best approach is to
ignore the bulk-source voltage, find the gate-source voltage and then iterate if
necessary.
VDD = 5V
rac
100µA
Fig. 4.2-5
2I
2·100
+
V
=
+ 0.7 = 1.126V
T0
β
110·10
Thus let us guess at a gate-source voltage of 1.3V (to account for the bulk effect) and calculate the resulting
gate-source voltage.
∴ VGS =
V T = V T0 + γ 2| φ F | - (-3.7) - γ 2|φF| = 0.7 + 0.4 0.7+3.7 - 0.4 0.7 = 1.20V ⇒ VGS = 1.63V
Now refine our guess at VGS as 1.6V and repeat the above to get VT = 1.175V which gives VGS = 1.60V.
Therefore, V BS = -3.4V.
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 20
MOS Models (5/23/00)
Example 2 - Continued
The small signal model for this example is shown.
The ac input resistance is found by,
iac = gdsvac - gmvgs - gmbsvbs
= gdsvac + gmvs + gmbsvs = vac(gm+gmbs+gds)
id
G,D,B
gmvgs
rds
gmbsvbs
rac
+
vds = vgs
vac
S
iac Fig. 4.2-6
vac
1
∴ rac = i = g +g +g
ac
m mbs ds
Now we must find the parameters which are,
2βID = 2·110·10·100 µS = 469µS, gds = 0.04V-1·100µA = 4µS,
469µS·0.4
= 0.0987·469µS = 46.33µS
and gmbs =
2 0.7+3.4
Finally,
gm =
106
rac = 469 + 46.33 + 4 = 1926Ω
If we had used the previous approximations of gm ≈ 10gmbs ≈ 100gds, then we could have simply let
1
1
rac ≈ g = 469 = 2132Ω
m
Probably the most important result of this approximation is that we would not have to find VBS which took
a lot of effort for little return.
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 21
MOS Models (5/23/00)
Small-Signal Model for the Active Region
∂iD |
K’WV DS
 K’W
gm =
=
(1+
λ
V
)
≈

 VD S
DS
∂ v GS Q
L
 L 
∂iD
K’W γ V D S
gmbs = ∂ v Q| =
BS
2L 2 φ F - V B S
∂iD
IDλ
K’W
gds = ∂v Q| = L ( V GS - V T - V DS )(1+ λ V DS ) + 1+λV
DS
DS
ECE 4430 - Analog Integrated Circuits and Systems
K’W
L (V GS - V T - V DS )
© Phillip E. Allen 2000
Page 22
MOS Models (5/23/00)
MOSFET CAPACITANCES
Types of Capacitance
Physical Picture:
SiO2
Gate
Source
C1
Drain
C2
C3
FOX
FOX
C4
CBS
Bulk
CBD
Fig1.8-5
MOSFET Capacitances consist of:
• Depletion capacitance
• Charge storage or parallel plate capacitance
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 23
MOS Models (5/23/00)
MOSFET Depletion Capacitors
Polysilicon gate
Model:
H
CJ·AS
CJSW·PS
C BS =
+
MJ
MJSW, v BS ≤ FC·PB
v B S
v B S


1 
1 
PB 
PB 


G
C
D
Source
Drain
F
E
A
and
V B S



1
(1+MJ)FC
+
MJ
C BS =
1+MJ 
PB

( 1- F C)
SiO2
CJ·AS
Bulk
Fig1.8-6
Drain bottom = ABCD
Drain sidewall = ABFE + BCGF + DCGH + ADHE
CBS
V B S


,
+
1
(1+MJSW)FC
+
MJSW
1+MJSW 
PB

( 1 - F C)
CJSW·PS
vBS> FC·PB
B
vBS ≥ FC·PB
vBS ≤ FC·PB
PB
where
AS = area of the source
PS = perimeter of the source
CJSW = zero bias, bulk source sidewall capacitance
MJSW = bulk-source sidewall grading coefficient
For the bulk-drain depletion capacitance replace "S" by "D" in the above.
ECE 4430 - Analog Integrated Circuits and Systems
vBS
FC·PB
Fig1.8-6B
© Phillip E. Allen 2000
Page 24
MOS Models (5/23/00)
Charge Storage (Parallel Plate) MOSFET Capacitances - C1 , C2 , C3 and C4
Mask L
Actual
L (Leff)
LD
Oxide encroachment
Actual
W (Weff)
Mask
W
Gate
Drain-gate overlap
capacitance CGD (C3)
Source-gate overlap
capacitance CGS (C1)
Gate
FOX
Source
Gate-Channel
Capacitance (C2)
Bulk
FOX
Drain
Channel-Bulk
Capacitance (C4)
Fig1.8-7
Overlap capacitances:
C1 = C3 = LD·Weff·Cox = CGSO or CGDO
(LD ≈ 0.015 µm for LDD structures)
Channel capacitances:
C2 = gate-to-channel = CoxW eff·(L-2LD) = CoxW eff·Leff
C4 = voltage dependent channel-bulk/substrate capacitance
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 25
MOS Models (5/23/00)
Charge Storage (Parallel Plate) MOSFET Capacitances - C5
View looking down the channel from source to drain
Overlap
Overlap
FOX C5
Gate
Source/Drain
C5 FOX
Bulk
Fig1.8-8
C5 = CGBO
Capacitance values and coefficients based on an oxide thickness of 140 Å or Cox=24.7 × 10−4 F/m2:
Type
CGSO
CGDO
CGBO
CJ
CJSW
MJ
MJSW
P-Channel
220 × 10−12
220 × 10−12
700 × 10−12
560 × 10−6
350 × 10−12
0.5
0.35
ECE 4430 - Analog Integrated Circuits and Systems
N-Channel
220 × 10−12
220 × 10−12
700 × 10−12
770 × 10−6
380 × 10−12
0.5
0.38
Units
F/m
F/m
F/m
F/m2
F/m
© Phillip E. Allen 2000
Page 26
MOS Models (5/23/00)
Expressions for CGD, CG S and CG B
Cutoff Region:
CGB = C2 + 2 C 5 = Cox(Weff)(Leff) + 2CGBO(Leff)
CGS = C1 ≈ Cox(LD)Weff) = CGSO(Weff)
CGD = C3 ≈ Cox(LD)Weff) = CGDO(Weff)
Cutoff
VB = 0
CGS
CGS = C1 +(2/3)C2 = Cox(LD+0.67Leff)(Weff)
= CGSO(Weff) + 0.67Cox(Weff)(Leff)
CGD = C3 ≈ Cox(LD)Weff) = CGDO(Weff)
p+
Saturated
VB = 0
p+
p- substrate
Active
VB = 0
Active Region:
CGB = 2 C 5 = 2CGBO(Leff)
CGS = C1 + 0.5C2 = Cox(LD+0.5Leff)(Weff)
= (CGSO + 0.5CoxLeff)Weff
CGD = C3 + 0.5C2 = Cox(LD+0.5Leff)(Weff)
VG < VT
Polysilicon
p- substrate
Saturation Region:
CGB = 2C5 = CGBO(Leff)
,,,
,,,
,,,
,,,
VS = 0
n+
VS = 0
CGS
n+
CGB
VG >VT
Polysilicon
n+
p- substrate
VD >VG -VT
CGD
n+
Inverted Region
VS = 0
CGS
VG >VT
Polysilicon
p+
VD > 0
CGD
n+
VD <VG -VT
CGD
n+
Inverted Region
Fig1.8-9
= (CGDO + 0.5CoxLeff)Weff
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 27
MOS Models (5/23/00)
Illustration of CGD, CG S and CG B
Capacitance
C4 Large
C2 + 2C5
CGS
C1+ 0.67C2
C1+ 0.5C2
C1, C3
2C5
0
CGS, CGD
vDS = constant
vBS = 0
C4 Small
CGS, CGD
CGD
CGB
Off
Saturation
VT
NonSaturation
vDS +VT
vGS
Fig1.8-10
Comments on the variation of CBG in the cutoff region:
1
CBG = 1
1 + 2C5
+ C
C2
4
For vGS ≈ 0, C GB ≈ C 2 + 2C 5
(C4 is large because of the thin inversion layer in weak inversion where VGS is slightly less than VT))
For 0<vGS V T, C GB ≈ 2C 5
(C4 is small because of the thicker inversion layer in strong inversion)
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 28
MOS Models (5/23/00)
Small-Signal Frequency Dependent Model
Cgd
G
Cgb
+
vgs
S
-
id
Cgs
gmvgs
gmbsvbs
vbs
rds
+
vds
-
S
D
Cbd
Cbs
+
B
Fig1.8-15
The depletion capacitors are found by evaluating the large signal capacitors at the DC operating point.
The charge storage capacitors are constant for a specific region of operation.
Gainbandwidth of the MOSFET:
Assume VSB = 0 and the MOSFET is in saturation,
gm
1
1 gm
f T = 2π C + C ≈ 2π C
gs
gd
gs
Recalling that
2
and
Cgs ≈ 3 C ox WL
gives
3 µo
fT = 4π 2 (V GS -V T )
L
gm = µoCox
ECE 4430 - Analog Integrated Circuits and Systems
W
(V GS -V T )
L
© Phillip E. Allen 2000
Page 29
MOS Models (5/23/00)
Summary of the MOSFET Large Signal Model
D
CGD
rD
CBD
vBD
+ -
G
rG
iBD
vBS
+ -
iD
rB
B
iBS
CBS
CGS
CGB
rS
where,
rG, rS, rB, and rD are

 vBD
iBD = Is exp
 
 Vt 
ohmic and contact resistances


 vBS

1 and iBS = Is exp V  - 1


 t

S
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 30
MOS Models (5/23/00)
Electron Drift Velocity (m/s)
SHORT-CHANNEL MOSFET MODEL
Velocity Saturation
The most important short-channel effect in MOSFETs is the velocity saturation of carriers in the
channel. A plot of electron drift velocity versus electric field is shown below.
105
5x104
2x104
104
5x103
105
106
Electric Field (V/m)
107
Fig1.8-11
An expression for the electron drift velocity as a function of the electric field is,
µ nE
v d ≈ 1 + E/E
c
where
vd = electron drift velocity (m/s)
µn = low-field mobility (≈ 0.07m2/V·s)
Ec = critical electrical field at which velocity saturation occurs
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 31
MOS Models (5/23/00)
Short-Channel Model Derivation
As before,
iD
WQ I(y)µ nE
JD = JS = W = Q I(y)vd(y) → iD = W QI(y)vd(y) =
1 + E/E c
→
E 

iD 1 + E = WQ I(y)µnE

C
Replacing E by dv/dy gives,
1 d v
dv

iD 1 + E dy= WQ I(y)µn
dy


C
Integrating along the channel gives,
L
vD S
1 d v
⌠ 
⌠
iD 1 +
Ec dydy = ⌡WQ I(y)µ ndv
⌡ 
0
0
The result of this integration is,
µnCox
W
K’
W
2] =
[2(v
V
)v
v
[2(vGS - V T )vDS - vDS 2]
iD =
GS
T
DS
DS
L
2[1
+
θ
(v
-V
)]
L
v

GS T
1 D S
2 1 + E L 
c


where θ = 1/LEc with dimensions of V-1.
The saturation voltage has not changed so substituting for vDS by vGS-VT gives,
K’
W
iD = 2[1 + θ (v -V )] L [ vGS - V T ]2
GS T
Note that the transistor will enter the saturation region for vDS < vGS - VT in the presence of velocity
saturation.
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 32
MOS Models (5/23/00)
The Influence of Velocity Saturation on the Transconductance Characteristics
The following plot was made for K’ = 110µA/V2 and W/L = 1:
1000
θ=0
θ = 0.2
iD/W (µA/µm)
800
θ = 0.4
600
θ = 0.6
400
θ = 1.0
200
0
0.5
1
1.5
2
vGS (V)
θ = 0.8
2.5
3
Fig1.8-12
Note as the velocity saturation effect becomes stronger, that the drain current-gate voltage relationship
becomes linear.
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 33
MOS Models (5/23/00)
Circuit Model for Velocity Saturation
A simple circuit model to include the influence of velocity saturation is the
following:
D
G
iD
+
+
vGS' RSX
vGS
We know that
K’W
iD = 2L (v GS ’ -V T )2 and v GS = v GS ’ + iD RSX
Substituting vGS’ into the current relationship gives,
Fig1.8-13
or
- S
v GS ’ = v GS - iD R XS
K’W
iD = 2L (v GS - iD R SX -V T )2
Solving for iD results in,
iD =
K’
W
(v GS - V T )2
 L
W

21 + K ’
L R SX (v GS -V T ) 

Comparing with the previous result, we see that
W
1
θL
θ = K’ L R SX
→
R SX =
= E K’W
K’W
c
Therefore for K’ = 110µA/V2, W = 1µm and Ec = 1.5x106V/m, we get RXS = 6.06kΩ.
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 34
MOS Models (5/23/00)
Output Characteristics of Short-Channel MOSFETs†
IBM, 1998, tox = 3.5nm
800
Drain Current (µA/µm)
700
600
NFET VGS=1.8V
Leff =
0.08µm
PFET
Leff =
0.11µm
VGS=1.4V
500
400
300
200
100
VGS=-1.8V
VGS=1.0V
VGS=-1.4V
VGS=-1.0V
VGS=0.6V
VGS=-0.6V
0
-1.8
-1.2
-0.6
0.6
0.0
Drain Voltage (V)
1.2
1.8
Fig1.8-14
†
Su, L., et.al., “A High Performance Sub-0.25µm CMOS Technology with Multiple Thresholds and Copper Interconnects,” 1998 Symposium on VLSI
Technology Digest of Technical Papers, pp. 18-19.
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 35
MOS Models (5/23/00)
SUBTHRESHOLD MOSFET MODEL
Weak inversion operation occurs when the applied gate voltage is below V T and pertains to when the
surface of the substrate beneath the gate is weakly inverted.
,,,
zz
,,
y
y
VGS
n+
n-channel
n+
Diffusion Current
p-substrate/well
Regions of operation according to the surface potential, φS.
φS < φF :
Substrate not inverted
φ F < φ S < 2φ F : Channel is weakly inverted (diffusion current)
2φF < φS :
Strong inversion (drift current)
Drift current versus diffusion current in a MOSFET:
log iD
Diffusion Current
Drift Current
10-6
10-12
0
ECE 4430 - Analog Integrated Circuits and Systems
VT
VGS
© Phillip E. Allen 2000
Page 36
MOS Models (5/23/00)
Large-Signal Model for Subthreshold
Model:
W
iD = K x L evGS/nVt(1 - e-vDS/Vt)(1 + λvDS)
where
Kx is dependent on process parameters and the bulk-source voltage
n ≈ 1.5 - 3
and
iD
kT
Vt = q
If vDS > 0, then
1µA
W
iD = K x L evGS/nVt (1 + λvDS)
Small-signal model:
VGS<VT
0
∂iD
qID
gm = ∂ v Q| = nkT
GS
∂iD
gds = ∂v Q|
DS
VGS=VT
0
1V
vDS
Fig1.8-18
ID
VA
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 37
MOS Models (5/23/00)
SUBSTRATE CURRENT FLOW IN MOSFETS
Impact Ionization
Impact Ionization:
Occurs because high electric fields cause an impact which generates a hole-electron pair. The electrons
flow out the drain and the holes flow into the substrate causing a substrate current flow.
Illustration:
,,,
,,,,,,,,
VG > VT
VD > VDS(sat)
S
B
Polysilicon
p+
Depletion
Region
,,,,,,,,
,,,,,,,,
A
n+
Fixed
Atom
p- substrate
Free n+
electron
Free
hole
Fig1.8-16
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 38
MOS Models (5/23/00)
Model of Substrate Current Flow
Substrate current:
iDB = K1(vDS - vDS(sat))iDe-[K2/(vDS-vDS(sat))]
where
K1 and K2 are process-dependent parameters (typical values are K1 = 5V-1 and K2 = 30V)
Schematic model:
D
iDB
G
B
S
Fig1.8-17
Small-signal model:
IDB
∂iDB
gdb = ∂v = K 2 V
DB
DS - V DS (sat)
This conductance will have a negative influence on high-output resistance current sinks/sources.
ECE 4430 - Analog Integrated Circuits and Systems
© Phillip E. Allen 2000
Page 39
MOS Models (5/23/00)
SUMMARY
Simple Large-Signal Model
Non-saturationWµoCox 
vDS2
 (v
- V T )v D S - 2  (1 + λ vDS )
iD =
L
 GS

SaturationWµ oC ox
2
iD =
2L (v GS - V T ) (1 + λ v DS )
Small-Signal Model
diD
diD
λiD
|
|
= β (V GS -V T ) = 2 β ID g ds ≡ dv
=
≈ λ iD
gm ≡ dv
GS Q
DS Q 1 + λ v D S
g mbs =
gmγ
2 2| φ F | - V B S
Capacitances
Capacitance
C4 Large
C2 + 2C5
CGS
C1+ 0.67C2
C1+ 0.5C2
C1, C3
2C5
0
CGS, CGD
vDS = constant
vBS = 0
C4 Small
CGS, CGD
CGD
CGB
Off
Saturation
VT
NonSaturation
vDS +VT
ECE 4430 - Analog Integrated Circuits and Systems
vGS
Fig1.8-10
© Phillip E. Allen 2000