EE247
Lecture 15
D/A Converters
• D/A architecture examples
– Unit element
– Binary weighted
•
Static performance
– Component matching
– Architectures
• Unit element
• Binary weighted
• Segmented
– Dynamic element matching
•
Dynamic performance
•
DAC Examples
– Glitches
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 1
R-String DAC
•
Advantages:
– Simple, fast for <8-10bits
– Inherently monotonic
– Compatible with purely digital
technologies
•
Disadvantages:
– 2B resistors & 2B switches for B
bits à High element count &
larger area for B>10bits
– High settling time for B > 10:
τmax = 0.25 x 2B RC
C
*Ref: M. Pelgrom, “A 10-b 50-MHz CMOS D/A
Converter with 75-W Buffer,” JSSC, Dec. 1990,
pp. 1347.
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 2
R-String DAC
Including Interpolation
Resistor string DAC
Resistor string interpolator increases
resolution w/o drastic increase in
complexity
e.g. 6bit DACà 3+3
Vout
Considerations:
Interpolation string loading of main R
string
Large R values à less loading but
lower speed
Can use buffers
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 3
R-String DAC
Including Interpolation
Use buffers
à Issues: offset & speed
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 4
Static DAC INL / DNL Errors
• Component matching
• Systematic errors
–
–
–
–
Contact resistance
Edge effects in capacitor arrays
Process gradient
Finite current source output resistance
• Random errors
– Lithography
– Often Gaussian distribution (central limit theorem)
*Ref: C. Conroy et al, “Statistical Design Techniques for D/A Converters,” JSSC Aug. 1989,
pp. 1118-28.
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 5
Probability density p(x)
Gaussian Distribution
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
( x−µ )
2
p( x ) =
1
2πσ
−
e
2σ
-3
-2
-1
0
1
2
3
x /σ
2
where standard d e v i a t i o n : σ = E( X 2 ) − µ 2
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 6
P (− X ≤ x ≤ + X ) =
=
1
+X −
2π
−X
∫
e
x2
2 dx
Probability density
p(x)
Yield
P(-X ≤ x ≤ +X)
 X 
= erf 

 2
0.4
0.3
0.2
0.1
0
1
0.8
0.6
0.4
0.2
0
95.4
68.3
38.3
0
0.5
1
1.5
2
2.5
3
X
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 7
Yield
X/σ
0.2000
0.4000
0.6000
0.8000
1.0000
1.2000
1.4000
1.6000
1.8000
2.0000
P(-X ≤ x ≤ X) [%]
15.8519
31.0843
45.1494
57.6289
68.2689
76.9861
83.8487
89.0401
92.8139
95.4500
EECS 247 Lecture 15: Data Converters
X/σ
2.2000
2.4000
2.6000
2.8000
3.0000
3.2000
3.4000
3.6000
3.8000
4.0000
P(-X ≤ x ≤ X) [%]
97.2193
98.3605
99.0678
99.4890
99.7300
99.8626
99.9326
99.9682
99.9855
99.9937
© 2004 H.K. Page 8
Example
• Measurements show that the offset voltage of
a batch of operational amplifiers follows a
Gaussian distribution with σ = 2mV and µ = 0.
• Fraction of opamps with |Vos| < X = 6mV:
– X/σ = 3 à 99.73 % yield (we’d still test before
shipping!)
• Fraction of opamps with |Vos| < X = 400µV:
– X/σ = 0.2 à 15.85 % yield
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 9
Component Mismatch
Example: Two side-by-side
Resistors
No. of resistors
400
300
∆R
200
R
100
Large # of devices
measured
0
996 1000 1004 1008 1012
& curved à typically if
988 992
sample size large shape
R[ Ω ]
is Gaussian
E.g. Let us assume in this example 1000 Rs measured
& 68.5% within +-4OHM or +-0.4% of average
à 1σ for resistorsà 0.4%
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 10
Probability density p(x)
Component Mismatch
Two side-by-side
Resistors
R=
R1 + R2
2
0.4
0.35
0.3
0.25
∆R
0.2
R
0.15
0.1
0.05
0
−3σ −2σ
dR = R1 − R2
σ d2R ∝
R
−σ
0
σ
2σ
For typical technologies & geometries
1σ for resistorsà 0.02 το 5%
1
Area
3σ
dR
R
In the case of resistors σ is a function of area
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 11
DNL Unit Element DAC
E.g. Resistor string DAC:
∆ = Rnom I ref
Iref
∆i = Ri I ref
DNLi =
=
∆nom − ∆
∆
Ri − R
nom
Rnom
=
d Rn o m
Rn o m
≈
dRnom
Ri
∆i = Ri I ref
σ DNL = σ dRi
Ri
DNL of unit element DAC is
independent of resolution!
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 12
DNL Unit Element DAC
E.g. Resistor string DAC:
Example:
If σdR/R = 0.4%, what DNL spec
goes into the datasheet so that
99.9% of all converters meet
the spec?
σ DNL = σ d R
i
Ri
Answer:
From table: for 99.9%
à X/σ = 3.3
σDNL = σdR/R = 0.4%
3.3 σDNL = 1.3%
DNL of unit element DAC is
independent of resolution!
àDNL= +/- 0.013 LSB
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 13
DAC INL Analysis
A
Ideal
n
B
N-n
Output/[Lsb]
N
B
A
n
(N-n)σε2
E = A-n r =n/N
= A-r(A+B)
= A (1-r) -B.r
à Variance of E:
σE2 =(1-r)2 .σΑ2 + r 2 .σB2
E
n
Variance
nσε2
N=2B-1
Input/[Lsb]
=N.r .(1-r).σε2
àMaximum @ r =0.5, n=N/2
àMax INL @ midscale
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 14
DAC INL
n

σ E 2 = n  1 −  ×σ ε 2
 N
To find m a x . v a r i a n c e :
→ n=N/2
•
dσ E 2
dn
=0
Error is maximum at mid-scale (N/2):
σ INL =
1
2B − 1 σ ε
2
with N = 2 B − 1
•
INL depends on DAC resolution and element matching σε
•
While σDNL = σε
Ref: Kuboki et al, TCAS, 6/1982
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 15
Untrimmed DAC INL
Example:
σ INL ≅
1 B
2 −1 σε
2
σ 
B ≅ 2 + 2 log2  INL 
 σε 
EECS 247 Lecture 15: Data Converters
σINL = 0.1 LSB
σε
σε
σε
σε
= 1%
= 0.5%
= 0.2%
= 0.1%
B = 8.6
B = 10.6
B = 13.3
B = 15.3
© 2004 H.K. Page 16
Simulation Example
DNL and INL of 12 Bit converter (from converter decision thresholds)
DNL [in LSB]
2
1
-0.04 / +0.03 LSB, avg=6.7e-005, std.dev=0.01, range=0.069
σε
B
= 1%
= 12
0
-1
500
1000
1500
2000
bin
2500
3000
3500
4000
σINL = 0.3 LSB
(midscale)
INL [in LSB]
2
1
-0.2 / +0.8 LSB, avg=0.22, std.dev=0.21, range=0.99
0
-1
500
1000
1500
2000
bin
2500
3000
3500
4000
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 17
Binary Weighted DAC
•
INL same as for unit element
DAC
•
DNL depends on transition
Iout
– Example:
0 to 1 àσDNL2 = σ(dΙ/Ι) 2
1 to 2 à σDNL2 = 3σ(dΙ/Ι) 2
•
Consider MSB transition:
0111 … à 1000 …
EECS 247 Lecture 15: Data Converters
2B-1 Iref
……………
4 Iref
2Iref
Iref
© 2004 H.K. Page 18
MOS Device Matching
Id =
dId
Id
dI d
Id
=
I d1 + Id 2
2
Id1
I d1 − Id 2
Id2
Id
 d W L   dVth 
= 
+

W
 L   VGS −Vth 
•Current matching depends on:
-Device ratio matching
à larger area less mismatch effect
-Threshold voltage matching
à Larger gate-overdrive less threshold voltage mismatch effect
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 19
Current-Switched DACs in CMOS
Iout
Iref
dId
Id
Switch Array
 d W L   dVth 
= 
+

W
 L   VGS −Vth 
……
256
•Advantages:
Can be very fast
Small area for <9-10bits
128
64 ………..…..1
Example: 8bit Binary Weighted
•Disadvantages:
Matching depends on Vth matching & device W/L matching
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 20
DNL of Binary Weighted DAC
•
Worst-case transition occurs at
mid-scale:
15
(
)
(
)
σDNL2/ σε2
2
σ DNL
= 2B−1 − 1 σε2 + 2B−1 σε2
10
144244
3
14243
0111...
1000...
≅ 2Bσε2
σ DNLmax = 2B / 2σε
5
σ I N Lmax ≅
•
0
2
4
6
8
10
12
14
1
2
2B − 1 σ ε ≅
1
2
σ DNLmax
Example:
B = 12, σε = 1%
à σDNL = 0.64 LSB
à σINL = 0.32 LSB
DAC input code
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 21
Simulation Example
DNL and INL of 12 Bit converter (from converter decision thresholds)
DNL [in LSB]
2
1
-0.9 / +0.4 LSB, avg=-7.5e-005, std.dev=0.039, range=1.3
σε
B
= 1%
= 12
0
-1
500
1000
1500
2000
bin
2500
3000
3500
4000
σDNL = 0.6 LSB
(midscale)
INL [in LSB]
2
1
-0.7 / +0.7 LSB, avg=3.3e-014, std.dev=0.33, range=1.3
0
-1
500
1000
1500
2000
bin
2500
EECS 247 Lecture 15: Data Converters
3000
3500
4000
MSB transitions
clearly visible
© 2004 H.K. Page 22
“Another” Random Run …
DNL and INL of 12 Bit converter (from converter decision thresholds)
DNL [in LSB]
2
1
-1 / +0.1 LSB, avg=-9.3e-005, std.dev=0.035, range=1.4
Now (by chance) worst
DNL is mid-scale.
0
-1
-2
500
1000
1500
2000
bin
2500
3000
3500
4000
Statistical result!
INL [in LSB]
2
1
-0.8 / +0.8 LSB, avg=-1.1e-013, std.dev=0.37, range=1.6
0
-1
500
1000
1500
2000
bin
2500
3000
3500
4000
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 23
Unit Element vs Binary Weighted
Unit Element DAC
σ DNL = σ ε
σ INL ≅ 2
B
Binary Weighted DAC
σ DNL ≅ 2 2 σ ε = 2σ INL
B
2 −1
σε
σ INL ≅ 2
B
2 −1
σε
Number of switched elements:
S = 2B
S=B
Significant difference in performance and complexity!
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 24
Unit Element vs Binary Weighted
Example: B=10
Unit Element DAC
Binary Weighted DAC
σ DNL = σ ε
B
σ INL ≅ 2 2 −1σ ε = 1 6σ ε
σ DNL ≅ 2 2σ ε = 32σ ε
B
σ INL ≅ 2 2 −1σ ε = 1 6σ ε
B
Number of switched elements:
S = 2 = 1024
B
S = B = 10
Significant difference in performance and complexity!
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 25
DAC INL/DNL Summary
•
DAC architecture has significant impact on DNL
•
INL is independent of DAC architecture and requires element
matching commensurate with overall DAC precision
•
Results are for uncorrelated random element variations
•
Systematic errors and correlations are usually also important
Ref: Kuboki, S.; Kato, K.; Miyakawa, N.; Matsubara, K. Nonlinearity analysis of
resistor string A/D converters. IEEE Transactions on Circuits and Systems,
vol.CAS-29, (no.6), June 1982. p.383-9.
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 26
Segmented DAC
•
Objective:
compromise between unit element and binary weighted DAC
(B2)LSB
MSB (B1 bits)
…
…
Unit Element Binary Weighted
•
Approach:
B1 MSB bits à unit elements
B2 = B-B1 LSB bits à binary weighted
•
•
INL: unaffected
DNL: worst case occurs when LSB DAC turns off and one more MSB
DAC element turns on: same as binary weighted DAC with B2+1 bits
Number of switched elements: (2B1-1) + B2
•
VAnalog
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 27
Comparison
Example:
B = 12, B1 = 5,
B1 = 6,
B2 = 7
B2 = 6
MSB
Unit element (10+0)
Binary weighted(0+10)
Segmented 5+7
Segmented 6+6
EECS 247 Lecture 15: Data Converters
σ INL ≅ 2
LSB
B
2
2
σ ε = 2σ INL
−1
σε
S = 2B1 − 1 + B2
σε = 1%
DAC Architecture
( B2 +1)
σ DNL ≅ 2
σINL[LSB]
σDNL[LSB]
# s.e.
0.32
0.32
0.32
0.32
0.01
0.64
0.16
0.113
4095
12
31+7
63+6
© 2004 H.K. Page 28
Dynamic DAC Error: Glitch
•
ideal
10
DAC output depends on
timing
5
0
1
1.5
2
2.5
3
1
1.5
2
2.5
3
1
1.5
2
Time
2.5
3
10
Plot shows situation where
– LSB/MSBs on time
– LSB early, MSB late
– LSB late, MSB early
early
•
Consider binary weighted
DAC transition 011 à 100
5
0
10
late
•
5
0
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 29
Glitch Energy
~dt x 2B-1
~T
•
•
Glitch energy (worst case):
LSB energy:
•
Need dt x 2B-1 << T or dt << 2-B+1 T
•
Examples:
fs [MHz]
B
dt [ps]
1
20
1000
12
16
10
<< 488
<< 1.5
<< 2
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 30
DAC Reconstruction Filter
B
fs/2
1
DAC Input
• Need for and
requirements depend
on application
0.5
0
0
0.5
1
1.5
2
2.5
sinc
1
– Correct for sinc distortion
– Remove “aliases”
(stair-case
approximation)
0.5
0
0
0.5
1
1.5
2
2.5
3
6
1
DAC Output
• Tasks:
3
6
x 10
x 10
0.5
0
0
0.5
1
1.5
Frequency
EECS 247 Lecture 15: Data Converters
2
2.5
3
6
x 10
© 2004 H.K. Page 31
Reconstruction Filter Options
D igital
F ilter
DAC
SC
Filter
ZOH
CT
F ilter
• Digital and SC filter possible only in combination with
oversampling (signal bandwidth B << fs/2)
• Digital filter can prewarp spectrum to compensate inband sinc attenuation (from ZOH)
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 32
Sample DAC Implementations
•
Untrimmed segmented
– T. Miki et al, “An 80-MHz 8-bit CMOS D/A Converter,” JSSC
December 1986, pp. 983.
– A. Van den Bosch et al, “A 1-GSample/s Nyquist Current-Steering
CMOS D/A Converter,” JSSC March 2001, pp. 315.
•
Current copiers:
– D. W. J. Groeneveld et al, “A Self-Calibration Techique for
Monolithic High-Resolution D/A Converters,” JSSC December
1989, pp. 1517.
•
Dynamic element matching:
– R. J. van de Plassche, “Dynamic Element Matching for HighAccuracy Monolithic D/A Converters,” JSSC December 1976, pp.
795.
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 33
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 34
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 35
Current-Switched DACs in CMOS
I1 = k (VGSM 1 − Vt h )
VGSM 2 = VGSM 1 − 3RI
VGSM 3 = VGSM 1 − 5RI
VGSM 4 = VGSM 1 − 6 R I
2
Iout
VDD
2
3RI 

2
I 2 = k (VGSM 2 −Vt h ) = I1  1 −

V
GSM 1 − Vt h 

2I1
gmM 1 =
VGSM 1 −Vt h
M1
I1
M2
I2
I3 M
4
M3
I4
2
 3RgmM 1 
→ I 2 = I1  1 −
 ≈ I1 (1 − 3RgmM 1 )

2 
2
 3RgmM 1 
→ I3 = I1  1 −
 ≈ I1 (1 − 5RgmM 1 )

2 
2
 3RgmM 1 
→ I 4 = I1  1 −
 ≈ I1 (1 − 6RgmM 1 )

2 
3RI
RI
2RI
Example: 4 unit element current sources
•Assumption: RI is small compared to transistor gate overdrive
à Desirable to have gm small
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 36
Current-Switched DACs in CMOS
Iout
VDD
I/2
I/2
I
M1
I1
M2
I2
M3
2RI
I3 M
4
I4
RI
Example: 4 unit element current sources
•Assumption: RI is small compared to xtor gate overdrive
à Desirable to have gm small
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 37
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 38
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 39
I/2
Current
Divider
EECS 247 Lecture 15: Data Converters
I/2
I
© 2004 H.K. Page 40
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 41
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 42
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 43
Dynamic Element Matching
During Φ2
During Φ1
I1(1) = 12 I o (1 + ∆1 )
I
(1)
2
I1( 2 ) = 12 I o (1 − ∆1 )
= I o (1 − ∆1 )
Io/2
I 2( 2 ) = 12 I o (1 + ∆1 )
1
2
Io/2
I1
I2
fclk
I 2(1) + I 2( 2 )
2
I (1 − ∆1 ) + (1 + ∆1 )
= o
2
2
I
= o
2
I2 =
EECS 247 Lecture 15: Data Converters
/ 2 error ∆1
Io
© 2004 H.K. Page 44
Dynamic Element Matching
During Φ2
During Φ1
I1(1) = 12 I o (1 + ∆1 )
I
(1)
2
I1( 2 ) = 12 I o (1 − ∆1 )
= I o (1 − ∆1 )
1
2
I 3(1) = 12 I1(1) (1 + ∆ 2 )
I
= I o (1 + ∆1 )(1 + ∆ 2 )
( 2)
2
= I o (1 + ∆1 )
1
2
I 3( 2 ) = 12 I1( 2 ) (1 − ∆ 2 )
1
4
= 14 I o (1 − ∆1 )(1 − ∆ 2 )
I (1) + I 3( 2 )
I3 = 3
2
I o (1 + ∆1 )(1 + ∆ 2 ) + (1 − ∆1 )(1 − ∆ 2 )
=
2
4
I
= o (1 + ∆1∆ 2 )
4
Io/4
Io/2
Io/4
I3
I4
I2
fclk
/ 2 error ∆2
I1
fclk
E.g. ∆1 = ∆2 = 1% à matching error is (1%)2 = 0.01%
EECS 247 Lecture 15: Data Converters
/ 2 error ∆1
Io
© 2004 H.K. Page 45
MOS Sampling Circuits
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 46
Re-Cap
Analog Input
Anti-Aliasing
Filter
Analog
Preprocessing
• How can we
build circuits
that "sample"
Sampling
+Quantization
A/D
Conversion
000
...001...
110
DSP
D/A
Conversion
"Bits to
Staircase"
Analog
Post processing
Reconstruction
Filter
Analog Output
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 47
Ideal Sampling
φ1
• In an ideal world,
zero resistance
sampling switches
would close for the
briefest instant to
sample a continuous
voltage vIN onto the
capacitor C
• Not realizable!
EECS 247 Lecture 15: Data Converters
vIN
vOUT
S1
C
φ1
T=1/fS
© 2004 H.K. Page 48
Ideal T/H Sampling
φ1
vIN
vOUT
S1
C
φ1
T=1/fS
• Vout tracks input when switch is closed
• Grab exact value of Vin when switch opens
• "Track and Hold" (T/H)
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 49
Ideal T/H Sampling
Continuous
Time
time
T/H signal
(SD Signal)
Clock
DT Signal
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 50
Practical Sampling
φ1
vIN
vOUT
M1
C
•
•
•
•
•
kT/C noise
Finite Rsw à limited bandwidth
Rsw = f(Vin) à distortion
Switch charge injection (EE240)
Clock jitter
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 51
kT/C Noise
k BT ∆2
≤
12
C
 2B − 1 

C ≥ 12k BT 
 VFS 
2
In high resolution ADCs kT/C noise usually dominates
overall error (power dissipation considerations).
B
Cmin (VFS = 1V)
8
12
14
16
20
0.003 pF
0.8 pF
13 pF
206 pF
52,800 pF
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 52
Acquisition Bandwidth
• The resistance R of
switch S1 turns the
sampling network into a
lowpass filter with
risetime = RC = τ
φ1
vIN
vOUT
R S1
C
• Assuming Vin is
constant during the
sampling period and C
is initially discharged
vout (t ) = vin (1 − e − t /τ )
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 53
Switch On-Resistance

1 
Vin − Vout  t =
 << ∆
2
fs 

−1
Vin e
2 f sτ
<< ∆
Vin = VFS
Worst Case:
τ << −
R << −
φ1
vIN
C
T
1
2 ln 2 B − 1
(
)
1
1
2 f sC ln 2 B − 1
Example:
B = 14,
(
vOUT
R S1
)
C = 13pF, fs = 100MHz
φ1
T=1/fS
T/τ >> 19.4, R << 40Ω
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 54
Switch On-Resistance
I D ( triode ) = µCox
RON =
µCox
for
RON =
W
L
VDS

 VGS − VTH −
2


VDS ,

dI D ( triode )
1
≅
RON
dVDS
VDS →0
1
1
=
W
W
(VGS − Vth ) µCox (VDD − Vth − Vin )
L
L
Ro =
1
W
µCox (VDD − Vth )
L
Ro
Vin
1−
VDD − Vth
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 55
Sampling Distortion
vout =
T
Vin  

−  1−


2τ  VDD −Vt h  
vi n  1 − e





10bit ADC & T/τ = 10
VDD – Vth = 2V
VFS = 1V
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 56
Sampling Distortion
• SFDR is very sensitive to
sampling distortion
• Solutions:
• Overdesignà Larger
switches
à increased switch
charge injection
• Complementary switch
• Maximize VDD/VFS
à decreased dynamic
range
• Constant VGS ? f(Vin)
à …
10bit ADC T/τ = 20
VDD – Vth = 2V
VFS = 1V
EECS 247 Lecture 15: Data Converters
© 2004 H.K. Page 57