Department of Electrical and Computer Engineering
DAC Architectures
Vishal Saxena, Boise State University
(vishalsaxena@boisestate.edu)
Vishal Saxena
-1-
Static Performance
of DACs
–2–
Vishal Saxena
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DAC Transfer Characteristics
ref
n
out
• N = # of bits
1
Digital input
Analog output
• VFS = Full-scale range
• Δ = VFS/2N = 1LSB
• bi = 0 or 1
Vout
N-1
N-1
bi
= VFS   N-i = Δ   bi  2i-N
i=0 2
i=0
Note: Vout (bi = 1, for all i) = VFS - Δ = VFS(1-2-N) ≠ VFS
–3–
Vishal Saxena
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Ideal DAC Transfer Curve
out
FS
FS
000
001
010
011
100
–4–
101
Vishal Saxena
110
111
in
-4-
Offset
out
FS
FS
Vos
000
001
010
011
100
–5–
101
Vishal Saxena
110
111
in
-5-
Gain Error
out
FS
FS
000
001
010
011
100
–6–
101
Vishal Saxena
110
111
in
-6-
Monotonicity
out
FS
FS
000
001
010
011
100
–7–
101
Vishal Saxena
110
111
in
-7-
Differential and Integral Nonlinearities
out
FS
ith Step Size - Δ
DNLi =
Δ
FS
000
001
010
011
100
101
110
111
in
•
DNL = deviation of an output step from 1 LSB (= Δ = VFS/2N)
•
INL = deviation of the output from the ideal transfer curve
–8–
Vishal Saxena
-8-
DNL and INL
out
FS
i
INLi =  DNL j
FS
j=0
000
001
010
011
100
101
110
111
in
INL = cumulative sum of DNL
–9–
Vishal Saxena
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DNL and INL
Vout
Vout
VFS-Δ
VFS-Δ
VFS
2
VFS
2
000
001
010
011
100
101
110
111
Din
000
Smooth
001
010
011
100
101
110
111
Noisy
•
DNL measures the uniformity of quantization steps, or incremental (local)
nonlinearity; small input signals are sensitive to DNL.
•
INL measures the overall, or cumulative (global) nonlinearity; large input
signals are often sensitive to both INL (HD) and DNL (QE).
– 10 –
Vishal Saxena
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Din
Measure DNL and INL (Method I)
out
FS
FS
Endpoint
stretch
000
001
010
011
100
101
110
111
in
Endpoints of the transfer characteristic are always at 0 and VFS-Δ
– 11 –
Vishal Saxena
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Measure DNL and INL (Method II)
out
FS
FS
Least-square
fit and stretch
(“detrend”)
000
001
010
011
100
101
110
111
in
Endpoints of the transfer characteristic may not be at 0 and VFS-Δ
– 12 –
Vishal Saxena
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Measure DNL and INL
Vout
Vout
VFS-Δ
VFS-Δ
VFS
2
VFS
2
000
001
010
011
100
101
110
111
Din
000
001
010
011
100
101
110
111
Method I (endpoint stretch)
Method II (LS fit & stretch)
Σ(INL) ≠ 0
Σ(INL) = 0
– 13 –
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Din
DAC Architectures
– 14 –
Vishal Saxena
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DAC Architecture
•
Nyquist DAC architectures
–
–
–
–
•
Binary-weighted DAC
Unit-element (or thermometer-coded) DAC
Segmented DAC
Resistor-string, current-steering, charge-redistribution DACs
Oversampling DAC
–
–
–
–
Oversampling performed in digital domain (zero stuffing)
Digital noise shaping (ΣΔ modulator)
1-bit DAC can be used
Analog reconstruction/smoothing filter
– 15 –
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Binary-Weighted DAC
– 16 –
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Binary-Weighted CR DAC
CP
Cu = unit capacitance
Vo
VX
8Cu
4Cu
2Cu
Cu
Cu
VR
b3
b2
b1
b0
•
Binary-weighted capacitor array → most efficient architecture
•
Bottom plate @ VR with bj = 1 and @ GND with bj = 0
– 17 –
Vishal Saxena
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Binary-Weighted CR DAC
N


  bN j  2N j Cu 
j1
V
Vo  
N
 R
N j
 Cp  Cu   2 Cu 
j1


N b
 2N Cu 
  VR   N- j
Vo  
j
 C  2N C 
2

j
1
p
u


 N

  bN j  2N j Cu 
j1
V
 
R
Cp  2N Cu 




•
Cp → gain error (nonlinearity if Cp is nonlinear)
•
INL and DNL limited by capacitor array mismatch
– 18 –
Vishal Saxena
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Stray-Insensitive CR DAC


2N Cu

Vo 
 N
Cp  2N1Cu  Cu
 2 Cu 
A



N
  V  bN- j
j
 R 
j1 2


Large A needed
to attenuate
summing-node
charge sharing
– 19 –
Vishal Saxena
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MSB Transition
Code 0111
Code 1000






C
C
C
V
1
2
3
Vo 0111  
4
 R
4 j
 Cp  C   2 C 
j1






C
V
4
Vo 1000   
4
 R
4 j
 Cp  C   2 C 
j1


Assume : C 4  C1  C2  C3   Cu  δC,
DNL  Vo 1000   Vo 0111  1LSB  1LSB

δC
C
Cu
 δC Cu
C

Largest DNL error occurs at the midpoint where MSB transitions, determined
by the mismatch between the MSB capacitor and the rest of the array.
– 20 –
Vishal Saxena
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Midpoint DNL
δC < 0
δC > 0
•
δC > 0 results in positive DNL
•
δC < 0 results in negative DNL or even nonmonotonicity
– 21 –
Vishal Saxena
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Output Glitches
• Cause: Signal
and clock skew
in circuits
• Especially
severe at MSB
transition where
all bits are
switching –
0111…111 →
1000…000
•
Glitches cause waveform distortion, spurs and elevated noise floors
•
High-speed DAC output is often followed by a de-glitching SHA
– 22 –
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De-Glitching SHA
1
o
N
SHA samples the output
of the DAC after it settles
and then hold it for T,
removing the glitching
energy.
SHA output must be smooth (exponential settling can be viewed as pulse
shaping → SHA BW does not have to be excessively large).
– 23 –
Vishal Saxena
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Frequency Response
HZOH  jω   e
j
ωT
2


sin ωT
ωT
2

HSHA  jω  
2
– 24 –
Vishal Saxena
1
1 j ω
ω 3dB
-24-
Binary-Weighted Current-Steering DAC
N
Vo  IR  
j1
bN- j
2j
•
Current switching is simple and fast
•
Vo depends on Rout of current sources without op-amp
•
INL and DNL depend on matching, not inherently monotonic
•
Large component spread (2N-1:1)
– 25 –
Vishal Saxena
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R-2R DAC
N
Vo  IR  
j1
bN- j
2j
X
o
3
2
1
0
•
A binary-weighted current DAC
•
Component spread greatly reduced (2:1)
– 26 –
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Unit-Element DAC
– 27 –
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Resistor-String DAC
•
Simple, inherently monotonic → good DNL performance
•
Complexity ↑ speed ↓ for large N, typically N ≤ 8 bits
– 28 –
Vishal Saxena
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Code-Dependent Ro
VR
Di
b0 b0
b1 b1
Vo
Co
Signal-dependent
RoCo causes HD
Ro
•
Ro of ladder varies with signal (code)
•
On-resistance of switches depend on tap voltage
– 29 –
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DNL
ΔR  0, σ R 
j1
Vj 
R
j1
k
1
N
R
1
k
 VR 
 j  1R   ΔRk
1
N
NR   ΔR k
j 2
 VR
Vj-1 
1
Vj  Vj-1 
 j  2R   ΔRk
1
N
NR   ΔRk
 VR
1
R  ΔR j1
N
NR   ΔRk
VR ΔR j1
 VR 

 VR
N
NR
1
V 

DNL j   Vj  Vj-1  R 
N 

VR ΔR j1

N
R
– 30 –
Vishal Saxena
 DNL  0, σDNL 
σR
R
-30-
INL
j1
Vj 
R
k
1
N
R
1
j1
j1
k
 VR 
 j  1 R   ΔRk
1
N
NR   ΔRk
 VR 
j 1
VR 
N
N
N - j  1 ΔRk   j  1 ΔRk
1
j
2
NR
VR
1
j  1 N - j  1 σR 2 2

j 1
2
VR , σ Vj 
VR
 Vj 
3
2
N
N
R
1 σR 2 2
N
N
2
V
,
when
j
1
 σ Vj  max  



R
4N R2
2
2
j -1 

INL j   Vj 
VR 
N


VR
N
 INL  0, σINL  max  
– 31 –
Vishal Saxena
N  σR 


2 R 
-31-
INL and DNL of Binary-Wtd DAC
A Binary Weighted DAC is typically constructed using unit elements, the
same way as that of a Unit Element DAC, for good component matching
accuracy.
INL  0, σINL  max  

N  σR 


2 R 
σ 
DNL  0, σDNL  max   2  INL  N  R 
R 
– 32 –
Vishal Saxena
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Current-Steering DAC
Io
I
I
I
Binary-to-Thermometer Decoder
b1
bN
•
Fast, inherently monotonic → good DNL performance
•
Complexity increases for large N, requires B2T decoder
– 33 –
Vishal Saxena
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Unit Current Cell
o
N
j
j
1
•
2N current cells typically decomposed into a (2N/2×2N/2) matrix
•
Current source cascoded to improve accuracy (Ro effect)
•
Coupled inverters improve synchronization of current switches
– 34 –
Vishal Saxena
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Segmented DAC
– 35 –
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BW vs. UE DACs
Binary-weighted DAC
Unit-element DAC
•
•
Pros
– Min. # of switched elements
– Simple and fast
– Compact and efficient
•
– Good DNL, small glitches
– Linear glitch energy
– Guaranteed monotonic
Cons
•
– Large DNL and glitches
– Monotonicity not guaranteed
•
Pros
Cons
– Needs B2T decoder
– complex for N ≥ 8
INL/DNL
•
– INL(max) ≈ (√N/2)σ
– DNL(max) ≈ 2*INL
INL/DNL
– INL(max) ≈ (√N/2)σ
– DNL(max) ≈ σ
Combine BW and UE architectures → Segmentation
– 36 –
Vishal Saxena
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Segmented DAC
• MSB DAC: Mbit UE DAC
…
• LSB DAC: L-bit
BW DAC
• Resolution: N =
M+L
• 2M+L switching
elements
• Good DNL
• Small glitches
• Same INL as
BW or UE
– 37 –
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Comparison
Example: N = 12, M = 8, L= 4, σ = 1%
Architecture
σINL
σDNL
# of s.e.
Unit-element
0.32
LSB’s
0.01
LSB’s
2N = 4096
Binaryweighted
0.32
LSB’s
0.64
LSB’s
N = 12
Segmented
0.32
LSB’s
0.06
LSB’s
2M+L =
260
Max. DNL error occurs at the transitions of MSB segments
– 38 –
Vishal Saxena
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Example: “8+2” Segmented Current DAC
Ref: C.-H. Lin and K. Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6mm2,” IEEE
Journal of Solid-State Circuits, vol. 33, pp. 1948-1958, issue 12, 1998.
– 39 –
Vishal Saxena
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MSB-DAC Biasing Scheme
Common-centroid global biasing + divided 4 quadrants of current cells
– 40 –
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MSB-DAC Biasing Scheme
– 41 –
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Randomization and Dummies
– 42 –
Vishal Saxena
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Current-Steering DAC Unit Cell
– 43 –
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Current-Steering DAC Calibration
– 44 –
Vishal Saxena
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References
1.
2.
3.








Y. Chiu, Data Converters Lecture Slides, UT Dallas 2012.
Rudy van de Plassche, “CMOS Integrated Analog-to-Digital and Digital-to-Analog
Converters,” 2nd Ed., Springer, 2005..
B. Boser, Analog-Digital Interface Circuits Lecture Slides, UC Berkeley 2011.
D. K. Su and B. A. Wooley, JSSC, pp. 1224-1233, issue 12, 1993.
C.-H. Lin and K. Bult, JSSC, pp. 1948-1958, issue 12, 1998.
K. Khanoyan, F. Behbahani, A. A. Abidi, VLSI, 1999, pp. 73-76.
K. Falakshahi, C.-K. Yang, B. A. Wooley, JSSC, pp. 607-615, issue 5, 1999.
G. A. M. Van Der Plas et al., JSSC, pp. 1708-1718, issue 12, 1999.
A. R. Bugeja and B.-S. Song, JSSC, pp. 1719-1732, issue 12, 1999.
A. R. Bugeja and B.-S. Song, JSSC, pp. 1841-1852, issue 12, 2000.
A. van den Bosch et al., JSSC, pp. 315-324, issue 3, 2001.
Vishal Saxena
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