Reactive components for pseudo-resistive
networks
transconductance G* = IS,,[( VG-Vm)/nUT]/Vo.
It is worth noting
that a saturated transistor corresponds to a pseudo-grounded (v*
= 0) pseudo-conductance. The pseudo-ground is noted O*.
E. Fragnih-e, A. van Schaik and E. Vittoz
Indexing terms: Compandors, Resistors
A transcapacitance with a linear relationship between its input
current and the derivative of its logarithmically compressed
output voltage is proposed. It is designed to be compatible with
conductances implemented by single transistors. Compact circuits
Principle of pseudo-capacitance: Transistors TI and & in Fig. 2a
have the same gate voltage. Assuming that they are saturated, they
can be considered as fpeudo-) grounded pseudo-conductances
having the same value G* = i/v,* imposed by T, and imposing i, =
V,G* by T2(Fig. 2b). The voltage vc follows the linear capacitance
law -dvc/dt = iJC = (Vdv,*)(i/CJ. The voltage shift V,, between v,
and vc is constant, thus (dvA/dt= dv,/dt and, using the definition
(eqn. 2) of the pseudo-voltage:
can be implemented using these elements, such as the current
mode resonator shown as an example.
Introduction: Linear networks based on transistors [l] are a very
convenient approach for analogue computation of physical or biological systems modelled by large networks of resistances, because
each resistance is implemented by a single MOS transistor. Each
transistor has a linear relationship between its drain-source current
and the difference between a function of its drain voltage and the
same function of its source voltage. This function of the physical
voltage is called the pseudo-voltage.The transistor therefore implements a pseudo-conductance which ensures the linearity of the currents and the pseudo-voltages in the entire network.
To extend the potential of such linear networks to systems
which include dynamic properties, in this Letter we propose a
compact implementation of a pseudo-transcapacitor which can be
used as building block for several frequency dependant circuits linear in current and pseudo-voltage.
describes the pseudo-capacitance law in terms of current and
pseudo-voltage using the pseudo-transcapacitance P = CUJ V,.
Note that PMOS transistor voltages are defined from ground
(instead of substrate) to terminal, so that v* = V, when v = 0.
The voltage shift
is needed to adjust v, close to the ground
(vA* . V,) in order to maximise the dynamic range of the input current i by keeping the capacitor current ic within the same order of
magnitude as i. Moreover, if the pseudo-voltage vc* is considered
as the pseudo-transcapacitor's ouput instead of v,*, the value of
the pseudo-transcapacitance is increased by a factor exp(VJUT),
which can be adjusted by V,.
A
IVGmvB
m7
7
'
&G*
a
vA*
4-w
'E*
T
GovG
b
C
12
m
Fig. 3 Dqferential current iizput pseudo-transcapacitance and its symbol
a NMOS
b PMOS
c Pseudo-conductance
a Differential current input pseudo-capacitance
b Symbol
Q
:I!*
G*
i4
+C
V-'
V-
a
b
Fig. 2 PMOS single current input pseudo-transcapacitor and its equivalent with pseudo-conductances
a PMOS single current input
.
11
b
LI
Fig. 1 N M O S and PMOS implementation of pseudo-conductance
.
pseudo-transcapacitor
Implementation of pseudotranscapacitor: The circuit of Fig. 2 can
only charge capacitor C. The pseudo-transcapacitor of Fig. 3
solves this problem using a differential input current. The input il
charges capacitor C according to eqn. 3, implemented by the transistors TI and T,, whereas the input i2, through T, and T4, discharges it similarly using ithe mirror TrT6. Using the followers T9TI,and T,-T,, with T, = TI, and T, = T8,the output pseudo-voltage is the capacitor voltage shifted by E,, whereas voltage v, at
the source of transistors TI and T, was shifted by V,,, resulting in
vc* = v,*exp(V,,/U,), where V, = Voic- V,,,. The circuit therefore
implements
b Equivalent with pseudo-conductances
(4)
with a pseudo-transcapacitance
Pseudo-conductance and pseudo-voltage in weak inversion: In an
MOS transistor in weak inversion, the channel current, defined
positive when flowing from terminal A to terminal B (Fig. 1), is
given by
V B / u T - e-VA/U'T)
iAB= &Ise(VG-"Tll)/"UT
(e(+ for NMOS, - for PMOS) (1)
where I,, V, and n are the specific current, threshold voltage and
slope factor of the transistor, U, = k,T/q is the thermodynamic
voltage and vG, v, and vB are the voltages referred to the local substrate at the gate and the terminals A and B. They are positively
defined from the gate and terminals A and B to the substrate for
NMOS transistors (Fig. la), and inversely for PMOS transistors
(Fig. lb). Defining the pseudo-voltage:
+
U* =
(- for NMOS, for PMOS) (2)
where 6 is an arbitrary scaling constant, the transistors in Fig. 1
impose the pseudo Ohm's law i = G*(v,*-v,*), with a pseudo-
ELECTRONICS LETTERS
6th November 1997
Vol. 33
II
The voltage biases Kh, and V,,, must be large enough so that the
followers can drive a load without affecting v,* and vc*. In practice, V,,, and V,,, should set T,-T, and T,-T,, in strong inversion.
It can be shown that the effect of current ILleaking from capacitor C corresponds to a pseudo-conductance g,* = (IL/V,)exp( Kh/
U,) in parallel with the pseudo-capacitance P.
The mismatches
q2, and
in the transistor pairs T,-T,, T,-T, and Ts-Thresult
in a current source (E12-E34*56)(il-i2)
in parallel with e.
Building blocks based on pseudo-transcapacitors:The pseudo-transcapacitor of Fig. 3 is transformed into a grounded pseudo-capacitor by imposing its output pseudo-voltage on its input with a
current conveyor, as shown on Fig. 4a. With constant current Z,
added to the pseudo-capacitor current i, as well as imposed on the
pseudo-transcapacitor input i2,this circuit implements:
No. 23
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1913
duC*
c=dt
= 2 1 - 22
= (2
+ Io)
- 10
=2
(6)
The mismatch between the two current sources I , , as well as the
internal mismatches of the pseudo-transcapacitor, result in an offset current source in parallel with the pseudo-capacitor which will
came a DC pseudo-voltage offset on the pseudo-conductance
loading the terminal vc*.
However, the parasitic pseudo-conductance g,* of the pseudotranscapacitors due to their leakage current IL would limit the
quality factor and the peak gain to Gg*/(2g,*), as well as moving
the zero of the transfer function (eqn. 9) from zero to (g,*IG,*)IT,
(assuming that Cc* = CL* and gL* < G,*).
As illustrated above by the very simple implementation of G*
and G,*, the main advantage of the proposed log-domain reactive
elements resides in their compatibility with linear conductances
implemented by a single transistor. Large resistive networks combined with few reactive elements can thus be implemented very
efficiently.
22 August 1997
0 IEE 1997
Electronics Letters Online No: 19971348
E. Fragnikre, A. van Schaik and E. Vittoz ( M A N T R A Centre for
Neuromimetic Systems, Swiss Federal Institute of Technology of
Lausanne, DI-EPFL Ecublens, CH 1015 Lausanne, Switzerland)
a
b
Fig. 4 Grounded pseudo-capacitor and companding integrator pseudotransinductance
a Grounded pseudo-capacitor
b Companding integrator
References
and ARREGUIT, x : 'Linear networks using transistors',
Electron. Lett., 1993, 29, pp. 297-299
2 SEEVINK, E : 'Companding current-mode integrator: A new circuit
principle for continuous-time monolithic filters', Electron. Lett.,
1990, 26, pp. 2046-2047
1
VITTOZ, E A ,
Pseudo-transcapacitors are closely related to companding integrators [2], which are based on a compression of the input current,
integration of the compressed current by a linear capacitor and an
expansion of the resulting capacitor voltage. Our pseudo-transcapacitor compresses and integrates, but the expansion is not
required since we want to output a pseudo-voltage. Nevertheless,
as shown in Fig. 4b, the expansion is easily performed by a
pseudo-conductance G*, resulting in:
Half volume dielectric resonator antenna
designs
M.T.K. Tam and R.D. Murch
where T = PIG*. Furthermore, controlling inputs i, and iz with
pseudo-voltages v,* and v2* through identical pseudo-conductances G* yields a pseudo-transinductor imposing:
where a gyrator made from three pseudo-conductances G* transforms the pseudo-capacitance c"" into a pseudo-inductance L* =
PIG*=.
Indexing terms: Dielectric-loaded antennas, Antennas
The authors demonstrate that the volume of a conventional
dielectric resonator antenna can be reduced by approximately
half. The technique relies on employing an additional conducting
plate in the DRA, whch acts as an electric wall. Experimental
and simulation results are provided for cylindrical and rectangular
dielectric resonator antenna designs.
Introduction: Recently, dielectric resonators have been shown to
be practical elements in antenna applications and have several
merits including high radiation efficiency, flexible feed arrangement, simple geometry and compactness [l, 21. In this Letter, we
demonstrate that the volume of the dielectric resonator antenna
(DRA) can be approximately reduced by half. We perform this by
utilising a metal plate perpendicular to the conducting ground
plane. The additional plate acts as a shorting post for the electric
field and allows part of the DRA to be removed if certain field
symmetry exists. The use of the metal plate can be likened to the
shorting post used in patch antennas to reduce their length from
U2 to U4. Two different kinds of DRA geometry are investigated:
cylindrical and rectangular.
a
Fig. 5 Current-mode resonator and A C equivalent
a Current-mode resonator
b AC equivalent
Antenna structure: The structure of a probe fed cylindrical DRA
on a ground plane is shown in Fig. la, where the diameter 2r = 72
Example of application: parallel-LC resonator: A current-mode res-
onator can be implemented using a pseudo-transcapacitor, a
pseudo-transinductor and an (optional) pseudo-conductor, as
shown in Fig. 5a. The pseudo-voltage v* across the resonator is
imposed by the pseudo-transcapacitor C controlled by its input
current ic = iin-iciL. The currents iG and iL in the pseudo-conductor G* and at the output of the pseudo-transinductor L* = CL*/
Gg*2are in turn both controlled by v*. The output current io,, is
proportional to v* through pseudo-conductance G,* of the gyrator, resulting in
where z2 = CL* and l / p = G*L*/C"*.Without the pseudo-conductor G*, the resonator has an infinite Q-factor and peak gain.
1914
mm, height h = 3 4 m , dielectric constant = 13, and the coaxial
probe has length 2 = 24mm. Typical expected electric field lines for
the fundamental HEMl, broadside mode have also been included
in Fig. l a and these have been obtained from [3]. By applying
approximate boundary conditions the resonant frequency can also
be calculated approximately and is -950MHz for this example [l].
From the electric field lines drawn in Fig. l a it becomes clear
that a line of symmetry exists along the centre line AB. By including an electric wall in the form of a conducting plate along the
centre line A B and removing the undriven side of the DRA (that
part to the left of the line AB) we can still maintain the same field
distribution in the driven side (right of line A B ) of the DRA as
shown in Fig. 16). Because the field distribution remains the same
we can expect the resonant frequency to remain the same and
therefore we have effectively reduced the volume of the DRA by
half. We refer to this structure as the half cylindrical DRA. It is
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Vol. 33
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