Synchronous Rectification for Forward
Converters
Steve Mappus
www.fairchildsemi.com
1
Agenda
•
Synchronous Rectifier (SR) Characteristics
•
Forward Converter Transformer Reset Techniques
•
Forward Converter SR Gate Drive
•
•
•
Self-Driven
Self
Driven
Hybrid Self-Driven
Control-Driven
•
SR Timing Issues
•
Primary-Side Trigger + Linear Predict Control (LPC)
•
•
Application Example
Measured Data
2
www.fairchildsemi.com
Synchronous Rectification (SR)
D1
Reset
Circuit
NP
NS
L
CO
D2
CIN
Q1
What is Synchronous
y
Rectification?
Rectifier Efficie
ency, ηRECT (%)
Rectifier Diode Efficiency
y
(All Converter Losses Neglected)
•
100%
Benefits of SR
• Higher Efficiency
• Lower output voltage and higher
current applications benefit most
• Parallel MOSFETs for higher current
SR Nomenclature
• Q2→control SR
• Q3→freewheeling SR
90%
80%
VF=0.35V
VF=0.65V
VF=1V
70%
60%
50%
1
2
3
4
5
6
7
8
9
10
11
12
Output Voltage (V)
η=
PO
VO × I O
=
=
PIN VO × I O + VF × I O
Replacing secondary side rectifiers (D1, D2)
with MOSFETs (Q2, Q3)
1
V
1+ F
VO
3
www.fairchildsemi.com
Parallel MOSFETs
Diode Thermal Characteristic
•
•
•
Negative temperature coefficient
Tempp increase = VF decrease
Not easily paralleled
SR Thermal Characteristic
•
•
•
•
•
Positive
P
iti temperature
t
t
coefficient
ffi i t
Temp increase = RDS(ON) increase
T↑, RDS(ON)↑, ID↓, T↓
Automatic current sharing
MOSFETs easily paralleled
Diode vs.
vs MOSFET Thermal II-V
V Characteristics
n = Number parallel MOSFETs
4
www.fairchildsemi.com
Rectifier I-V Characteristics
Rectifier efficiency
η=
PO
VO × I O
=
=
PIN VO × I O + VF × I O
1
V
1+ F
VO
Schottky Rectifier (MBR4035PT, 35V, 40A)
•
Operates in first quadrant (Q1) only
η=86.84%, (VF=0.5V, VO=3.3V)
SR MOSFET (FDMS8670S,
(FDMS8670S 30V,
30V 42A)
η=97.06%, (VF=0.1V, VO=3.3V)
•
RDS(ON)
VF
VF
IF
(a) SR MOSFET
>10% improvement, BUT…
•
Considers RDS(ON) conduction loss only!
•
Operates in third quadrant (Q3)
IF
(b) Schottky Rectifier
5
www.fairchildsemi.com
SR I-V Characteristics
Q1
ID(A)
D ID
VGS4
Ohmic
Region
VGS3
VGS2
VDS
G
VGS
S
VGS1
VF(BD)
D
BVDSS
VGS=0V
(Body-Diode)
VGS1
SR Operates in Third Quadrant
VGS2
VDS
G
VGS3
VGS
S ID
VDS(V)
VGS4
Q3
•
SR
Ohmic
Region
•
•
Low current
RDS(Q1)=RDS(Q3)
High current, SR body-diode will conduct if:
I D × RDS (ON ) ≥ VF ( BD )
For VGS=0V, negative current flows through SR
body-diode
body
diode
6
www.fairchildsemi.com
CCM Buck, Diode Rectification
VGS(Q1)
VIN+VF
VIN-VO
VDS(Q1)
VIN
VD1
VIN-VO
VL
VF
-V
VO
CCM
CCM
VO
=D
VIN
ILO
PD1 = VF × I O × (1 − D)
IDS(Q1)
ID1
t0
t1
t2
CCM Buck Operational Waveforms
•
•
D1 operates
p
in first qquadrant onlyy – operation
p
similar to SR
Lower voltage converters can not tolerate losses associated with diode rectification
www.fairchildsemi.com
DCM Buck, Diode Rectification
DCM and CCM Voltage Gain
1
k=0.01
Volttage Gain
0.8
VO
=D
VIN
k=0.1
0.6
k≥1
kk=0
0.5
5
0.4
0.2
0
0.2
•
•
0.6
0.8
1
Duty Cycle
DCM
VO
=
VIN
0.4
2
4× k
1+ 1+ 2
D
DCM Buck Operational Waveforms
where,
k=
2× L
RO × T
D1 operates in first quadrant only – no negative current flow during DCM
Gain is non-linear during DCM operation
www.fairchildsemi.com
Non-Isolated Synchronous Buck
SR Dominant Losses:
•
Channel conduction
PSR(CH) = I O2 × RDS (ON ) × (1 − D)
Dedicated Controller or Driver
•
•
•
•
•
Minimize dead time
Anti cross-conduction protection
Optimized gate drive current
Emulate asynchronous operation
Reduce body-diode conduction
•
Body-Diode conduction
PSR ( BD ) = V F × I O × t BD × Fs
Where : t BD = (t1 − t 0 ) + (t 3 − t 2 )
•
Reverse Recovery
PSR ( RR ) = QRR × VIN × FS
www.fairchildsemi.com
SR Body-Diode Reverse Recovery
IF
D
-dIF
dt
CGD
CDS
G
RG
RDRV
t0→t1
VF
CGS
t
IF
S
VR
D
(a) Ideal Diode – No Reverse Recovery
CGD
CDS
G
RG
RDRV
t1→t2
IF
(ISD)
CGS
tRR
-dIF
dt
IDS
tA
tB
QA
QB
VF
S
D
QA=IFxtA
QB=IFxtB
Softness=tA/tB
IDS
CGD
IRR
CDS
G
t2→t3
t
VR
RG
RDRV
CGS
t0
t1
t2
t3
(b) SR Body-Diode
Body Diode – “Ideal”
Ideal Reverse Recovery Characteristic
IG
IS(CGS)
S
IS(QRR)
IS(CDS)
SR body-diode has high VF and long tRR!
www.fairchildsemi.com
Parallel SR Schottky Diode
Parasitic Inductance Limitation
di VSR ( BD ) − VF
=
dt
LP1 + LP 2
•
Typical example:
di 1.2V − 0.5V
A
=
= 70
dt
µs
2 × 5nH
•
A
Assume
115A
A lload
d current
dt =
•
15 A × µs
= 215ns
70 A
SyncFET™ with Monolithic Schottky
•
•
•
Minimal parasitic inductance
Low VF
Using same example parameters:
di
A
= 600 (measured )
dt
µs
Current commutation time can exceed
body-diode conduction time
•
dt =
15 A × µs
= 25ns
600 A
Order of magnitude improvement
www.fairchildsemi.com
SyncFET™ Reverse Recovery
FDMS7670 vs FDMS7670S SyncFET™
•
•
•
SyncFET™ QRR improvement of ~10%
Previous generation trench technology would show improvement closer to ~50%
FDMS7670S, SyncFET™ VF=0.43V, FDMS7670 VF=0.7V
www.fairchildsemi.com
Forward Converter SR
∝
∆
∝
(a) Forward Converter SR
(b) Single-Ended Transformer Hysteresis
Forward Converter with SR
•
•
•
•
Q2, Q3 gate drive challenges similar to synchronous buck
Pi
Primary
to
t secondary
d
isolation
i l ti adds
dd additional
dditi l timing
ti i requirement
i
t
Single-ended converter topology requires transformer reset
Optimal SR timing is related to transformer reset method
www.fairchildsemi.com
Transformer Reset Techniques
Active Clamp
Reset
Resonant
Reset
RCD Reset
NP
NS
CCL
NP
NS
NP
NS
Q2
VIN
Q1
Reset Winding
+ Reset Energy Recycled
+ Simple Off-Line Solution
- 50% Duty Cycle Limit (1:1)
- Possible Core Saturation
- Transformer Structure
- Q1 Hard Switched
0
VIN
VIN
Q1
0
0
-VR
-VR
RCD Reset
+ Inexpensive Off-Line Solution
+ >50% Duty cycle Possible
- Reset Energy Dissipated
- Q1 Hard Switched
Resonant Reset
+ Reset Energy Recycled
+ Fewest Components
+ Simple Telecom Solution
- Repeatable Design Difficult
- High VDS Stress
- Not for Off-Line Power
- Not
N t Suitable
S it bl for
f Self-Driven
S lf D i
SR
- Q1 Hard Switched
-VR
Q1
Active Clamp Reset
+ High Efficiency (ZVT)
+ Higher Frequency Operation
+ Lowest Vds Stress
+ Off-Line and Telecom
+ SR Gate Drive
- Q1, Q2 Gate Drive
Hi h Cost
C t
- Higher
- Limited PWM and/or Driver
Choices
Reset Method Impacts Self-Driven SR Gate Drive
14
www.fairchildsemi.com
SR Gate Drive Methods
1.
Self-Driven
2.
Hybrid Self-Driven
3.
Control-Driven
15
www.fairchildsemi.com
Self-Driven SR
Self-Driven SR
•
•
SR gate drive derived from transformer
(as shown) or output inductor
Advantages
• Simple – no timing issues!
• SR gate charge recycled to load
• High efficiency with minimal components
• Best applied to active clamp forward (D and 1-D)
16
Self-Driven RCD Reset Waveforms
www.fairchildsemi.com
Self-Driven SR (Continued)
Self-Driven SR
•
Disadvantages
• SR gate drive is not regulated
• Not compatible with all reset techniques
• Difficult to optimize VGS and RDS(ON)
( ) when VIN > 2:1
• RDS(ON) can vary by 10% or more
• No control of freewheeling SR during start-up or light load
DCM operation
17
RDS(ON) versus VGS for
FDMS7670AS, SyncFET™
www.fairchildsemi.com
Hybrid Self-Driven SR
LO
VC
CIN
VIN
U1
FAN3100C
PBias
1
PWM
R1
2
3
VDD
IN+
IN-
CO
RO
Q1
Q2
5
GND
D1
RC1
OUT
Q3
VS
SBias U2
FAN3100C
4
1
2
C1
3
VDD
OUT
5
GND
IN+
IN-
R2
4
C2
D2
RC2
RCD Forward Converter
Hybrid Self
Self-Driven
Driven SR
•
•
•
•
•
Forward converters with resonant reset signals (ie, RCD or Resonant Reset)
Control SR (Q2) is self-driven
Freewheeling SR (Q3) gate-drive derived from primary-side inverted PWM
Q1 to Q3, primary to secondary timing is critical
Q2 to Q3 timing issues similar to non-isolated synchronous buck
18
www.fairchildsemi.com
Hybrid Self-Driven SR Timing
RC1
LO
RC2
PWM
VC
CIN
U1
FAN3100C
PBias
VIN
PWM
1
PWM
PWM
R1
2
VDD
D1
IN+
IN-
Q2
U2
FAN3100C
SBias
4
1
C1
2
3
VGS(Q1)
CO
Q1
5
GND
3
RC1
OUT
Q3
VS
VDD
OUT
5
GND
IN+
IN-
R2
4
C2
D2
RC2
VGS(Q2)
VGS(Q3)
VC
VIN
Freewheeling SR Timing Adjustments
•
•
•
•
VDS(Q1)
VS
VDS(Q2)
•
VDS(Q3)
t0 t1 t2
Split primary PWM signal
Delay primary PWM rising edge,
edge t0→t2, tRC1
Delay and invert secondary-side Q3 gate drive
Apply tRC2 so that Q3 turns on just after VS goes
negative
Adjust t0→t2 > t3→t4 so that Q2 is OFF prior to Q3 ON
(no cross-conduction for all line & load)
t3 t4 t5
19
www.fairchildsemi.com
RO
Hybrid Self-Driven SR
Advantages
•
•
•
•
Improvement over self-driven SR
Reduce body-diode conduction
Regulate freewheeling SR gate drive
Best applied to RCD or resonant reset forward converters
Disadvantages
•
•
•
•
•
Non-adaptive to varying component or CCM/DCM mode change
C t l SR gate
Control
t drive
d i nott regulated
l t d (VGS proportional
ti l to
t VIN)
Timing adjustments dependant upon R and C tolerance and duty cycle, D
Can not be used if primary PWM includes internal gate drive
Can not control freewheelingg SR against
g
negative
g
current flow (DCM,
(
, pre-biased
p
loads))
Full control of both SR MOSFETs only achievable using Control-Driven
Control Driven SR
20
www.fairchildsemi.com
Control-Driven SR
LO
PBias
U1
FAN3100C
1
2
3
OUT
VDD
Q1a
ININ
IN+
VP
VD
GND
Q3
D2
5
CO
RO
D1
4
Q1b
VIN
Q2
PWM
8
1
2
+
-
3
4
SBias
7
6
+
-
5
U2
FAN3225C
2 Switch Forward Converter (Delays Not Shown)
•
•
•
•
•
•
2 Switch Forward Desired SR Waveforms
Both SR MOSFETs are controlled by primary-side
primary side PWM
General purpose low-side gate drivers or “smart-drivers” often used
Offers full SR control during start-up, light-load, OCP, pre-biased output
SR g
gate drive is regulated
g
and independent
p
of transformer reset method
Q3 timing adjustment similar to previous Hybrid Self-Driven example
RC Delay also needed for Q2 SR
21
www.fairchildsemi.com
Control-Driven SR Timing Delays
Secondary-Side Control
SR secondary can be driven directly by PWM
Secondary
y to p
primary
yp
power stage
g p
propagation
p g
delay
y ((solid arrows))
•
PWM to primary side gate drive and power transformer
Secondary to primary SR propagation delay (dashed arrows)
•
•
•
Power stage and SR delay times are often not equal
SR gate drive naturally leads primary MOSFET gate drive
Timing delay normally added in this path
22
www.fairchildsemi.com
Control-Driven SR Timing Delays
Primary-Side Control
Primary to secondary power stage propagation delay (solid arrows)
•
•
PWM to primary-side gate drive and power transformer
Delay normally added in this path
Primary to secondary SR propagation delay (dashed arrows)
•
•
PWM to pulse transformer and SR MOSFET gate driver
Often need to advance the SR signal (impossible)
Optimal timing adjustment requires primary and secondary sensing
23
www.fairchildsemi.com
Control-Driven SR
Primary-Side Triggering
+
LO
VIN
+
Q1a
1 XP
GND 8
2 XN
SOUT 7
3 SIN
VDD 6
VO
R1
FAN6210
D2
DB
LM
Q3
CO
R2
D1
Q1b
R3
4 RDLY DET 5
R4
Q2
DZ
FAN6206
1 LPC1
PWM
SR1 8
2 LPC2 GND 7
3 SN
SR2 6
4 SP
VDD 5
Primary Sensing
•
•
Any single-ended
A
i l
d d PWM input
i
t (SIN)
Transformer reset voltage (DET)
Secondary Sensing
•
•
Q2 drain
drain-source
so rce voltage
oltage (LPC1)
Q3 drain-source voltage (LPC2)
24
www.fairchildsemi.com
Primary-Side Triggering
Light Load (CCM)
FAN6210 Waveforms - Light Load (CCM), XP Triggered by DET
•
•
•
•
•
XP rising edge triggers turn-on
turn on for each SR
XN rising edge triggers turn-off for each SR
XN triggered by PWM input (SIN) rising and falling edges
XP control SR turn-on triggered
gg
byy delayed
y PWM output
p (SOUT)
(
)
XP freewheeling SR turn-on normally triggered by DET (shown)
25
www.fairchildsemi.com
Primary-Side Triggering
Full Load (CCM)
SIN
SOUT
300ns
Programmable delay
50ns
XN
50ns
700ns
XP
300ns
100ns
Programmable delay
700ns
50ns
300ns
50ns
300ns
300ns
Gate drive for Freewheeling SR
Gate drive for control SR
DET
FAN6210 Waveforms - Heavy Load (CCM), XP Triggered by XN
•
•
•
•
•
XP rising edge triggers turn-on
turn on for each SR
XN rising edge triggers turn-off for each SR
XN triggered by PWM input (SIN) rising and falling edges
XP control SR turn-on triggered
gg
byy delayed
y PWM output
p (SOUT)
(
)
XP freewheeling SR turn-on normally triggered by DET or XN (shown)
• XP can never trigger while XN is HIGH – prevents SR cross-conduction
26
www.fairchildsemi.com
SR Negative Current Issues
LO
INEG
Q1
VIN
PWM
CIN
Forward SR
Synchronous Buck
•
•
•
•
•
•
Q2 blocks INEG when Q3 turns off (Q2 off)
INEG charges SR COSS during Q3 off
BVDSS stress from switching INEG
SR switching adjustment required (as shown)
•
Q2
CO
RO
IO
Q1 drain clamped to DC source
Q2 VDS clamped to DC source through Q1
body-diode
Negative inductor current ok for VDS
www.fairchildsemi.com
Linear Predict Control (LPC)
LO
+
VO
R1
Power
Stage
((Primary)
y)
Q3
CO
R2
R3
R4
Q2
FAN6206
1 LPC1
SR1 8
2 LPC2 GND 7
FAN6210
((XP, XN))
3 SN
SR2 6
4 SP
VDD 5
1
1
< Ratio LPC 2 <
VO
VO − 0.5V
•
•
•
•
•
LPC Function is used to turn off Q3 before ILO<0A during DCM operation
During CCM SR gate drive controlled by SP(XP) and SN(XN)
SN signal follows PWM signal and can not turn off Q3 before ILO<0
Both SR VDS monitored by resistor dividers
Solves Problem of Negative SR Current
28
www.fairchildsemi.com
Primary-Side Triggering (DCM)
FAN6206 Waveforms - Light Load (DCM)
29
www.fairchildsemi.com
Primary-Side Triggering
Advantages
•
•
•
•
•
•
•
Easily implements correct primary to secondary SR timing for forward converters
No RC timing adjustments required
Compatible with all forward transformer reset techniques including 2 switch forward
Can be used with any single-ended PWM controller
G
Green
mode
d ffunction
i di
disables
bl ffreewheeling
h li SR gate drive
d i for
f D<10%
D 10%
Operates in CCM and DCM
Freewheeling SR control prevents negative current flow
Be Aware of
•
•
SR Gate drive current limited to 0.7A/1A (source/sink)
• Use FAN3xxx series low-side ggate drivers for drivingg higher
g
gate
g charge
g
Internal fixed delays result in longer body-diode conduction times at higher frequency
• For low output voltage converters SyncFET can help
30
www.fairchildsemi.com
Primary-Side Triggering
Application Circuit Specifications
INPUT
I
Input
t Voltage
V lt
90VAC<V
VIN(AC)<264V
264VAC
Line Frequency
47Hz<FLINE<63Hz
PFC Output
310VDC<VBULK<380VDC
OUTPUT
Output Voltage
12VDC
Output Power
300W
Load Current
25A
Switching Frequency
65kHz
Intended Application: PC Power (Computing)
31
www.fairchildsemi.com
Why 65kHz Operation?
dBuV
dBuV
100
100
Fundamental
(66kHz)
Fundamental
(100kHz)
90
90
80
80
2nd harmonic
(132kHz)
70
70
60
60
50
50
40
40
30
30
20
20
10
10
100k
150k
200k
300k
500k
EN 55022 QP
EN 55022 AV
100k
1M
Frequency spectrum with 66kHz operation
•
•
2nd harmonic
(200kHz)
150k
200k
300k
500k
1M
Frequency spectrum with 100kHz operation
Lower EMI
Trade Off: EMI filter size versus transformer size
32
www.fairchildsemi.com
Primary-Side Triggering
Application Validation Circuit
33
www.fairchildsemi.com
Measured Waveforms
Steady State and LPC Function
Control
SR Gate
Freewheeling
SR Gate
XP (SP)
XN (SN)
LPC
VDS Freewheeling SR
S and S
SP
SN control S
SR switching
i i
LPC function during DCM operation
PWMIN
(SIN)
300ns
Freewheeling
SR G
Gate
XP, XN
XN
XP
SOUT
SIN→SOUT, 300ns fixed turn-on delay
SIN→SOUT, 100ns fixed turn-off delay
34
www.fairchildsemi.com
Measured Waveforms
SR Dead-Time, Load Transient
PWMIN
(SIN)
XP, XN
XP
XN
Freewheeling
SR Gate
400ns
Control
SR Gate
FW SR↓→Control SR↑, 500ns dead-time
FW SR↑→Control SR↓, 400ns dead-time
0A→10A load transient
10A→0A load transient
35
www.fairchildsemi.com
Measured Waveforms
Start-Up, OCP, Green Mode
SOUT
VOUT=8.8V
ZOOM
VOUT
SOUT
Control SR
Freewheeling SR
SR control during start-up
FW SR control during start-up
D=7.8%
PWMIN
(SIN)
XP, XN
VDS Freewheeling SR
VDS Control SR
10A→64A overload transient
Green mode function enabled for D<10%
36
www.fairchildsemi.com
Measured Efficiency
Schottky vs SR
SR Efficiency Comparison
(115VAC Input, 12VDC Output, 300W, 12V/25A Output)
95%
Primary-Side Trigger Control-Driven SR
(FDP5800)
Schottky Rectifiers (FYP2006DN)
Efficiency (%)
90%
85%
80%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Output Power (%)
300W=100%
37
www.fairchildsemi.com
Summary
•
Self-Driven SR
• Best for active clamp forward where IO(MIN) > ILO/2 (BCM)
• SR gate drive independent from primary control
•
Hybrid Self-Driven SR
• Performance improvement over self
self-driven
driven SR
•
Control Driven SR
• SR timing is critical
• Difficult to implement discretely
•
FAN6210+FAN6206
• Simplifies SR timing
• Freewheeling SR control during DCM operation
Evaluate all SR solutions under steady state and dynamic test conditions!
38
www.fairchildsemi.com
Questions?
THANK YOU!
39
www.fairchildsemi.com
References
1. “FAN6210 — Primary-Side
y
Synchronous
y
Rectifier (SR)
( ) Trigger
gg Controller for Dual
Forward Converter”, Datasheet, Fairchild Semiconductor, March 2010.
2. “FAN6206 — Highly Integrated Dual-Channel Synchronous Rectification Controller for
Dual-Forward Converter”, Datasheet, Fairchild Semiconductor, April 2010.
3 “AN
3.
AN-6206
6206 — Primary-Side
Primary Side Synchronous Rectifier (SR) Trigger Solution for DualDual
Forward Converter”, Fairchild Semiconductor, April 2010.
40
www.fairchildsemi.com
Follow us on Twitter twitter.com/fairchildSemi
View product and company videos, listen to podcasts and comment on our blog @ www.fairchildsemi.com/engineeringconnections
Visit us on Facebook @ www.facebook.com/FairchildSemiconductor
www.fairchildsemi.com