Synchronous Rectification for Forward Converters
Steve Mappus
I.
INTRODUCTION
For switched mode power supplies (SMPS), rectifier
diodes are routinely used to convert AC voltage
waveforms to a regulated DC output voltage. The
conduction loss of a rectifier diode contributes
significantly to the overall power loss, especially for
low-voltage, high-current converter applications. As a
simple example, consider the non-isolated buck
converter shown in Fig. 1.
2 From Equation (2), it is apparent that for lower output
voltage converters, the rectifier conduction loss becomes
a greater percent of the total converter loss. Fig. 2
illustrates the impact rectifier diode conduction loss has
on overall efficiency for several typical values of VF.
Rectifier Diode Efficiency
Rectifier Efficiency, ηRECT (%)
Abstract — In many switching power converters, rectifier diodes
are used to obtain the DC output voltage. The conduction loss of a
diode rectifier contributes significantly to the overall power loss,
especially for low-voltage, high-current converter applications. The
conduction loss of a rectifying diode is given by the product of its
forward-voltage drop and forward conduction current. By replacing
the rectifier diode with a MOSFET operated as a synchronous
rectifier (SR), the equivalent forward-voltage drop can be lowered
and, consequently, the conduction loss can be reduced.
Since SRs are active devices, the gate driving method and proper
timing are critical for obtaining high efficiency. This paper describes
the benefits and unique challenges of implementing MOSFETs as SR
devices in forward converter applications. Trade-offs and challenges
between self-driven, hybrid self-driven, and control-driven SR
techniques are discussed in detail. A unique control-driven, primaryside triggering SR drive solution is introduced and validated in a
300W, off-line, two-switch forward converter.
(All Converter Losses Neglected)
100%
90%
80%
VF=0.35V
70%
VF=0.65V
60%
VF=1V
50%
1
2
3
4
5
6
7
8
9 10 11 12
Output Voltage (V) LO
Fig. 2. Rectifier diode efficiency.
Q1
VIN
PWM
CIN
D1
VF
CO
RO
IO
Fig. 1. Non-isolated buck, diode rectification.
The duty cycle, (D), of Q1 is directly controlled using an
analog or digital pulse-width modulator (PWM) controller
where the Schottky rectifier, D1, conducts during the
interval when Q1 is off (1-D). Since it is not actively
controlled, the switching action of D1 is simple and the
power dissipated due to conduction loss is given by:
P
V
I
1
D 1 Even in the best case for a 1V output converter using a
Schottky rectifier with VF=0.35V, a 25% efficiency
penalty cannot be tolerated for most modern DC-DC
converter applications.
Replacing a Schottky diode with a SR MOSFET
introduces a rectifier possessing almost linear resistance
characteristics and a lower forward-voltage drop.
Consequently, the rectifier conduction loss can be
reduced. Fig. 3 compares the equivalent forward-voltage
drop between a 30V SR MOSFET and a 35V Schottky
rectifier, each operating with a forward current of 15A.
The conduction loss of Fairchild’s FDMS8670S SR
MOSFET is 1.5W compared to 7.5W for Fairchild’s
MBR4035PT Schottky rectifier.
If all other associated losses are ignored and a
constant duty cycle assumed, the overall efficiency due
to rectifier diode conduction loss can be expressed by:
Fairchild Semiconductor Power Seminar 2010-2011
1
replaced by a MOSFET SR. However, several loss
mechanisms must be accounted for when considering
MOSFET SRs, such as Q2, shown in Fig. 4.
LO
Q1
VIN
Q2
PWM
CO
CIN
RO
IO
Fig. 3. Forward-voltage drop comparison between an SR MOSFET and
Schottky diode rectifier.
In addition to minimizing conduction loss, SR
MOSFETs have the added benefit of being easily
paralleled. The combination of conduction, switching,
gate-charge, and body diode related losses all contribute
to how much power is dissipated within the SR
MOSFET. Higher power dissipation leads to increased
device junction temperature. As MOSFETs have a
positive temperature coefficient, their RDS(on) increases
with increasing temperature. For two or more SR
MOSFETs used in parallel, the positive temperature
coefficient is responsible for reducing the current
flowing in the hotter device, forcing more current to
flow in the cooler device. For very high current
applications, two or more SR MOSFETs can be placed
in parallel and the total current is shared between devices
at least well enough to prevent potential damage due to
thermal runaway. Conversely, Schottky rectifiers have a
negative temperature coefficient. As the device junction
temperature of a Schottky rectifier increases; the voltage
decreases, resulting in even more current flowing in the
hotter device. The problem can be mitigated by two
devices manufactured on the same die, but it is not
generally recommended to use parallel Schottky diodes
in high-current switching power supply applications.
II.
SYNCHRONOUS RECTIFIER LOSSES
Lower conduction losses and ease of parallel
operation are two unmistakable benefits that can lead to
higher converter efficiency when a Schottky rectifier is
Fairchild Semiconductor Power Seminar 2010-2011
Fig. 4. Non-isolated synchronous buck converter.
Channel conduction loss (PSR(CH)), body diode
conduction loss (PSR(BD)), and reverse recovery loss
(PSR(RR)) are three major contributors to power
dissipation within a SR. These are calculated by:
1
3 4 5 From Fig. 4, at time t0, Q1 is switched off and the load
current is commutated from the RDS(on) channel
resistance of Q1 to the body diode of Q2. At time t0+,
VDS(Q2) is still present while the full load current is
flowing in the Q2 body diode. The high voltage and
current simultaneously present across the Q2 body diode
results in reverse recovery loss in the SR as defined by
Equation (5). The QRR term shown in Equation 5 defines
the reverse recovery charge that can be obtained from
the MOSFET data sheet.
2
During the dead time, t0→t1, the full load current
freewheels through the body diode of Q2. Since the SR
internal body diode has much worse electrical
characteristics than a Schottky rectifier, reducing the
t0→t1 and t2→t3 conduction times is imperative to
maximizing SR performance. From t1→t2, Q2 conducts
the full load current through its RDS(on) channel resistance.
When the channel conduction time is much greater than
the body diode conduction time, the time interval t1→t2
can be approximated by 1-D and used to determine
conduction loss as shown in equation (3). At time t2, Q2
is switched off and the current is commutated from the
RDS(on) channel resistance of Q2 to the body diode of Q2.
Therefore, for one complete switching cycle of Q2, there
are two distinct body diode conduction time intervals.
The sum of these two time intervals, t0→t1 and t2→t3,
defines tBD used in Equation (4) to estimate the total SR
body diode conduction loss.
There are several techniques for dealing with body
diode reverse-recovery associated losses in SR
applications. Slowing the turn-on time of the control
MOSFET Q1 reduces the magnitude of the reverserecovery current flowing in Q2 at the expense of
increasing Q1 switching loss. However, for highfrequency switching applications, this is most likely an
unacceptable compromise. A better approach is to
reduce the dead time to near zero. Zero dead time means
there would be no current flowing in the SR body diode,
eliminating the reverse-recovery and body diode
conduction losses. As a result, adaptively controlling
critical timing parameters has been a developmental
focal point of most modern synchronous buck
controllers and gate drive ICs. With the exception of
some advanced digital control algorithms, the dead-time
between Q1 and Q2 normally appears as some value
slightly greater than zero to avoid potential shootthrough current.
A common approach for dealing with SR body diode
associated losses is to insert a Schottky rectifier in
parallel with the SR, as shown in Fig. 5.
Fairchild Semiconductor Power Seminar 2010-2011
Fig. 5. Reducing SR body diode loss with parallel Schottky rectifier.
During the dead time, it is desirable for the load
current to flow through the parallel Schottky rectifier,
D2, which has negligible QRR and a lower VF compared
to the body diode of Q2. The effectiveness of this
approach can be limited by parasitic inductances LP1 and
LP2. Placing D2 directly across the drain and source
terminals of Q2 helps minimize parasitic trace
inductance, but bond wire and lead inductances may still
dominate, especially at higher switching frequencies. As
an example, Fairchild’s FDMC7660, 30V 20A
PowerTrench® MOSFET specifies VF of its internal
body diode as 1.2V. Adding a parallel Schottky rectifier
with VF=0.5V and assuming LP1=LP2=5nH, would yield:
.
.
70
6 Assuming 15A load current:
215
7 The result of Equation (7) indicates it would take
215ns to transition the current from the body diode to the
parallel Schottky. When the transition time (215ns)
exceeds the total body diode conduction time, the
effectiveness of adding a parallel Schottky rectifier is
negated. Since inductive reactance is proportional to
frequency, adding a small amount of resistance to the
MOSFET gates slows down the switching transitions
and helps mitigate the adverse effects of LP1 and LP2.
However, this still may not justify an external Schottky
rectifier for reducing body diode conduction loss.
Adding a parallel Schottky rectifier can help reduce SR
body diode current during power supply startup or lightload operation when the SR is sometimes disabled.
Fairchild’s SyncFETTM MOSFET family was
specifically developed for SR applications. A
PowerTrench® MOSFET and an integrated parallel
Schottky rectifier are included in a single package. The
3
body diode, 0.43V compared to 0.7V. This results in
substantially less power loss during the dead time in a
synchronous buck converter application.
Measured QRR
20A, 300A/µs
6
4
FDMS7670
FDMS7670S
Isd (A)
Schottky diode cell can be interleaved through the
MOSFET active area or placed separately in a dedicated
area on the die, providing an extremely small physical
separation from the MOSFET body diode. Interleaving
helps evenly distribute the current density within the die.
This leads to lower thermal stress and optimized
Schottky diode VF vs. ID electrical characteristics. Using
either method, monolithically fabricating the Schottky
rectifier with the MOSFET essentially eliminates LP1
and LP2 and allows faster commutation of current into
the Schottky diode. An example of a SyncFETTM
MOSFET interleaving process is shown in Fig. 6.
2
0
-2
-4
0
10
20
30
40
50
time (ns)
Fig. 7. Reverse recovery waveforms for SyncFET MOSFET vs. nonSyncFET MOSFET.
Because SRs are active devices, their ability to
outperform a Schottky diode rectifier is highly
dependent upon the gate driving method used and timing
with respect to the PWM controlled MOSFET. A
summary of performance characteristics important for
driving SRs in non-isolated synchronous buck converters
would include:
Fig. 6. SyncFET™ MOSFET monolithic fabrication.
As mentioned, a Schottky rectifier generally has a QRR
lower than that of an intrinsic body diode. The reverserecovery current waveforms shown in Fig. 7 compare a
FDMS7670S SyncFET™ MOSFET to a similar sized
FDMS7670 non-SyncFET™ MOSFET die. The reverserecovery charge, QRR, is determined from the measured
source-drain current (Isd) and reverse-recovery time (tRR)
and results in a QRR improvement of 10%. The higher
channel density and deeper cell trench used in
Fairchild’s low-voltage process yields a body diode
possessing intrinsic reverse-recovery characteristics
more closely associated with a Schottky rectifier.
SyncFET™ MOSFET comparisons made using previous
generation standard trench technology would yield QRR
improvements closer to 50%. Because the Schottky is
integrated with the MOSFET, its forward-voltage drop is
much lower than the voltage drop across the intrinsic
Fairchild Semiconductor Power Seminar 2010-2011
1. Anti-cross-conduction protection to assure that the
two MOSFETs, Q1 and Q2, never actively conduct
at the same time.
2. Minimizing the dead time between Q1 and Q2 to
reduce frequency-related power losses associated
with SR MOSFET body diode conduction and
reverse-recovery time.
3. Peak gate drive current optimized to efficiently
overcome the high-gate charge associated with low
on-resistance SR MOSFETs.
4. Very low impedance pull-down on the SR gate drive
to assure the gate is held LOW when high dv/dt is
applied across the drain-source terminals.
For non-isolated synchronous buck converters, most
of the issues associated with driving the SR MOSFET
are covered by features incorporated in numerous PWM
controllers and gate driver ICs dedicated to this popular
converter topology. The interface between the PWM
controller and the power stage is direct. The controller or
gate drive IC can sense the current in any leg or the
voltage at any node and use this information for making
decisions regarding proper gate drive timing. For
4
isolated buck derived converters, the introduction of a
power transformer adds a new set of SR challenges in
addition to many of the same concerns related to the
non-isolated synchronous buck.
III.
FORWARD CONVERTER SR
CONSIDERATIONS
The forward converter is sometimes referred to as an
isolated buck converter in that the secondary side
includes two rectifiers used in a high-side, low-side
configuration. Similar to a non-isolated synchronous
buck converter, the two output SRs feed a LC filter;
except that a power transformer isolates the input
voltage from the regulated DC output voltage. Because
Q2 is in series with the transformer secondary, it can be
moved from the high-side to the low-side, as highlighted
in Fig. 8.
Magnetic flux density varies between B1 and B2 at a
rate determined by the converter switching frequency.
To prevent core saturation, the magnetic flux must return
to B1 at the end of every switching cycle. A negative
reset voltage, shown in Fig. 10 as -VR, is applied to the
transformer primary, forcing the core to reset. There are
four basic reset circuits commonly applied to forward (or
flyback) converters: third-winding reset, resonant reset,
RCD reset, and active-clamp reset.
Fig. 8. Forward converter with synchronous rectifiers.
Moving Q2 to the low-side secondary return
simplifies the task of driving Q2 and Q3 since they are
both ground referenced. The driving methods for Q2 and
Q3 are discussed in detail in the following section.
The forward converter (or flyback converter) is a type
of single-ended isolated power converter. Because
single-ended converters operate transformers with
positive voltage and positive current, operation is limited
to the first quadrant of the BH curve, as shown in Fig. 9.
∝
∆
∝
Fig. 9. Single-ended transformer operation.
Fairchild Semiconductor Power Seminar 2010-2011
Fig. 10. Single-ended transformer reset circuits.
The forward-converter topology is defined by the type
of reset circuit used. As a result, the transformer reset
waveform, -VR, differs depending upon the type of reset
chosen. For a self-driven SR approach, -VR reflected to
the transformer secondary is often used to drive the gate
of the freewheeling SR MOSFET, Q3. Any dead time
that exists in the primary, such as the plateaus between
VIN and –VR shown in Fig. 10 appear as body diode
conduction on the secondary. Therefore, the ability to
optimize timing between Q2 and Q3 is highly dependent
upon the type of reset circuit.
Based on the method used to derive the SR gate drive
signals, the implementation of SR for isolated converters
can be classified into one of three types shown in Fig. 11
through Fig. 13.
5
flows though the body diode of Q2 until the voltage on
NS is large enough to turn on SR MOSFET, Q2.
Conversely, when the primary-side MOSFET, Q1, is
turned off; the reset voltage induces a negative voltage
seen across NS. Secondary-side current flow is initially
through the body diode of Q3. The conducting body
diode of Q3 places a positive voltage on the gate of SR
MOSFET, Q2. Since the SR body diodes conduct on
every switching cycle and the transformer secondary
voltage requires a finite time to transition between power
transfer and reset, there is an unavoidable dead time.
Despite its simplicity, there are limitations to self-driven
SR.
The Q2 SR gate drive is directly proportional to VIN
by the transformer turns ratio; therefore, when VIN varies
by 2:1, VGS for the Q2 SR also varies by 2:1. As shown
in Fig. 14, if the minimum SR VGS=5V, RDS(ON) can
increase by 10% or more compared to when VGS=10V.
Fig. 11. Self-driven SR method.
Fig. 12. Hybrid self-driven SR method.
LO
XFMR NP
Reset
NS
Q3
CO
RO
CIN
VIN
PBias
FAN3100C
1
2
PWM
3
VDD
OUT
Q1
5
Q2
GND
IN+
IN-
4
FAN3225C
8
1
2
+
-
3
4
SBias
7
6
+
-
5
Fig. 13. Control-driven SR method.
Self-Driven Synchronous Rectification
The circuit shown in Fig. 11 is one example of the
self-driven SR method where the gate drives are derived
directly from the transformer secondary voltage, but
several variations of this technique can also be applied.
Alternatively, the gate drive signals can be derived from
the output inductors or dedicated secondary-side
transformer windings. The one thing that all self-driven
SR circuits have in common is that the secondary-side
gate drives are developed independently from the
primary-side control. Self-driven SR requires no
primary-side information, making its operation
comparatively simple. When the primary-side MOSFET,
Q1, is switched on; VIN appears across the transformer
primary, NP. The transformer secondary also sees VIN
reduced by the transformer turns ratio. As positive
voltage is initially building across NS, secondary current
Fairchild Semiconductor Power Seminar 2010-2011
Fig. 14. RDS(ON) vs. VGS for FDMS7670AS SyncFET™ MOSFET.
For applications where the input voltage variation is
greater than 2:1, it becomes even more difficult to
optimize RDS(ON) for varying VGS and assure operation
less than absolute maximum ratings. Also, the Q3 SR
gate drive voltage is determined from the transformer
primary reset voltage. Each reset technique in Fig. 10
produces a different waveform that may or may not be
best suited for deriving the Q3 SR freewheeling gate
voltage. As a result, the freewheeling SR can be
subjected to excessive body diode conduction time when
used with a resonant or RCD clamp reset mechanism.
For this reason, the active clamp reset circuit that
6
operates with full D and 1-D for a full switching period,
is best suited for self-driven SR. One of the motivations
for considering the active clamp forward is the ability to
achieve zero (or reduced) voltage switching (ZVS).
Low-voltage SR MOSFETs with extremely low RDS(on)
tend to have very high gate capacitance, CGS. In a selfdriven SR application, such as in Fig. 11, the CGS is
reflected back to the primary side, negatively influencing
ZVS of an active clamp forward or resonant reset time of
a RCD clamp.
For instances where light-load efficiency is a concern,
the self-driven SR forward can exhibit lower efficiency
compared to Schottky diode rectification. SR MOSFETs,
especially when operated in parallel, possess very high
gate charge. Gate charge losses contribute significantly
to overall power loss during light-load operation. One
redeeming quality is that the power associated with gate
charge is regenerated back to the load.
Considering these limitations, self-driven SR can be
an attractive option for gaining relatively high efficiency
with minimal circuit complexity. For low-voltage, highcurrent applications with narrow VIN range and for active
clamp forward converters where the secondary-side
driving voltage is square (D and 1-D); self-driven SR
can be a viable option over diode rectification.
Hybrid Self-Driven Synchronous Rectification
Hybrid self-driven SR uses the primary-side PWM
signal to control the freewheeling SR MOSFET, Q3. The
control SR MOSFET, Q2, remains self-driven with
operation as described above.
Fig. 15. Schematic for RCD forward converter with hybrid self-driven SR.
Fairchild Semiconductor Power Seminar 2010-2011
Fig. 16. RCD forward converter with hybrid self-driven SR.
The advantage of hybrid self-driven SR over selfdriven SR can best be explained referring to the RCD
clamp forward converter waveforms shown in Fig. 16.
When operating in discontinuous conduction mode
(DCM), the RCD clamp forward converter exhibits a
long dead time, shown as tBD2 in Fig. 16. During time
tBD2, the transformer secondary voltage, VS, is zero;
resulting in an extended period of body diode conduction.
Also, the self-driven gate drive waveform for the
freewheeling SR, VGS(Q3), can have a slow rising edge,
due to the transformer leakage inductance, and a very
slow resonant falling edge. However, the control SR gate
drive, VGS(Q2), directly follows VGS(Q1) according to the
duty cycle, D. In an effort to reduce the amount of
secondary-side body diode conduction and approximate
full D and 1-D switching, hybrid self-driven SR can be
7
an effective solution for RCD forward type converters.
In addition to the RCD clamp forward, other examples
may include resonant reset and third-winding reset.
A hybrid self-driven configuration derives VGS(Q2)
from the secondary-side transformer voltage, but VGS(Q3)
is driven by inverting (1-D) the primary-side PWM
signal (D). By applying the PWM signal to the inverting
input of a low-side MOSFET driver such as Fairchild’s
FAN3100, the gate drive signal phasing can be
developed for VGS(Q3). There are two RC delay circuits
highlighted in the schematic in Fig. 15. In addition to
inverting the primary-side PWM signal, the primary-tosecondary timing relationship, naturally maintained with
self-driven SR, must be accounted for by applying one
or more external RC delay circuits. All timing
adjustments are made with respect to the PWM control
signal; but ultimately, SR gate drive timing must properly
align with the transformer secondary voltage, VS.
The secondary-side freewheeling SR MOSFET, Q3,
should be turned on just after VS goes negative. Turning
on Q3 too early results in cross-conduction with Q2
turn-off and potentially damaging shoot-through current.
Turning on Q3 too late lowers efficiency by permitting
undesirable body diode conduction in Q2 and Q3. Q3
must be turned off just before VS transitions positive.
Turning off Q3 too early allows additional body diode
conduction as tBD2 is increased, making the operation of
Q3 appear more like the self-driven case. Turning off Q3
too late can result in shoot-through current.
As shown in the Fig. 15 schematic, splitting the PWM
control signal between U1 and U2 provides the timing
reference needed for making the necessary primary and
secondary-side gate drive adjustments. On the primary
side, VGS(Q1) rising edge is delayed and this is highlighted
in Fig. 16a as τRC1. Placing D1 across R1 in the direction
shown assures the falling edge of VGS(Q1) undergoes a
minimal delay with respect to the PWM input signal. On
the secondary side, VGS(Q3) rising edge is delayed and
this is highlighted in Fig. 16a as τRC2. Delaying the rising
edge of VGS(Q3) requires a delay applied to the falling
edge of the PWM input signal to U2. Placing diode D2
across R2 in the direction shown assures that the falling
edge of VGS(Q3) is only minimally delayed with respect to
the PWM input signal. When properly applied, the delay
time from the PWM rising edge to the rising edge of
Fairchild Semiconductor Power Seminar 2010-2011
VGS(Q1) is longer than the delay time from the PWM
falling edge to the falling edge of VGS(Q1). This condition
must be met to assure that the control SR, Q2, is
switched off prior to the start of the next freewheeling
period when Q3 is switched on.
The hybrid self-driven technique can offer significant
improvement over self-driven SR; however, it is nonadaptive to varying component values, parasitic
inductances, and capacitances and CCM versus DCM
operating mode changes. Therefore, primary-tosecondary timing adjustments must be made, taking
worst-case operating parameters into account. The
minimum timing delay is normally set at minimum D
(VIN(MAX)) and with the converter sourcing minimum
load current (DCM). When the converter is operating
under heavy load current (CCM) the optimal required
delay time is less than the set delay time. Since the
control SR, Q2, is self-driven; primary-to-secondary
timing adjustments are only made for the control-driven
freewheeling SR MOSFET, Q3. For cases where full
control of both secondary-side SR MOSFETs is required,
a control-driven SR method is the only solution.
Control-Driven Synchronous Rectification
Using the PWM signal to control SR switching
overcomes all of the issues associated with self-driven
SR. Both SR gate drives are regulated and, therefore,
independent of input voltage variations or reset method;
so switching transitions remain constant over line and
load. Since the output is controlled by the PWM,
decisions can be made regarding when to turn off the
SRs based on load current or output voltage. The single
biggest challenge related to control-driven SR is the
timing relationship between the primary-side MOSFET,
Q1, and the output SR MOSFETs, Q2 and Q3. For the
hybrid self-driven SR method, only the control-driven
freewheeling SR MOSFET required timing adjustments.
Control-driven SR requires timing adjustments to both
SR MOSFETs. Applying the correct timing delays
requires a detailed understanding of all primary to
secondary delay elements.
The two-switch forward converter shown in Fig. 17
limits the maximum VDS of the two primary MOSFETs
to VIN, making it a popular choice for off-line power
conversion.
8
primary-to-secondary delay through the power stage
(heavy bold arrows) is often not equal to the delay to the
SR MOSFETs (dashed line arrows).
Fig. 17. Two-switch forward converter with control-driven SR.
Fig. 19. Two-switch forward converter timing delay paths.
Fig. 18. Desired waveforms for control-driven SR.
In most cases, the high-voltage gate drive circuitry for
the primary MOSFETs has a different propagation delay
compared to the low-voltage, secondary-side SR gate
drive circuitry. The power stage delay also includes an
off-line power transformer with a larger propagation
delay than the pulse transformer used to pass the SR gate
drive signals to the secondary side. Optimizing proper
SR gate drive timing is further complicated by the fact
that the PWM can be located either on the primary (as
shown in Fig. 19) or secondary side. As a result, the task
of implementing control-driven SR often requires more
accurate timing adjustment algorithms that can be
designed discretely, but are much simpler when
integrated into a silicon solution.
The two primary-side MOSFETs are switched on and
off simultaneously according to the PWM duty cycle. It
follows that the control SR, Q2, should be turned on just
after the primary MOSFETs are turned on. Similarly, Q2
CONTROL-DRIVEN SR USING
should be turned off just prior to the primary MOSFETs IV.
PRIMARY-SIDE TRIGGERING
turning off. The freewheeling SR MOSFET, Q3, should
then be turned on just after the primary MOSFETs turn
Fig. 20 is a two-switch forward converter that senses
off. Q3 should then be turned off just before the primary primary and secondary-side power stage information to
MOSFETs are turned on. The primary-to-secondary accurately compose secondary-side SR gate drive signals.
timing adjustment for Q3 is similar to that described for Fairchild’s FAN6210 primary-side SR trigger controller
the hybrid self-driven case. Another RC timing uses a single channel PWM signal input (SIN) to generate
adjustment would need to be applied to U2, pin 8. While two edge-triggered output signals, XP and XN. An
all timing adjustments are made with respect to the internal fixed-time delay applied to the PWM input
PWM control signal, ultimately the SR gate drive timing signal allows the time necessary to align the secondarymust properly align to the transformer secondary voltage, side SR MOSFET switching transitions with the applied
VS, and guarantee non-overlapping SR signals during transformer voltage.
primary to secondary power transfer. Relying strictly on
RC delay timing can be difficult, if not impossible, for
obtaining proper SR timing. As shown in Fig. 19, the
Fairchild Semiconductor Power Seminar 2010-2011
9
+
LO
VIN
+
Q1a
FAN6210
1 XP
GND 8
2 XN
SOUT 7
3 SIN
DB
VO
R1
D2
LM
Q3
CO
R2
D1
Q1b
VDD 6
R3
4 RDLY DET 5
R4
Q2
DZ
FAN6206
PWM
1 LPC1 SR1 8
2 LPC2 GND 7
3 SN
SR2 6
4 SP
VDD 5
Fig. 20. Two-switch forward converter, primary-side trigger SR control.
Fig. 21. FAN6210 SR timing diagram vs. load current, heavy load condition, XP triggered by XN.
Fig. 22. FAN6210 SR timing diagram vs. load current, light load condition, XP triggered by DET.
Fairchild Semiconductor Power Seminar 2010-2011
10
As seen in the timing diagrams of Fig. 21 and Fig. 22,
the rising edge of XP is used to determine the turn-on
time of Q2 and Q3, while the rising edge of XN is used
to determine the turn-off time of Q2 and Q3. XP and XN
signals are narrow pulses representing delayed primaryside PWM edges. XN has a 300ns pulse width and is
always triggered by the rising and falling edge of the
PWM input signal after a 50ns internally set delay.
Corresponding to the PWM input rising edge, XN is sent
to the secondary-side, where it is used to turn off the
freewheeling SR MOSFET. Only after the freewheeling
SR is turned off can the SOUT signal be applied to the
primary-side MOSFETs. The 300ns internal delay
ensures that the freewheeling SR is always turned off
before the primary-side MOSFETs are turned on.
After the delayed PWM input signal (SOUT)
transitions HIGH, the XP signal is then released,
commanding the turn-on of the secondary-side SR
MOSFET, Q2. The dead-time between SOUT and XP
should be minimized and is therefore user-adjustable by
a single resistor from RDLY to ground. XP has a 700ns
pulse width and requires these conditions be met for
triggering:
ƒ
Rising edge of the PWM output (SOUT) signal and
XN is LOW
and
ƒ Falling edge of the DET signal and XN is LOW
During the PWM input turn-off, SOUT is commanded
off faster than the turn-on period. This can be seen in Fig.
21 and Fig. 22 by the 300ns delay applied to the SOUT
turn-on compared to the 100ns delay time applied to
SOUT turn-off. Since PWM controllers modulate the off
time (trailing-edge modulation), the delay applied to the
trailing edge needs to be as small as possible so that
accurate control of the power stage can be maintained.
On the other hand, the SOUT trailing-edge delay must
be long enough that the rising edge of XN (triggered by
SIN falling edge) occurs prior to the falling edge of
SOUT. When the primary-side PWM MOSFETs are
turned off, the transformer primary voltage begins to
reverse as the winding voltage decreases to negative VIN.
During this transformer reset period, the dv/dt transition
can vary as a function of output load current. The
optimum turn-on point of the freewheeling SR MOSFET
is just after the transformer secondary winding voltage
Fairchild Semiconductor Power Seminar 2010-2011
has decreased lower than VOUT. This optimal turn-on
point is determined by the DET signal, which is used to
monitor the clamped primary-side transformer winding
voltage. During heavy-load operation, the dv/dt seen by
the DET pin increases so it is possible for XP to trigger
while XN is still HIGH. If XN is still HIGH while DET
has transitioned LOW, then XP is not allowed to trigger
until XN transitions LOW. Triggering XP this way
prevents SR shoot-through by ensuring that XP and XN
can never overlap. Conversely, during light-load
operation, the dv/dt seen at the DET pin decreases to the
point that the DET falling edge comes after XN falls to
zero. In this case, the XP signal is triggered by the DET
voltage after a 50ns delay. Since the XP and XN pulses
are not the “real” PWM signal, they cannot be used to
drive the SR MOSFETs directly. Instead, XP and XN
are used as inputs and decoded by the FAN6206
secondary-side SR controller and driver. The primaryside FAN6210 assumes CCM operation for the power
stage; however, during DCM operation, the inductor
current can be allowed to go negative. Since secondaryside information is not transferred to the primary, the
FAN6210 has no way to determine DCM operation.
Under CCM operation, the gate drive timing is
determined by SP (XP) and SN (XN), with operation as
described by the timing diagrams of Fig. 21 and Fig. 22.
Since SN is triggered by the FAN6210 PWM input
signal, the freewheeling SR MOSFET cannot be turned
off before the output inductor current reaches zero. For
DCM operation negative inductor current is allowed to
flow in the secondary SRs. Turning on the control SR
MOSFET under this condition can result in exceedingly
high VDS ringing during DCM operation. In the best case,
this ringing might be controlled using a dissipative RC
snubber at the cost of a slight penalty in efficiency. In
the worst case, the voltage could ring high enough to
exceed the maximum breakdown voltage of the SR
MOSFET. To emulate DCM diode rectification, the
freewheeling SR MOSFET should ideally be turned off
the instant the output inductor current reaches 0A,
preventing negative current flow.
By sensing the drain-source voltage of each SR, as
shown in Fig. 20, FAN6206 introduces a timing-control
technique called linear predict control (LPC) to
accurately determine the optimal freewheeling SR
11
MOSFET turn-off time during DCM operation. Fig. 23
shows the LPC timing diagram relative to the FAN6210
primary-side signals when operating in DCM.
The drain-source voltage divider, RatioLPC2, plays a
much different role for the turn-off of the freewheeling
SR MOSFET. The voltage present on LPC2 is detected
by an internal voltage-dependant current source, iCHG,
used to charge a fixed capacitor. However, the discharge
current, iDISCHG, is controlled by the FAN6206 bias
voltage on VDD, but is constant. The value of iCHG
results in an applied dv/dt used to precisely determine
the turn-off timing for the freewheeling SR MOSFET
relative to RatioLPC2 and ILO. The relationship between
RatioLPC2 and the freewheeling SR MOSFET gate drive
is shown in Fig. 24.
Fig. 23. FAN6206 DCM timing diagram.
When operating in DCM, the current through the
freewheeling SR decreases to zero prior to the SN (XN)
turn-off command. To prevent negative current flow, the
drain-source voltage dividers R1, R2 for the
freewheeling SR and R3, R4 for the control SR must be
properly set to sense the voltage at the correct LPC
threshold. The voltage divider scaling for LPC1 and
LPC2 is defined as:
8 9 LPC is not necessary for the control SR because it is
always turned off by the SN (XN) signal. Nonetheless,
the control SR voltage divider, R3, R4 is used to
determine the state of the drain-source voltage according
to an internal 2V threshold used by LPC1. LPC1 being
less than 2V and SP (XP) rising edge are the two
required conditions for triggering the turn-on of the SR1
gate drive signal. It is therefore recommended to set the
R3, R4 voltage divider within the range of 3V to 5V
according to Equation (10):
3
5 10 where RatioLPC1 is given by Equation (8), VIN is the
forward converter input voltage, and n is the transformer
turns ratio.
Fairchild Semiconductor Power Seminar 2010-2011
Fig. 24. LPC2 control of freewheeling SR MOSFET turn-off during
DCM operation.
For proper operation and control of the freewheeling
MOSFET, the LPC2 pin voltage is normalized to the
nominal output voltage, 1/VO. Therefore, the scaling
factor of RatioLPC2 should be set according to:
.
11 For example, if VO=12V and R2 is chosen as 10kΩ,
R1 would be approximately 105kΩ, giving
RatioLPC2=0.0869. Keeping R2 as 10kΩ, the value of R1
can be adjusted slightly to modify the exact turn-off of
the freewheeling SR. As shown in Fig. 24, increasing R1
lowers the value of RatioLPC2 and turns off the
freewheeling SR sooner relative to the start of DCM
operation. Conversely, decreasing R1 increases the value
of RatioLPC2 and turns off the freewheeling SR later.
Setting the value of R1 during minimum load operation
prevents negative current flow in the freewheeling SR
during deep DCM operation. Once the load current is
increased and CCM operation is resumed, LPC1 and
12
LPC2 are used to sense winding information and the SR
gate drive timing is taken over by SP (XP) and SN (XN).
Control-driven primary-side SR triggering is
compatible with any of the forward converter reset
methods in Fig. 10. Although the fixed internal delay
times are optimized for converter operation around
100kHz, the timing accuracy is completely controlled by
the FAN6210 and FAN6206, eliminating the need to set
RC timing delays such as those shown in Fig. 15 and Fig.
16a. For operation above 100kHz, extended body diode
conduction times can be expected, warranting a
SyncFET MOSFET or an additional Schottky rectifier in
parallel with the freewheeling SR. The solution is
flexible since it can be employed using any single-ended
PWM controller. A final noteworthy feature of the
FAN6210 is the ability to disable the SR turn-on trigger
signal, XP, when the PWM input duty cycle is less than
10% during DCM operation. This type of “green-mode”
functionality helps maintain higher light-load efficiency
by reducing power dissipation associated with SR gate
charge losses. During green-mode operation, the output
load current flows through the SR body diodes until the
duty cycle is commanded greater than 10%.
V.
The two-level Vbulk is derived from the PFC section of
the FAN4801 PFC/PWM combo controller. The typical
voltage level for Vbulk is 380V, but under low-line and
light-load conditions, the PFC output voltage, Vbulk, is
decreased to 310V to maintain higher light-load
efficiency. The switching frequency, fS, is 65kHz for the
PFC and PWM stages. The transformer turns ratio of
TX1 is 11, hence the VDS voltage during PWM turn-on
period is 380/11=34.55V. In accordance with Equation
(11), RatioLPC2 = 1/11.5 is determined. The scaled
voltage on LPC2 is 3V. From Equation (10), the plateau
voltage on LPC1 during the PWM turn-off period should
be between 3V~5V. Selecting RatioLPC1 = 1/7.8, the
scaled voltage from Equation (10) is 4.43V. Final LPC
resistor divider values are chosen as R9 = 10kΩ, R8 =
105kΩ, R7 = 10kΩ, and R6 = 68kΩ. During low-line
and light-load operation when Vbulk is decreased to 310V,
the scaled voltage on LPC2 is 2.45V, while LPC1 is
3.61V. Based on the specifications in Table 1 and the
design guidelines discussed herein for configuring the
FAN6210 primary-side SR trigger controller and
FAN6206 SR controller, the schematic shown in Fig. 25
was built and tested with measured results shown below.
APPLICATION EXAMPLE,
CONTROL-DRIVEN SR, PRIMARYSIDE TRIGGERING
To validate the operation of the proposed controldriven SR technique, a two-switch forward converter
was designed and tested according to the specifications
in Table 1.
TABLE 1.
SYSTEM-LEVEL SPECIFICATIONS
Input
Input Voltage Range
90~264VAC
Line Frequency Range
47~63Hz
Output Voltage of PFC Stage (Vbulk)
310V / 380V
Output
Output Voltage (Vo)
12V
Output Power (Po)
300W
Output Current (Io)
25A
Typical Switching Frequency (fs)
65kHz
Fairchild Semiconductor Power Seminar 2010-2011
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Fig. 25. LPC2 control-driven SR primary triggering application test circuit.
Fairchild Semiconductor Power Seminar 2010-2011
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TABLE 2.
BILL OF MATERIALS (BOM), COMPONENTS USED TO TEST SCHEMATIC SHOWN IN FIGURE. 17
Part
Value
Note
Resistor
Part
Value
Note
Inductor
R1
8.2kΩ
1/8W
L1
73µH
R2
10kΩ
1/4W
L2
1.8µH
R6
68kΩ
1/8W
Diode
R7
10kΩ
1/8W
D1
FR107
R8
105kΩ
1/8W
D2
Zener Diode/5.6V
R9
10kΩ
1/8W
D7
1N4148
R10
10kΩ
1/8W
D8
1N4148
R11
10kΩ
1/8W
D9
UF1007
R12
4.7Ω
1/8W
D10
UF1007
R13
4.7Ω
1/8W
MOSFET
R14
10kΩ
1/8W
Q1
FDP5800
R15
10kΩ
1/8W
Q2
FDP5800
R16
0.15Ω
2W
Q3
FCP20N60
R17
3kΩ
1/8W
Q4
FCP20N60
R18
38.3kΩ
1/8W
Transformer
R19
10kΩ
1/8W
TX1
66:6
Primary 20mH
R20
1kΩ
1/8W
TX2
1:1
Primary 160µH
TX3
1:1.2
Primary 300µH
Capacitor
C1
100nF
50V
IC
C2
100nF
50V
U1
FAN6210
C3
470pF
25V
U2
FAN6206
C4
100nF
50V
U3
PC817
C5
270µF
450V
U4
TL431
C6
1µF
50V
C7
3300µF
16V
C8
3300µF
16V
C9
4.7nF/250V
Y-Capacitor
Fairchild Semiconductor Power Seminar 2010-2011
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VI.
CONTROL-DRIVEN SR, PRIMARY-SIDE TRIGGERING, MEASURED RESULTS
Fig. 26. SR gates controlled by SP and SN during CCM operation.
Fig. 27. PWM input FAN6210 100ns falling-edge delay.
Fig. 28. Freewheeling SR is turned off by LPC during DCM operation.
Fig. 29. CCM 500ns leading-edge body diode conduction.
Fig. 30. PWM input FAN6210 300ns rising-edge delay.
Fig. 31. CCM 400ns trailing-edge body diode conduction.
Fairchild Semiconductor Power Seminar 2010-2011
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Fig. 32. 0A→10A dynamic load step response.
Fig. 33. VOUT startup, freewheeling SR current commutation.
Fig. 34. 10A→0A dynamic load step response.
Fig. 35. IOUT short circuit, controlled SR turn-off.
Fig. 36. VOUT startup, SR gate drives begin switching.
Fig. 37. Green mode, D<10%, DCM, SRs off.
Fairchild Semiconductor Power Seminar 2010-2011
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operation. System operating conditions such as startup,
SR Efficiency Comparison
shut-down, load transient, short-circuit, and over-current
(115VAC Input, 12VDC Output, 300W, 12V/25A Output)
95%
are just a few dynamic test conditions that should be
Primary‐Side Trigger Control‐Driven SR (FDP5800)
closely monitored. One of the most important dynamic
Schottky Rectifiers (FYP2006DN)
features of a control-driven SR solution is that the SR
Efficiency (%)
90%
gate drives never actively cross-conduct. The waveforms
shown in Fig. 32 through Fig. 36 capture some of the
FAN6210 / FAN6206 dynamic characteristics. Fig. 32
85%
and Fig. 34 focus on the control SR and freewheeling SR
gate drive signal during a 10A load transient,
80%
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Output Power (%) Fig. 38. Primary-side trigger control-driven efficiency improvement.
Fig. 26 through Fig. 31 show the steady-state
performance of the FAN6210 / FAN6206 control-driven
SR solution. The typical steady-state SR driving signals
developed from the FAN6206 SR control signals, SP
(XP) and SN (XN), under CCM operation are shown in
Fig. 26. Fig. 28 shows the freewheeling SR being turned
on by SP (XP), but turned off early by LPC under DCM
operation. The control SR is shown turning on by the SP
(XP) rising edge and turning off by the SN (XN) rising
edge. The rising and falling edge PWM delays are
highlighted in Fig. 30 and Fig. 27 where it can be
verified that the rising-edge delay is 300ns compared to
the 100ns falling-edge delay. During CCM full-load
operation, the SR body diode conduction time was
measured as 500ns on the leading edge, shown in Fig. 29
and 400ns on the trailing edge as shown in Fig. 31. For a
converter switching at 65kHz, 900ns of total body diode
conduction represents approximately 5% of the total
switching period. The overall converter efficiency
benefits compared to Schottky diode rectification are
greater than 2% for all load conditions above 20%, as
highlighted in Fig. 38.
When evaluating any control-driven SR solution,
dynamic performance is as important as steady-state
Fairchild Semiconductor Power Seminar 2010-2011
highlighting that the gate drives remain controlled
without any overlap or indication of shoot-through
current. The output voltage during startup is shown in
Fig. 33; where, at approximately VOUT=8.8V, the control
SR begins switching first, followed by the freewheeling
SR after several switching cycles. During the time that
VOUT<8V, the output load current flows through the SR
body diodes until the FAN6206 turn-on threshold is
reached. As the SR body diodes initially handle the
output rectification, voltage is apparent on the drainsource of each SR. At the moment the freewheeling SR
turns on for the first time, special attention should be
paid to the drain-source voltage, watching for any
excessive voltage spikes. As seen in Fig. 36, the initial
gate signals for the freewheeling SR are highlighted
along with the drain-source voltage of each SR. The
switching action is seamless, with no overlapping drain
signals or voltage spikes, as the current is smoothly
commutated from the body diode to the channel
resistance. Finally, one of the more problematic dynamic
SR tests is output current, short-circuit overload. At 64A,
the applied short-circuit load current shown in Fig. 35 is
more than 250% over the maximum rated converter load
current. As the output voltage begins to drop, the
freewheeling SR is monitored and is shown to stop
switching when VOUT<7.5V. An enlarged view indicates
that the freewheeling SR stops switching first and the
control SR remains switching for six additional pulses.
18
The control SR always switches just before and just
when considering RC delay tolerances or combinational
beyond the freewheeling SR, assuring the load is
logic that must be introduced to assure proper SR timing.
Using any single-ended PWM input; a simple control-
controlled during startup and shutdown.
Another important operating mode to consider is light-
driven primary-side SR triggering technique was
load DCM operation where the duty cycle is decreasing.
introduced and validated. The solution works with any
FAN6210’s green-mode prevents SR turn-on by
forward converter reset method, produces regulated gate
disabling the XP (SP) control signal whenever the
drive, uses LPC to avoid negative SR current flow,
converter duty cycle is less than 10%. During green-
offers green-mode operation to improve light-load
mode operation, XN (SN) SR turn-off signals are
efficiency, and accurately resolves primary-to-secondary
generated, but are meaningless since the SRs cannot
timing delay issues without the use of external RC delay
turn-on in the absence of XP (SP). As DCM current
circuits. The circuit was tested and validated in a 300W
flows through the SR body diodes, the drain-source
off-line two-switch forward converter application. Test
voltage is shown in Fig. 37 for each SR under the
results were presented proving the solution to be robust
condition that D=7.8%. As the converter load is
and reliable under steady state and dynamic test
increased from DCM toward CCM operation and the
conditions. Finally, an efficiency comparison was made
duty cycle increases above 10%, XN (SN) is reinitiated
replacing the SR MOSFETs with Schottky rectifiers.
and the control SR resumes switching followed by the
The results presented in Fig. 38 show a greater than 2%
freewheeling SR.
overall improvement for 20%<IOUT<100% when the
VII.
CONCLUSION
The efficiency and performance benefits gained from
replacing Schottky diode rectifiers with SR MOSFETs
primary trigger control driven SR technique was used.
REFERENCES
[1]
Controller
in forward converters were studied. Many of the same
challenges associated with non-isolated synchronous
isolation, adding a level of SR timing complexity.
for
Dual
Forward
Converter”,
Datasheet,
Fairchild
Semiconductor, March 2010.
[2]
“FAN6206
—
Highly
Integrated
Dual-Channel
Synchronous
Rectification Controller for Dual-Forward Converter”, Datasheet,
buck converters apply to forward converters; however, a
power transformer is necessary for primary-to-secondary
“FAN6210 — Primary-Side Synchronous Rectifier (SR) Trigger
Fairchild Semiconductor, April 2010.
[3]
“AN-6206 — Primary-Side Synchronous Rectifier (SR) Trigger Solution
for Dual-Forward Converter”, Fairchild Semiconductor, April 2010.
Several methods of developing SR gate drive signals
Steve Mappus is a principal Systems Engineer
were discussed. For certain applications, self-driven SR
Conversion group located in Bedford, NH, USA. In his
working
in
Fairchild
Semiconductor’s
Power
current role, he is responsible for new product
is a simple approach yielding significant efficiency
development of power-supply control and MOSFET
improvements, but with limitations. Control-driven SR
gate drive ICs. He has more than 20 years of power
methods overcome many of the obstacles associated
supply design experience, including ten years designing military and
with self-driven SR, but developing proper timing and
years working in the power management semiconductor business specializing
commercial power systems for avionic applications. He has spent the last ten
gate drive are necessary for successful implementation.
in systems and applications engineering. His areas of interest include high-
In some cases, control-driven SR schemes are devised
rectification, high-frequency power conversion, and power factor correction.
power
converter
topologies,
soft-switching
converters,
synchronous
using general purpose, low-side MOSFET gate drivers;
however, this SR drive technique can be troublesome
Fairchild Semiconductor Power Seminar 2010-2011
19