Proc. of Int. Conf. on Advances in Electrical & Electronics 2010
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#2
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Department of Electronics and Communication, National Institute of Technology, Hamirpur
Hamirpur (H.P)-177005, India
1 rintu2008@gmail.com
2 ranka.deepesh@gmail.com
3 kamleshnhr@gmail.com
4 ashwani_paper@yahoo.com
Abstract—A new CMOS buffer without short-circuit power consumption is proposed. In this work, the gate-driving signal of the output pull-up (pull-down) transistor is fed back to the output pull-down (pull-up) transistor to get tri-state output tapering factor and the number of stages of a tapered buffer system; these parameters are the two primary variables in the design of tapered buffers. An application-specific momentarily, eliminating the short-circuit power tapering factor and number of stages of a tapered buffer system necessary to drive a wide range of capacitive loads consumption. The TSPICE simulations are used to verify the operation of the buffer. It is observed that the power-delay product of the proposed buffer is about 15% smaller than conventional tapered CMOS buffer.
Keywords— CMOS buffer, short-circuit power consumption,
MOS.
[14], [15], [16]. All the work focussed so far includes the short circuit power consumption. This issue is handled in our works. A conventional tapered CMOS buffer, shown in
Fig.1, consumes both the dynamic switching power and short-circuits power due to simultaneous turn-on of the
I.
INTRODUCTION pull-up/pull-down transistors [17], [18], [19], [20] as
I N CMOS integrated circuits, large capacitive loads are often encountered [1], [2], [3]. These large loads occur both on-chip, where high, localized fan-out and long global interconnect lines are common, and off chip, where highly capacitive chip-to-chip communication lines exit [4], [5],
[6]. In order to drive these large capacitive loads at high speeds, buffer circuits are required which must quickly source and sink relatively large currents while not degrading the performance of previous stages [7].With the high integration level of CMOS, the capacitive load of periodic signals such as clock has become very large. With such a large capacitive load, driving circuits consume a illustrated in Fig.2. Short-circuit power consumption can be eliminated by tri-stating the output node momentarily before every output signal transition. In this work, we concentrated on the simulation part of the without short circuit power consumption and working on the analytical approach in our subsequent work. relatively large portion of the total power of a VLSI [8].
The power consumption of a CMOS buffer driving a capacitive load consists of dynamic switching power and short-circuits power. While the switching-power consumption is unavoidable to drive a capacitive load, short-circuit power is a waste of current and should be minimized or even eliminated for low-power operation [1].
The buffer provides a high impedance input, so as not to load down the logic/ registers and high current to quickly charge (discharge) the large capacitive load. Thus, the buffer isolates the logic/registers from the load, amplifying the signal along the way [9], [10].
In past, many different approaches [4], [8], [11], [12], [13]
Fig. 1 Design of tapered CMOS buffer to tapered buffer design have been described in the literature, focusing on a variety of performance aspects.
The most commonly addressed criteria in tapered buffer design are propagation delay, power dissipation and physical area. Analytic expressions to determine the
Fig.2 Timing diagram of tapered CMOS buffer
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© 2010 ACEEE
DOI: 02.AEE.2010.01.111

Proc. of Int. Conf. on Advances in Electrical & Electronics 2010
The rest of the paper is organized as follows. In Section
II, schematic and functionality of the proposed buffer is presented. The results obtained are discussed in Section III.
Finally, concluding remarks are offered in Section IV.
II.
S CHEMATIC AND FUNCTIONALITY OF PROPOSED BUFFER
A new CMOS buffer without short-circuit power consumption is proposed. The output pull-up and pulldown transistors are driven by separate driving signals generated so the pull-up and pull-down transistors do not turn on simultaneously. The schematic and timing diagrams of the proposed CMOS buffer are shown in Fig.3 and Fig.4 respectively.
A.
Functioning of proposed buffer
The gate driving signal N
1
(N
2
) of the output pull-up
(pull-down) transistor is fed back to the output pull-down
(pull-up) transistor to get tri-state output momentarily, eliminating the short-circuit power consumption. The logic states of the output stage driver change only once for each output transition in the proposed buffer as opposed to twice in the FS [11] and CFS [17] buffer. Since the gate driving signals are fed back instead of the output signal itself, the feedback delay is independent of the output capacitive load, making the optimization of the circuit much easier. The pull-up and pull-down operations are explained respectively in the following.
Fig.4 Timing diagram of tapered CMOS buffer
When the input signals IN rises from 0 to V
DD
, the internal node N
2
falls from V
DD
to zero, turning off the output pull-down transistor M
2
. Then, the node N
4
rises from zero to V
DD
and after some delay, the node N
1
falls from V
DD
to zero. Now, the output pull-up transistor M
1
is turned on and the output voltage begins to rise from zero to
V
DD
. Since the node N
2
is driven to zero before the node
N
1
, the pull-down transistor M
2
is turned off before the pull-up transistor M
1
is turned on. Therefore, there is no period when both the pull-up and pull-down transistors are turned on simultaneously and thus no short-circuit power consumption.When the input signal IN falls from V
DD
to 0, the node N
1
is driven to V
DD
, turning off the output pull-up transistor M
1
. Then, the node N
3
falls from V
DD
to zero and after some delay, the node N
2
rises from zero to V
DD
. Now, the output pull-down transistor M
2
is turned on and the output voltage begins to fall from V
DD
to zero. Since the node N
1
is driven to V
DD
before the node N
2
, there is no period when both the pull-up and pull-down transistors are turned on simultaneously and thus no short-circuit power consumption in this case, as well.
IN M
3
N
1
III.
R ESULTS AND D ISCUSSION
M
1
N
4
M
4
N
3
M
5
M
6
M
7
M
8
N
2
M
2
C load
OUT
Fig.3 Proposed CMOS buffer without short-circuit power consumption .
The proposed buffer is simulated in TSPICE simulator for two different technology nodes i.e. 180 nm and 250 nm.
To see the clear cut impact of short circuit power, we have chosen 180 nm and 250 nm technology nodes. Fig. 5 and
Fig. 7 plot the propagation delay vs. load capacitance at
180 nm and 250 nm technology nodes respectively. It is observed from the Fig. 5 and Fig.7 that propagation delay increases as the load capacitance increases. The propagation delay is significant in case of proposed buffer design as compared to the conventional tapered for a given load. The large no of transistors used in proposed buffer introduces large internal parasitic capacitance which require large time to charge and discharge thereby increasing the propagation delay.
213
© 2010 ACEEE
DOI: 02.AEE.2010.01.111

Proc. of Int. Conf. on Advances in Electrical & Electronics 2010
Fig. 6 and Fig. 8 plot the average power vs. load capacitance at 180 nm and 250 nm technology nodes respectively. It is reported in Fig. 6 and Fig. 8 that power consumption is significantly lower in case of proposed buffer due to the absence of short circuit power consumption component. However it is shown in Fig. 9 that power delay product is improved in a proposed buffer.
This means that extent of reduction in power consumption is more than the extent of delay increment in proposed buffer. Thus proposed design is suitable for the application where large capacitive load is encountered and low power consumption is required.
22.5
23.2
22.8
22.4
22.0
21.6
Proposed
Taper
21.2
0 20 40 60
Load Capacitance(ff)
80 100
Fig.7
Propagation delay vs. load capacitance at 250 nm technology node.
22.2
500
21.9
Taper
Proposed
400
21.6
Proposed
Taper
300
21.3
0 20 40 60
Load Capacitance(ff)
80 100
200
Fig.5 Propagation delay vs. load capacitance at 180 nm technology node.
100
100
80
60
40
20
Taper
Proposed
0
0 20 40 60
Load Capacitance(ff)
80 100
Fig.6 Average power dissipation vs. load capacitance at 180 nm technology node.
0
0 20 40 60
Load Capacitance(ff)
80 100
Fig.8 Average power dissipation vs. load capacitance at 250 nm technology node.
© 2010 ACEEE
DOI: 02.AEE.2010.01.111
214

Proc. of Int. Conf. on Advances in Electrical & Electronics 2010
10000
8000
6000
4000
2000
0
0 20
Fig.9 Power delay product (PDP) vs. load capacitance at 180 nm and 250 nm technology nodes.
Fig. 9 plots the power delay product (PDP) vs. load capacitance at 180 nm and 250 nm technology nodes.
It is found that proposed CMOS buffer provides at least
15% less power delay product (PDP) than conventional tapered CMOS buffer because proposed buffer has no short-circuit power consumption. Delay is higher in proposed CMOS buffer than conventional tapered CMOS buffer. As conventional tapered CMOS buffer takes less area than proposed CMOS buffer, so conventional tapered
CMOS buffer is a good choice for delay centric design and proposed buffer is suitable for power aware environment.
IV.
C ONCLUSION
A new CMOS buffer has been proposed which has no short-circuit power consumption. The output pull-up and pull-down transistors are driven by separate driving stages which ensure pull-up and pull-down transistors do not turn on simultaneously. The TSPICE simulation results show about 15% improvement in the power-delay product compared to a conventional tapered CMOS buffer, and thus the proposed buffer is suitable for low-power application where large capacitive load is encountered.
R
40 60
Load Capacitance(ff)
80
EFERENCES
Proposed 180nm
Proposed 250nm
Taper 180nm
Taper 250nm
100
[1] H. J. M. Veendrick, "Short-circuit dissipation of static
CMOS circuitry and its impact on the design of buffer circuits,” IEEE J. Solid-State Circuits , vol. SC-19, no. 4, pp.
468-473, Aug. 1984.
[2] H. C. Lin and L.W. Linholm, "An optimized output stage for
MOS integrated circuits,” IEEE J. Solid-State Circuits , vol.
SC-1O, no. 2, pp. 106-109, Apr. 1975.
[3] R. C. Jaeger, "Comments on 'An optimized output stage for
MOS integrated circuits',” IEEE J. Solid-State Circuits , vol.
SC-1O, no. 3, pp. 185-186, June 1975.
[4] N. Hedenstiem and K. O. Jeppson, "Comments on the optimum CMOS tapered buffer problem," IEEE J. Solid-
State Circuits , vol. 29, no.2, pp. 155-/59, Feb. 1994.
[5] S. Dhar and M. A. Franklin, "Optimum buffer circuits for driving long uniform lines," IEEE J. Solid-State Circuits , vol. 26, no.1, pp. 32-40, Jan. 1991.
[6] B. S. Cherkauer and E. G. Friedman, “A Unified Design
Methodology for CMOS Tapered Buffers,” IEEE Trans. on
VLSI Systems , vol. 3, No. 1, pp. 99-111, Mar. 1995 .
[7] C. yoo, “A CMOS Buffer without Short-Circuit Power
Consumption,” IEEE Trans. Circuit Syst. II , vol. 47, No. 9, pp. 935-937, Sep. 2000.
[8] N. Li, F. Haviland, and A. Tuszynski, “A CMOS Tapered
Buffer,” IEEE J. Solid-State Circuits , vol. 25, pp. 1005–
1008, Aug. 1990.
[9] L. A. Glasser and L. P. J. Hoyte, "Delay and power optimization in VLSI circuits," in Proc. ACM/IEEE Design
Automat. Conf.
, June 1984, pp. 529-535.
[10] H. B. Bakoglu and J. D. Meindl, "Optimal interconnection circuits for VLSI," IEEE Trans. Electron Devices , vol. ED-
32, no. 5, pp. 903-909, May 1985.
[11] H. Y. Huang and Y. H. Chu, “Feedback-Controlled Split-
Path CMOS Clock Buffer,” Proc. Int. Symp. Circuits and
Systems , vol. 4, pp. 300–303, 1996.
[12] K. Y. Khoo and A. N. Wilson Jr., “Low Power CMOS Clock
Buffer,” Proc. Int. Symp.Circuits and Systems , vol. 4, pp.
355–358, 1994.
[13] S. M. Kang and Y. Leblebici , “CMOS Digital Integrated
Circuits” TMH Edition 2003.
[14] F. S. Lai, "A generalized algorithm for CMOS circuit delay, power, and area optimization," Solid-State Electron.
, vol.
31, no. II, pp. 1619-1627, Nov. 1988.
[15] B. S. Cherkauer and E. G. Friedman, "Unification of speed, power, area, and reliability in CMOS tapered buffer design," in Proc. IEEE Int. Symp. Circuits, Syst.
, May 1994, pp.
4.111-4.114.
[16] C. M. Lee and H. Soukup, "An algorithm for CMOS timing and area optimization," IEEE J. Solid-State Circuits , vol.
SC-19, no. 5, pp. 781-787, Oct. 1984.
[17] K. H. Cheng, W. B. Yang, and H. Y. Huang, “The Charge-
Transfer Feedback-Controlled Split-Path CMOS Buffer”
IEEE Trans. Circuits Syst. II , vol. 46, No. 3, pp. 346-348,
Mar. 1999.
[18] N. Hedenstiema and K. O. Jeppson, "CMOS circuit speed and buffer optimization," IEEE Trans. Comput.-Aided
Design , vol. CAD-6, no. 2, pp. 270-281, Mar. 1987.
[19] H. Shichman and D. A. Hodges, "Modeling and simulation of insulated gate field-effect transistor switching circuits,"
IEEE J. Solid-State Circuits , vol. SC-3, no. 3, pp. 285-289,
Sept. 1968.
[20] Y. Leblebici and S. M. Kang, "Modeling and simulation of hot carrier-induced device degradation in MOS circuits,"
IEEE J. Solid-State Circuits , vol. 28, no. 5, pp. 585-595,
May 1993
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