EECS 42 Intro. electronics for CS Fall 2001
Lecture 24: 11/28/01 A.R. Neureuther
Version Date 12/01/01
Lecture 24
CMOS Capacitance and Circuit Delay
A)
B)
C)
D)
E)
CMOS Structure and Capacitance
Gate and Source Drain Capacitance Model
Cascade Inverter Delay
Capacitance from Logic Function
Fan-Out and Logic Delay
Reading: Schwarz and Oldham, pp. 518-526, and
lectures 16-19.
Copyright 2001, Regents of University of California
EECS 42 Intro. electronics for CS Fall 2001
Lecture 24: 11/28/01 A.R. Neureuther
Version Date 12/01/01
Dynamic Performance: Add Capacitances
ε WL
CG = Cox × W × L = ox
t ox
C SD = C junction × W × 4 Lmin + C perimeter × W
VS
VG
gate
Area of Gate
W
source
VD
Bottom
Sidewall
L
drain
Capacitance CG is between gate and the underlying channel, which
is connected to the source, CGS = CG and hence is modeled as
capacitance to a.c. ground.
Capacitance CSD has a bottom and out-side perimeter between the
source or drain and the underlying substrate which is connected to
a.c. ground. There is also a gate perimeter component for which
there is a 2X magnifying (Miller) effect on the S/D side because the
gate swings the opposite direction of the S/D.
Copyright 2001, Regents of University of California
EECS 42 Intro. electronics for CS Fall 2001
Lecture 24: 11/28/01 A.R. Neureuther
Version Date 12/01/01
Gate Capacitance Model
ε WL
CG = Cox × W × L = ox
t ox Dielectric Constant for SiO
Cox
(
)
ε ox
8.85 x10 −14 F / cm (3.9 )
−7
2
x
F
cm
5
.
75
10
/
=
=
=
t ox
6 x10 −7 cm
L = 0.25µm
(
W = 0.375µm
)
CG = 5.75 x10 −7 F / cm 2 × 0.375 x10 −4 × 0.25 x10 −4 = 0.54 fF
EE42 Simplified CG model:
CG/MS = 0.4fF/MS (ie. 0.4 fF per Minimum Square of gate layout)
Example For Gates with the minimum length of 0.25 µm:
(W/L)n = 0.375/0.25 = 1.5 has 1.5 MS and has CG = 0.6 fF.
(W/L)p = 0.75/0.25 = 3.0 has 3.0 MS and has CG = 1.2 fF.
Copyright 2001, Regents of University of California
Note: CG is
proportional
to (W/L)
2
EECS 42 Intro. electronics for CS Fall 2001
Lecture 24: 11/28/01 A.R. Neureuther
Version Date 12/01/01
Source/Drain Capacitance Model
C SD = C junction × W × 4 Lmin + C perimeter × W
Accurately evaluating CSD involves modeling the advanced
physics of junctions and is considered in somewhat more
detail in EECS 141.
CSD is generally proportional to W.
EE42 Simplified CG model:
CSD = 0.4fF/LMIN (ie. 0.4 fF per Minimum 0.25µm Feature length)
Example: (W/L)n = 0.375/0.25, => 1.5L with CSD = 0.6 fF.
Example: (W/L)p = 0.75/0.25 => 3.0L with CG = 1.2 fF.
Copyright 2001, Regents of University of California
EECS 42 Intro. electronics for CS Fall 2001
Lecture 24: 11/28/01 A.R. Neureuther
Version Date 12/01/01
The CMOS Inverter with Parasitic capacitances
V
Symbolic circuit
DD
S
Model
R
C
V
in
p
Gp
DD
G
v
p
v
out
v
p
D
v
in
D
G
MODEL
n
p
n
C
Gn
C
R
CDn
n
S
Note that the switches are NOT
independent , in fact they are “ganged”
Copyright 2001, Regents of University of California
out
n
Dp
EECS 42 Intro. electronics for CS Fall 2001
Lecture 24: 11/28/01 A.R. Neureuther
Version Date 12/01/01
Gate-Delay Analysis -- Identify key Components
vin1
Basic case: one
inverter driving
another
vin1
1
vout1
2
V
VDD
MP2
vout2
vin1
MP4
vout1
= vin2
+
-
MN1
Suppose Vin1 goes from high to low.
vout1
vout2
vout2
MN3
MP2 turns on and MN1 turns off.
Then Vout1 goes from low to high (but a little bit later … i.e. delayed ).
Of course Vin2 is the same as Vout1 .
Thus Vout2 goes from high to low (delayed even more from
the input Vin1).
Copyright 2001, Regents of University of California
t
EECS 42 Intro. electronics for CS Fall 2001
Lecture 24: 11/28/01 A.R. Neureuther
Version Date 12/01/01
“Cascaded” CMOS Inverters
Note that there are no resistors, capacitors, inductors in a
CMOS circuit -- there are only NMOS and PMOS transistors.
The output of stage 1 must charge the Source/Drain capacitances of
the first stage and the gate capacitances of the second stage.
That is CDn and CDp of the first stage and CGn and CGp of the second
stage.
VDD
vout1 =
vin1
vout2
vin2
CLOAD = CDn + CDp + CGn + CGp
CLOAD
LOGIC STAGE N
STAGE N +1
Copyright 2001, Regents of University of California
EECS 42 Intro. electronics for CS Fall 2001
Lecture 24: 11/28/01 A.R. Neureuther
Version Date 12/01/01
Typical Capacitance Values:
(W/L) ratios
VDD
Consider “0.25µm technology”
with a typical NMOS device
v
vin1
0.25 X 0.375 µm as pull-down
1.5
3.0 v
out1 =
1.5
vout2
vin2
CLOAD
and 0.25 X 0.75 pull-up
LOGIC STAGE N
3.0
STAGE N +1
CLOAD = CDn + CDp + CGn + CGp
CLOAD = (1.5 + 3.0 + 1.5 +3.0)(0.4fF) =
(9)(0.4fF) = 3.6fF
Copyright 2001, Regents of University of California
EECS 42 Intro. electronics for CS Fall 2001
Lecture 24: 11/28/01 A.R. Neureuther
Version Date 12/01/01
ID
Resistance Model
for Switching
ID
RDN
D
IDS
G
N Ch
S
The circuit symbol
From IDS = CdV/dt we have
∆t = C∆V/ IDS = C VDD/ 2 IDS
But if we had an RC discharge
∆t = 0.69RC so the effective
resistance, RDN ,= ∆t /0.69C
= VDD/(0.69 X 2 IDS ) = .72 VDD / IDS
So we use
R DN
VDS
VDD/2
VDD
(3/4)VDD
 3 V
≈   DD
 4  I DS
Copyright 2001, Regents of University of California
D
RDN
G
S
Electrical Model
EECS 42 Intro. electronics for CS Fall 2001
Lecture 24: 11/28/01 A.R. Neureuther
Version Date 12/01/01
Resistance Model for Switching
For the 0.25 µm technology with VDD =2.5V
For Wp = 0. 75µm
R DP
 3  VDD  3  2.5V
= 11.87kΩ ≈ 12kΩ
= 
≈ 
 4  I DS  4  158µA
D
For Wn = 0.375µm
R DN
 3  VDD  3  2.5V
= 9.57kΩ ≈ 10kΩ
= 
≈ 
 4  I DS  4  196µA
RDN
G
S
Electrical Model
Copyright 2001, Regents of University of California
EECS 42 Intro. electronics for CS Fall 2001
Lecture 24: 11/28/01 A.R. Neureuther
Version Date 12/01/01
Inverter Propagation Delay
Discharge (pull-down)
VDD
VDD
VOUT
VIN =
Vdd
COUT = 3.6fF
VOUT
VIN =
Vdd
RD
∆t = 0.69RDNCLOAD = 0.69(10kΩ)(3.6fF) = 25 ps
Discharge (pull-up)
∆t = 0.69RDPCLOAD = 0.69(12kΩ)(3.6fF) = 30 ps
Copyright 2001, Regents of University of California
COUT = 3.6fF
EECS 42 Intro. electronics for CS Fall 2001
Lecture 24: 11/28/01 A.R. Neureuther
Version Date 12/01/01
Computer Circuits Are and Order of
Magnitude Slower Than a Simple Inverter.
The Source/drain capacitance of a circuit increases roughly
proportional to the number of input signals.
Slide 13
will give
The resistance from the output node to ground of VDD increases an
roughly proportional to the number of input signals.
example
The time to charge the internal source/drain capacitances is the
product of the capacitance and resistance and roughly increases
as the square of the number of input signals.
The delivery of the output signal to more than one logic gate
(Fan-Out) introduces further loading proportional to the FanOut.
Copyright 2001, Regents of University of California
EECS 42 Intro. electronics for CS Fall 2001
Lecture 24: 11/28/01 A.R. Neureuther
Version Date 12/01/01
Study this page carefully as three starting point mistakes were corrected.
Example CMOS Circuit
VDD
A
B
CLOAD = (12+6+3+1.5)(0.4fF) = 9 fF
VDD
3
3
3
C
3
3
VOUT
1.5
A
B
1.5
C
1.5
1.5
1.5
CLOAD
Lump all at
this node.
Copyright 2001, Regents of University of California
Worst case is a=1, c =0,
and b changes 1 => 0
R = 2RDP = 24kΩ
∆t= 0.69(24kΩ)(9 fF )
= 149 ps
For comparison the
inverter had a pull-up
delay of 30 ps
EECS 42 Intro. electronics for CS Fall 2001
Lecture 24: 11/28/01 A.R. Neureuther
Fanout
3
Fanout is always ≥ 1 (there is
always a load)
3
1
1.5
Gate capacitances sum and
are charged by the driver
resistance
One load device was in
included in the initial
estimate of CLOAD.
Version Date 12/01/01
3
1.5
Fan-Out (FO) = n
2
3
n
1.5
C’LOAD= CLOAD + (FO - 1)((W/L)p +(W/L)n)(CG/MS)
C’LOAD= CLOAD + (FO - 1)(1.5+3.0)(0.4 fF)
Copyright 2001, Regents of University of California
Assumes
minimum
length devices.
EECS 42 Intro. electronics for CS Fall 2001
Lecture 24: 11/28/01 A.R. Neureuther
Version Date 12/01/01
Coping with Power Consumption
a.c. POWER
D.C. POWER
Tube: 300V x 20 mA = 6W
Bipolar Transistor: 5V x 20 mA = 200 mW
NMOS Transistor: 5V x 200 µA = 1 mW
True of every gate!
CMOS Transistors: 5V x 100 nA = 0.5 µW
Assumes ½ of
the gates
change state
PSHORT-CIRCUIT = (1/2) ISHORT-CIRCUIT VDD τ30-70 fCLOCK
= (1/2) (60 µA) 2.5V (0.1ns) (109) = 7.5 µW
PDYNAMIC = (1/2)(1/2) C VDD 2 fCLOCK
Only the L =>H
= (1/2) (1/2)(10 fF) (2.5)2 109 = 15.6 µW
takes energy
True for only active gates.
from VDD
Copyright 2001, Regents of University of California
EECS 42 Intro. electronics for CS Fall 2001
Lecture 24: 11/28/01 A.R. Neureuther
Version Date 12/01/01
What Might You be Buying for Christmas 2010?
Today’s Technology: Pentium IV, 42 million transistors, 40-60
Watts, L = 0.18 µm
Intel’s Statements in San Francisco Chronicle pp. E1, 11/26/01:
“We don’t see any fundamental barrier (to Moore’s Law of scaling).
Introduced a Tera-Hertz transistor for the 30 GHz (2010 generation)
There is a problem of ‘leakage’ of energy even when the transistors
are in the off position.
Intel’s new design stems the energy flow by using a different material
for the existing insulator in one area of the transistor while adding
another insulator on top of the silicon.
If Intel wins their bet in
The claim the leakage is 10,000 times smaller. 2010 you can use your
knowledge from EE 42 to
explain to the sales person
“We’re betting our entire business on this.”
how this technology
improvement works.
Copyright 2001, Regents of University of California