phys. stat. sol. (c) 3, No. 6, 2368 – 2372 (2006) / DOI 10.1002/pssc.200565119
Enhancement-mode AlGaN/GaN HEMTs on silicon substrate
Shuo Jia, Yong Cai, Deliang Wang, Baoshun Zhang, Kei May Lau, and Kevin J. Chen*
Department of Electrical and Electronic Engineering, Hong Kong University of Science and Technology,
Clear Water Bay, Kowloon, Hong Kong
Received 25 July 2005, revised 21 February 2006, accepted 4 April 2006
Published online 19 May 2006
PACS 73.40.Kp, 81.05.Ea, 85.30.Tv
High performance enhancement-mode AlGaN/GaN HEMTs (E-HEMTs) were demonstrated with samples
grown on low-cost silicon substrate for the first time. The fabrication process is based on fluoride-based
plasma treatment of the gate region and post-gate annealing at 450 °C. The fabricated E-HEMTs have
nearly the same peak transconductance (Gm) and cut-off frequencies as the conventional depletion-mode
HEMTs (D-HEMTs) fabricated on the same wafer, suggesting little mobility degradation caused by the
plasma treatment.
© 2006 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
1 Introduction
Most of the development in GaN-based HEMT technology has been focused on depletion-mode AlGaN/GaN HEMTs (D-HEMT) [1–4] that feature negative gate threshold voltage. Enhancement-mode
HEMT (E-HEMT) devices, which exhibit a positive threshold voltage, provide extra benefits in many
applications. For RF/microwave applications, the E-HEMTs enable the elimination of the negative polarity supply voltage, leading to reduced circuit complexity, size and cost. For digital applications, EHEMTs integrated with D-HEMTs can be used in direct coupled FET logic (DCFL) circuits that have
much simpler circuit configurations compared to those implemented by D-HEMT based technologies.
However, the fabrication of E-HEMTs in III-nitride materials is difficult due to the large amount of polarization charges in AlGaN/GaN hetero-structures. To date, most E-HEMTs have been fabricated by
reducing the gate-to-channel distance via thinner barrier layer growth [5] or recess etch [6, 7]. The approach using thinner barrier features large access resistance that degrades the transconductance. The
recessed-gate approach requires additional pre-gate annealing and additional gate-level photolithography,
which implies that the gate recess and gate metallization are not self-aligned. A novel approach is proposed by our group recently on samples grown on sapphire substrate. The technique employs selfaligned fluoride-based plasma treatment of the gate region and post-gate annealing [8], maintaining low
access resistance. Confirmed by second ion mass spectroscopy (SIMS) measurement, the plasma treatment can effectively incorporate immobile negatively charged fluorine ions into AlGaN barrier, raise the
conduction band, and shift the threshold voltage to a positive value. For high volume applications, such
as digital integrated circuits, it is necessary to demonstrate E-HEMT on silicon substrate that offers benefits of large-size and low-cost.
In this paper, we demonstrate the first AlGaN/GaN E-HEMTs on silicon substrates. Crack-free AlGaN/GaN HEMT structures were grown on silicon substrates. Using fluoride-based plasma treatment,
D-HEMTs with a threshold voltage of -3.3 V are converted to E-HEMTs with a 0.5 V threshold voltage,
allowing monolithic integration of E-HEMT and D-HEMT for digital applications.
*
Corresponding author: e-mail: eekjchen@ust.hk, Phone: +852- 2358-8969, Fax: +852-2358-1485
© 2006 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
phys. stat. sol. (c) 3, No. 6 (2006)
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2 Material growth and device fabrication
The heterostructure layers employed in this study were epitaxially grown by metalorganic chemical vapor deposition (MOCVD) on a 2-inch (111) silicon substrate. It consists of a 30 nm high temperature
AlN nucleation layer grown at 1150 °C, followed by a 1 µm thick GaN buffer, which has a 10 nm thick
low-temperature AlN interlayer grown at 760 °C inserted in the middle. Then the Al0.3Ga0.7N barrier is
grown, which consists of a 3-nm undoped spacer, a 15-nm doped (Si doped, 5x1018 cm–3) carrier supply
layer, and a 2-nm undoped cap layer. Owing to the optimized interlayer, the grown sample is crack free.
For device processing, both D-mode and E-mode HEMTs are implemented on the same wafer. Device
mesa was formed using Cl2/He plasma dry etching in an STS ICP-RIE system followed by the
source/drain ohmic contact formation with Ti/Al/Ni/Au annealed at 850 °C for 30 seconds. The ohmic
contact resistance was typically measured to be 0.7 Ω-mm by TLM method. Ni/Au e-beam evaporation
and lift-off were carried out subsequently to form the gate electrodes. E-HEMTs underwent identical
processing as D-HMETs, except for an additional fluoride-based treatment before the gate metal deposition. This treatment employs CF4 plasma in a RIE system at a power 170 W for 120 seconds after gate
regions were open by photolithography. D-HEMTs are protected by photoresist during treatment and not
affected. After the gate metal deposition, the sample was annealed at 450 °C in N2 ambient for 10 minutes to recover the plasma induced damage. Experiment results show that the pinch-off voltage shift will
increase with both the plasma power and treatment time. However, higher energy treatment will cause
un-recoverable damage and degradation of mobility. This RTA temperature was chosen to be 450 °C out
of consideration of maintaining good gate Schottky contact and source/drain ohmic contacts. All the D/E
mode devices stated in this article have 1 µm gate length and 100 µm gate width with a source-gate spacing of LSG = 1 µm and a gate-drain spacing of LGD = 2 µm.
3 Device characteristics and discussion
The transfer characteristics of both D-mode and E-mode HEMTs fabricated on the same wafer are plotted in Fig. 1(a). Defining the threshold voltage (Vth) as the gate bias intercept of the linear extrapolation
of drain current at the point of peak transconductance (gm), the Vth of D-HEMTs is -3.3 V, while for EHEMTs it is 0.5 V. The peak Gm was 182 mS/mm for D-mode device and 167 mS/mm for E-mode device. The small difference may come from device variation or un-recovered damages. The shift of Vth is
attributed to the incorporation of negative charged fluorine ions into the AlGaN barrier during the plasma
treatment. These immobile charges effectively deplete the channel electrons and convert the HEMT into
E-mode. Owing to the self-aligned nature of the plasma treatment, the access region between the source
and gate remains to be D-mode and low on-resistance (Ron) can be maintained, a key feature for achieving high-performance E-HEMT. Figure 1(b) shows the output characteristics of E-mode devices (before
and after annealing). Comparison of source-drain current-voltage curves of E-mode device before and
200
1200
D-mode
E-mode
100
600
400
200
0
-7
50
Vth=-3.3 V
VDS=10V
-6
-5
-4
-3
-2
-1
VGS (V)
0
2
3
250
200
150
100
50
Vth=0.5 V
1
VGS: From 0 to 2.4 V, step by 0.3 V
Before RTA
After RTA
E-HEMT
IDS (mA/mm)
150
800
Gm (mS/mm)
IDS (mA/mm)
1000
350
300
4
0
0
0
2
4
6
VDS (V)
8
10
Fig. 1 DC characteristics. (a) Transfer curves measured on the D/E mode device. (b) Output curves of E-mode
device before and after RTA at 450 °C.
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Shuo Jia et al.: Enhancement-mode AlGaN/GaN HEMTs on silicon substrate
after annealing suggests that that annealing at 450 °C for 10 minutes is essential to recovering the damage induced during the plasma treatment. No shift of threshold voltage was observed after the annealing.
Among 35 E-mode HEMTs tested across a 1 cm by 1 cm area, the standard deviation of the threshold
voltage is about 0.1 V.
It should be pointed out that the E-mode device can be biased to higher gate voltage up to 2.5 V,
which in turn provides a larger gate voltage swing and thereby improves the dynamic range for the input.
To study this phenomenon we compare the gate current of D/E HEMTs with both source and drain
grounded. As can be seen in Fig. 2, the E-mode device showed a reduction of both forward and reverse
gate currents, especially at VGS larger than 1 V. Corresponding to the same gate leakage current in
D-HEMT at VGS = 1.5 V, the E-HEMT can be biased at 2.5 V. We believe the mechanism for gate current is a combination of thermal emission and tunneling through the AlGaN barrier. The incorporation of
negative charge in the AlGaN barrier can effectively raise the conduction band energy of the barrier,
resulting in higher potential barrier for both thermal emission and tunneling. Consequently, the gate
current is suppressed.
1
10
D-mode
E-mode
0
10
-1
Ig (A/mm)
10
Fig. 2 Gate Schottky diode characteristics of the D-HEMTs
and E-HEMTs with both source and drain grounded.
-2
10
-3
10
-4
10
-5
10
-6
10
-7
10
-16 -14 -12 -10 -8
-6
-4
-2
0
2
4
Vg (V)
The on-wafer small-signal characterization was carried out by S-parameter measurements with an
Agilent 8722ES Network Analyzer and a microwave probe station. The devices were measured at the
bias condition exhibiting the peak Gm as shown in Fig. 3. A current gain cutoff frequency (fT) of 7.5 GHz
and a maximum stable gain/maximum available gain (MSG/MAG) cutoff frequency (fmax) of 16.9 GHz
were obtained from E-HEMTs, which are close to the D-HEMTs, whose fT and fmax were 7.9 GHz and
18.7 GHz, respectively. These results suggest that a large shift in the threshold voltage can be achieved
without degradation of transconductance and RF performance through the treatment and post-gate annealing technique.
Gain (dB)
40
30
Current gain of D-mode HEMT
MAG/MSG of D-mode HEMT
Current gain of E-mode HEMT
MAG/MSG of E-mode HEMT
20
Fig. 3 Short-circuit current gain (H21) and maximum stable
gain/maximum available gain (MSG/MAG) of the typical 1
µm x 100 µm D/E-HEMTs measured at gate bias displaying
maximum transconductance and VDS = 10 V.
10
0
1E8
1E9
Frequency (GHz)
1E10
4 Simulations and discussion
In order to investigate the mechanisms of the threshold voltage shift by CF4 plasma treatment, second ion
mass spectrum (SIMS) measurements were carried out on accompanying samples. Confirmed by SIMS
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phys. stat. sol. (c) 3, No. 6 (2006)
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measurement [8], the plasma treatment can effectively incorporate negatively charged fluorine ions into
AlGaN barrier, raise the potential in conduction band, and shift the threshold voltage to a positive value.
To confirm this explanation, we calculate the conduction band profile by applying Poisson’s equation
and Fermi-Dirac statistics. Parameters used for this calculation are the same as those listed in [9]. Based
on SIMS result, we assume a Gaussian distribution of the negative charged fluorine ions as follows:
N ( x) = N P *exp( -
x2
)
2∆ 2
(1)
NP is the peak concentration at AlGaN surface and equals to 2x1019 cm–3, and a standard deviation ∆ of 7
nm is assumed. N(x) is the negative charge concentration as the function of vertical depth. This profile is
in good agreement with the measured result. We adopted an effective polarization charge density of
8x1012 cm–2 and a Schottky barrier height of φB = 0.6 V in this simulation to match experimentally observed valued of pinch-off voltage. Figure 4 shows the conduction band structure along a vertical cross
section under the gate. The solid line and dashed line represent the conduction band of D-mode (without
fluorine ions) and E-mode (with fluorine ions) device respectively, and the dotted line shows the position
of the Fermi level.
As shown in Fig. 4 (a), the negative charges are incorporated into the AlGaN layer after plasma treatment, and the 2DEG in the channel of E-mode device are depleted to maintain charge neutrality. In modeling the band diagram, the conduction band at the surface is pinned by the schottky barrier, and the
incorporated negative charges can effectively raise the conduction band, to the extent that the Fermi level
is below the conduction minimum at AlGaN/GaN interface. Figure 4 (b) shows the band diagram with
positive gate bias. It is generally believed that the mechanism for gate current is a combination of thermal emission and tunneling through the AlGaN barrier [10, 11]. After treatment, the conduction band of
AlGaN is raised, resulting in effectively higher and thicker barrier for channel electrons to tunnel through
the AlGaN layer, and the forward gate current is suppressed. Figure 4 (c) shows the band profile with -5
V gate bias. Similarly, the probability for electrons tunneling through the barrier layer is reduced, and
consequently the reverse leakage current is decreased. This simulation result is in agreement with the
measured gate currents, as shown in Fig. 2.
1.0
0.5
0.0
-0.5
EF
0
20
40
60
Depth (nm)
80
D-mode Gate bias: +1 V
E-mode
0.4
0.2
Energy (eV)
Energy (eV)
1.5
8
0.6
D-mode Gate bias: 0V
E-mode
0.0
EF
-0.2
-0.4
-0.6
-0.8
100
-1.0
D-mode Gate bias: -5 V
E-mode
6
Energy (eV)
2.0
4
2
0
0
20
40
60
Depth (nm)
80
100
0
50
100
150
200
250
EF
300
Depth (nm)
Fig. 4 Simulated conduction band edge profiles with (a) zero gate bias, (b) gate bias of +1 V, and (c) gate bias of 5 V of AlGaN/GaN heterostructures. Solid lines represent D-mode device and dashed lines represent E-mode device
with plasma treatment.
5 Conclusions
We demonstrate, for the first time, both depletion-mode and enhancement-mode AlGaN/GaN HEMTs
fabricated on the same sample grown on silicon substrate. This technique is based on a combination of
self-aligned plasma treatment of the gate region and a post-gate annealing process. The fabricated EHEMTs device exhibits a threshold voltage above zero with nearly no degradation of transcondcutance
and RF performance. Meanwhile the gate leakage current in the E-mode HEMT is suppressed, allowing
larger input voltage swing. These results are attractive for various applications requiring low-cost D/Emode HEMTs integration.
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Acknowledgements This work is partially supported by the Research Grant Council of Hong Kong Government
under CERG grant HKUST6317/04E, HKUST6215/03E and 611805.
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