Date due: Beginning of 3rd week lab period
CE310 - Digital Systems II
Lab #2
VHDL Design and Simulation of Digital Circuits
Objective: to learn the VHDL design entry, simulation, basic timing analysis and
implementation process of a digital design using a modern design tool.
Introduction:
VHDL is an industry standard and portable hardware description language (HDL). It is a
high-level programming language specifically made for describing how a circuit behaves.
It is well structured and allows modular and hierarchical designs to manage system
complexity.
VHDL was initially intended as a documentation language for describing the structure of
complex circuits, and for modeling the behavior of digital circuits for simulation. Today,
however, it has become a popular tool for design entry in CAD systems, which synthesize
the VHDL code into hardware implementation. VHDL is a sophisticated language so
only a subset of features for use in synthesis will be covered in this course. The required
features will be introduced when needed.
In this first lab exercise you will learn how to use the VHDL design entry for describing a
digital design, synthesis of the design, performing basic functional and timing
simulations, and implementing designs on to a target FPGA.
Tasks:
First read the “Quartus II Introduction Using VHDL Design” tutorial to learn how to use
the VHDL design entry. Apart from the initial design entry step to describe your
hardware design in VHDL, the rest of the process, i.e. the synthesis, simulation and
implementation are identical to what you are already familiar with from your first lab.
I) House alarm in VHDL
Do the same house-alarm design from lab #1, but this time using VHDL entry method.
1) Follow the steps of using the Quartus II CAD tool as described in the tutorial to
Create a project that realizes a house alarm circuit described as follows. The
ALARM output is asserted (‘1’) if the user is in panic (i.e. the PANIC input is
‘1’); or if the alarm’s enable input is asserted (i.e. ENABLEA is ‘1’), the user is
not exiting (i.e. EXITING is ‘0’), and the house is not secure (i.e. SECURE is
‘0’). The house is considered secure if the WINDOW, DOOR and GARAGE
sensor inputs are all ‘1’. The following logic equation captures the expected
behavior of the alarm system.
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Date due: Beginning of 3rd week lab period
CE310 - Digital Systems II
ALARM = PANIC + (ENABLEA & !EXITING & !SECURE)
where,
SECURE = DOOR & WINDOW & GARAGE
You will target your alarm circuit on to the DE2 evaluation board, so you will
have to make the proper pin assignments for the inputs and outputs of your circuit
to switches and LEDs connected to the FPGA on the board. Refer to the file
DE2_pin_assignments.csv for the pin assignments of the DE2 board.
2) Perform functional and timing simulation of your alarm circuit on representative
test vector that you create to verify its functionality and to analyze its timing
performance.
As part of the timing analysis determine the time delays in each of the following
cases:
a) From the time PANIC goes from LOW to HIGH till you see a LOW to
HIGH transition on the ALARM output signal, assuming initially the
output was LOW.
Delay: _________________
b) From the time EXITING goes from HIGH to LOW till you see a LOW to
HIGH transition on the ALARM output signal, assuming initially the
output was LOW and all other input conditions are such that the output
produces the desired transition.
Delay: _________________
c) From the time GARAGE goes from LOW to HIGH till you see a HIGH to
LOW transition on the ALARM output signal, assuming initially the
output was HIGH and all other input conditions are such that the output
produces the desired transition.
Delay: _________________
3) Program your design (using the JTAG programming mode) on the FPGA on the
DE2 board and demonstrate its functionality to your lab instructor.
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Date due: Beginning of 3rd week lab period
CE310 - Digital Systems II
II) Multiplexers
Figure 1a below shows a sum-of-products circuit that implements a 2-to-1 multiplexer
with a select input s. If s = 0 the multiplexer’s output m is equal to the input x, and if s = 1
the output is equal to y. Part b of the figure gives a truth table for this multiplexer, and
part c shows its circuit symbol.
Figure 1: A 2-to-1 multiplexer
1) Create a VHDL design project for implementing a 2-to-1 multiplexer on the
FPGA on the DE2 board. Use switch SW17 on the DE2 board as the s input,
switch SW0 as the x input, and SW1 as the y input. To see the status of the input
and output signals, connect the two input switches to two red lights (e.g. LEDR1
and LEDR0) and the output to a green light (e.g. LEDG0).
2) Perform functional and timing simulation on your 2-to-1 multiplexer circuit on
representative test vector that you create to verify its functionality and to analyze
its timing performance.
a. What is the longest propagation delay in the circuit?
b. What input change(s) result in the longest propagation delay?
4) Program your 2-to-1 multiplexer on the FPGA and demonstrate its functionality
to your lab instructor.
3) Create a VHDL design project that implements an 8-bit wide 2-to-1 multiplexer
shown in Figure 2a. This circuit has two eight-bit inputs, X and Y, and produces
the eight-bit output M. If s = 0 then M = X, while if s = 1 then M = Y. This circuit
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Date due: Beginning of 3rd week lab period
CE310 - Digital Systems II
has the symbol shown in Figure 2b, in which X, Y, and M are depicted as eight-bit
wires (buses). Use switch SW17 on the DE2 board as the s input, switches SW7-0 as
the X input and SW15-8 the Y input. Connect the SW switches to the red lights
LEDR and connect the output M to the green lights LEDG7-0.
Figure 2: An 8-bit wide 2-to-1 multiplexer
4) Perform functional simulation on your 8-bit wide 2-to-1 multiplexer circuit on
representative test vector.
5) Program your 8-bit wide 2-to-1 multiplexer design on the FPGA and demonstrate
its functionality to your lab instructor.
Check-off and report:
Demonstrate your working circuit simulation to your lab instructor for representative
input data combinations. Hand in print outs of your well-commented VHDL design codes,
the timing diagrams, and answers to the questions. Include the authors’ names, date, brief
description of the circuit, the input & output signals, and other relevant information in
your comments. The information you need to provide in the cover page of your report
and its format should be the same as that outlined in the first lab assignment handout.
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