POWER AMPLIFIERS
©James Buckwalter
1
Power Amplifiers
• Purpose of a power amplifier
– Generate high output power
– Efficient conversion of DC power to RF
power
– Linear amplification
• Generally PAs will be
– Common source
– Cascode
• Inductor is a “choke” to provide DC
• Capacitor is a “ac coupling” path to
output
©James Buckwalter
2
Definition of Power
• Instantaneous Power
• Average Power
P = v (t ) × i (t )
T
1
Pav = ò v (t ) × i (t ) dt
T t=0
• There is a component that averages to zero that
corresponds to energy stored and dissipated each
cycle.
©James Buckwalter
3
Definition of Power
• If the voltage and current is
v ( t ) = V cos (wt )
i (t ) = I cos (wt + q )
• The average power becomes
T
1
1
2
Pav = VI cosq ò cos (wt ) dt = VI cosq
T
2
t=0
• In phasor notation v (t ) = V Re {e jwt }
1
1 2
1 2
1
*
P = Re {vi } = V Re {Y } = I Re { Z } Preac = Im { vi * }
2
2
2
2
©James Buckwalter
4
Example:
©James Buckwalter
5
Time Scales for Power Amplifiers
• Carrier T ~1ns, Period Ts ~100ns, Control ~ 1ms
©James Buckwalter
6
Power Scales for Power Amplifiers
©James Buckwalter
7
Large Signal Analysis
• Consider harmonic analysis
v ( t ) = åVk cos ( kwt )
k³0
i ( t ) = å I k cos ( kwt + q k )
• Power
• In phasor
k³0
1
P = V0 I 0 + åVk I k cos (q k )
2 k³1
1
1
2
2
P = å Vk Re {Yk } = å I k Re { Z k }
2 k³1
2 k³1
©James Buckwalter
8
Harmonic Engineering
• Power is not simply V2
• May see strong harmonic content but power
delivered at harmonics might be small due to
impedance at harmonics
1
1
2
2
P = å Vk Re {Yk } = å I k Re { Z k }
2 k³1
2 k³1
• Keep load reactive at harmonics.
©James Buckwalter
9
PA Characteristics
Voltage versus time
Output versus Input Power
Current versus time
Gain versus Power
Loadline Impedance
Efficiency versus Power
Harmonics
©James Buckwalter
10
Notation
• Be careful about notation of voltage, current,
and power.
1
• Average power P = Re {vi * }
2
• For small signal, RMS voltage and current is
v
common
vrms =
2
• Therefore,
P = Re {vrmsi
*
rms
©James Buckwalter
}
11
Units
• Peak Units
vRF = v pk sin (w RF t )
• RMS Units
T /2
(
)
2
1
vrms =
v RF (t ) dt
ò
T -T /2
© James Buckwalter
12
What does it mean to be
“matched”?
• The antenna will appear to be 50  at the
RF frequency so the input impedance of the
receiver should be 50 .
• Why 50 ?
–
–
–
–
It’s historical but an important (IEEE) standard.
30 Ohms offers the best power handling.
75 Ohms offers the lowest attenuation.
All test interfaces are 50 .
©James Buckwalter
13
Power Amplifier Matching
• Loadline should be
matched to 50 Ohm
antenna output (or
something like that).
• How do we do this?
©James Buckwalter
14
Power Delivered to a Load
2
iL
1
1
*
*
Pdel ,L = Â{ v L iL } = Â{ iL Z L iL } =
RL
2
2
2
Pdel ,L =
vS
2
2
(R
S
RL
+ RL ) + ( X S + X L )
2
©James Buckwalter
2
15
Power Delivered to a Load
Pdel ,L =
vS
2
2
(R
S
RL
+ RL ) + ( X S + X L )
2
• How do you maximize the power delivered?
• Vary the load while keeping the source impedance
fixed.
©James Buckwalter
16
2
Two Important Conclusions:
Conjugate (Power) Matching
¶PDL
II)
= 0 ® RS = RL
¶RL
I)X S = - X L
Pdel ,L,max =
vS
2
8RS
=
vL
2
2RL
©James Buckwalter
since vL =
RL
1
vS = v S
RS + RL
2
17
What is the Penalty for Mismatch?
X S = -X L + d X
Pdel ,L =
vS
2
8RS
1
æ dX ö
1+ ç
÷
è 2RS ø
2
®
Pdel,L
Pav,S
=
1
æ dX ö
1+ ç
÷
è 2RS ø
2
• The PA is very nonlinear at high power. This explains
how the gain and power change under different
conditions.
©James Buckwalter
18
Characteristics of Transistor
Amplifiers
©James Buckwalter
19
Ideal Assumptions
• The transistor acts like a current source
• Current controlled by input voltage as long as
threshold condition is satisfied.
• Current is independent of output voltage as long
as minimum/maximum output voltage is
satisfied.
©James Buckwalter
20
Difference between Current Models
©James Buckwalter
21
Classes of Power Amplifier
• Bias point amplifiers
– Class-A
– Class-B
– Class-C
• Switching amplifier
– Class-E
– Class-F
©James Buckwalter
22
PA Waveform
• Drain current consists of
DC current and AC
current
iD = I D + id
id = i pk sin (wot )
vo = -id R
©James Buckwalter
23
PA Quiescent Conditions
• DC Conditions
VDS = VDD
IDS = IDD
• DC and AC Conditions
VDS = VDD+VAC
VAC = VOUT
IDS = IDD+IAC
IAC=-ILOAD=-VOUT/RL
©James Buckwalter
24
Transistors as Power Devices
• At high-power, the transistor is
operating as a large signal
device.
• Large voltage swing across
drain-source junction
• Maximum voltage is VMAX~2Vdd
of transistor
• Minimum voltage is VMIN ~Vk
where transistor begins to
turn off
• Maximum current of transistor
at VMIN is Imax
©James Buckwalter
25
Time Waveforms
vin = VGG + v pk cos (wot )
iD = I DD - i pk cos (wot ) = I DD - iL
iL = i pk cos (wot )
vDS = VDD + iL RL
©James Buckwalter
26
Class A Operation
• Bias such that device never turns “off” (Vgs – Vt > 0)
iD = I DD - ipk cos (w RF t )
vDS =VDD + ipk RL cos (w RF t )
PRF =
2
ipk
RL
2
• Note that the peak voltage across transistor is 2 Vdd!
©James Buckwalter
27
Class-A Efficiency
• How much power consumption is required to keep
the amplifier from turning off?
iD = I DD - i pk cos (w RF t )
v DS = VDD + ipk RL cos (w RF t )
I DD ³ ipk
VDD ³ ipk RL +VMIN
• Device power
1 2
Pdev = Pdev ( dc) + Pdev (w ) = I DDVDD - ipk RL
2
• Maximum efficiency
2
i pk
RL
PRF
V
h=
=
£ DD = 50%
PDC 2I DDVDD 2VDD
©James Buckwalter
28
Voltage Swing Limitations
P
• Efficiency
h= o
PDC
• RF Voltage/Current
VRF ,MAX
=
Po Pmax
Pmax PDC
1
= (V MAX -V MIN )
2
1
V MAX +V MIN )
(
2
= 2VDD -V MIN
VDD =
V MAX
I RF ,MAX = I DD
• This defines the limitation in delivering power
1
1
PRF ,MAX = VRF ,MAX I RF ,MAX = (VMAX -V MIN ) I DD
2
4
PDC = VDD I DD
©James Buckwalter
29
Class-A Efficiency vs RF Power
• Construct efficiency in terms of minimum device
output voltage and d.c. voltage
PRF
PRF PRF ,MAX
h=
=
PDC PRF ,MAX PDC
h=
h=
PRF
PRF ,MAX
PRF
PRF ,MAX
1 (V MAX -V MIN ) I DD
2 (V MAX +V MIN ) I DD
PRF 1 æ V MIN ö
1 2VDD - 2V MIN
=
çç1÷÷
2
2VDD
PRF ,MAX 2 è VDD ø
Back-off of amplifier
results in linear efficiency
degradation with power
Operating
Power
©James Buckwalter
Maximum
Class-A Efficiency
Device
Factor
30
Class-A Output Power
DON’T THINK YOU NEED THIS SLIDE
2
ipk
R
V MAX -V MIN
1
PRF =
= I DD
2
2
2
1
PRF = I DD (V MAX -V MIN )
4
• The peak output power can be re-written as a product of
the maximum current for the device (where Imax =
2*Ipk) and the voltage swing (where ipk*R = Vdd-Vk)
• So called power triangle
©James Buckwalter
31
Power Triangle
• Another way to look at
this is that the area
under the IV curve
should give the total
power
1 I MAX (V MAX -V MIN )
PRF =
2 2
2
1
PRF = I MAX ( 2VDD -V MIN )
8
Breakdown voltage (BV) may be larger than twice the VDD. More generally, we should take 2 VDD
©James Buckwalter
32
Class A Load-line Resistance
• Must increase current handling or voltage handling of
device.
• Load line is defined by
RLL
V
(
=
MAX
-VMIN )
I MAX
• For Silicon CMOS, voltage is extremely limited. Large
current means wide transistors and low output
impedances.
©James Buckwalter
33
Example: 1 W Power Amplifier in
CMOS
• You are asked to design a 1 W PA in a 1 V
CMOS process.
• What is the size of the transistor assuming
that the transistor can handle 1 mA per
micron of DC current; i.e. 2mA per micron of
Idd? The knee voltage is 0.3 V.
• What is the loadline resistance?
©James Buckwalter
34
Solution: 1 W Power Amplifier in
CMOS
• Power delivered from PA:
PDEL =
I DD ( 2VDD -VK )
4
4PDEL
4W
I DD =
=
= 2.35A
2VDD -VK 1.7V
• CMOS PAs handle high current!!!
©James Buckwalter
35
Solution: 1 W Power Amplifier in
CMOS
• The loadline resistance is
RLL
V
(
=
MAX
-VK )
I DC
2.7V
=
= 1.14W
2.35A
• This is an extremely small resistance. This
makes matching difficult as we will discuss
today!
©James Buckwalter
36
More Examples
©James Buckwalter
37
Class A Load-line Resistance
• Load line can be defined under different conditions
1
PRF = I MAX (VMAX -VMIN )
8
h=
PRF
PRF ,MAX
1 æ VMIN ö
çç1÷÷
2 è VDD ø
• Different load lines selected for fixed Vdd
©James Buckwalter
38
Power/Efficiency Trade-off
• Changing RL changes
efficiency and output
power.
• Larger loadline
resistance achieves
higher efficiency at
expense of power.
©James Buckwalter
39
Changing Loadline Resistance for
Efficiency
• For fixed Vdd, changing
the loadline, the output
power reduces while
the efficiency increases.
• This is an important
observation used for
Doherty, Chereix, and
Envelope Tracking
©James Buckwalter
40
CLOSER LOOK AT LOADLINE
©James Buckwalter
41
Effect of Output Capacitance
• Loadline is not static
when transistor model
is no longer quasi static
d
iD = I DD - i pk cos (w RF t ) + C DS vOUT
dt
id = -ipk cos (w RF t ) + jw RF CDS vOUT
©James Buckwalter
42
Matching Conditions
• 1) DC loadline considerations dictate choice of RL to
optimize Pout or PAE combination. (not necessarily
gain)
• 2) Imaginary part of load admittance is established to
match the imaginary part of device
BL = -Á {YO }
©James Buckwalter
43
Simulating the Reactive Loadline
• De-embed the Cds and Cdg values and add these as
“negative” capacitors to get a quasi-static loadline.
©James Buckwalter
44
Simulation of Waveforms
• Now we can look inside transistor to get loadline
©James Buckwalter
45
Load Pull Contour
• Load pull measurement (simulation) consists of
systematically varying load impedance and
measuring amplifier characteristics
• Load pull contours describe how Pout (efficiency,
linearity, etc) vary with ZL
©James Buckwalter
46
Load Pull Contours
©James Buckwalter
47
Differences in Load Pull for Power and
PAE
©James Buckwalter
48
PA Design Methodology
1. Choose Vdd based on transistor technology with
sufficient power handling capability and breakdown
voltage
2. Using DC characteristics choose load line and verify
the Pout can be obtained.
3. Determine the input impedance matching network
using the bias condition on the average DC current
corresponding to average output power
4. Determine the load susceptance and match the
output to obtain RL and BL
5. Provide output match at harmonic frequencies
6. Set-up bias network
7. Optimize using simulator.
©James Buckwalter
49
Overdriven Class A
• You might wonder what happens when we turn a class
A amplifier to “11”
• In general, you get higher output power and efficiency
in the overdriven regime but this is difficult to analyze
• Vin determine Idrain through the nonlinear transistor
characteristics
• Vdrain depends on the load impedance at different
harmonics
• If Vdrain is too low, the transistor is forced into triod
and becomes a voltage source causing current collapse.
©James Buckwalter
50
©James Buckwalter
51
Power Added Efficiency
• Power added efficiency incorporates the RF power
lost into driving the device.
PAE 
Prf ,out  Prf ,in
PDC
Prf ,out 
Prf ,in

1 
PDC  Prf ,out



1

PAE   1  
 G
• The PAE is never more than the drain efficiency.
• High gain is required from the PAE to make the
amplifier efficient.
©James Buckwalter
52
PAE
• Gain can be changing with output power as device is
pushed into compression
Po =
i R
2
pk
g v )
(
=
m in
2
2
Po
2
G=
µ gm R
Pin
©James Buckwalter
2
R
53
CLASS B
©James Buckwalter
54
Class-B Operation
• Drain current on for half
the cycle
ì
ï ipk cos (w ot ) id > 0
iD = í
0
id £ 0
ïî
iD
v pk = - Rcos (w RF t )
2
v 2pk
2
VDD
PRF =
£
2R 2R
Note that the current is
half-wave rectified by the
voltage is a sine wave!
©James Buckwalter
55
Fourier Components for Half-Wave
ì
ï ipk cos (wot ) id > 0
iD = í
0
id £ 0
ïî
iD ( f ) =
ipk
p
+
i pk
2
sin ( 2p ft ) -
2i pk
p
å
k³1
cos ( 4p kft )
4k 2 -1
• Even harmonics result from half wave current
©James Buckwalter
56
Class-B Loadline
What does this say about
the possible output power?
©James Buckwalter
57
Harmonic Matching for Class-B
• At fundamental, generate loadline match
• At higher harmonics, ZL = 0
©James Buckwalter
58
Power Dissipation in Class A and Class B
©James Buckwalter
59
Class-B Current Analysis
• IQ should be zero for DC (no power consumption with no input).
• However, quiescent current is obviously not the “average”
current.
• To calculate the d.c. power consumption, the d.c. average power
• Looking at the half-wave drain current, we could also calculate
I DC
1
=
2p
p
òi
PK
sin (q ) dq £
0
iPK
p
p
iPK
I FUND = ò iPK sin (q ) dq £
p 0
2
1
2
©James Buckwalter
60
Class-B Efficiency
• The output power and DC power are
2
2
1
1 v PK 1 æ iPK ö
PRF = v PK iPK =
= R çç ÷÷
2
2 R 2 è 2 ø
PDC = VDD I DC = VDD
iPK
p
• Therefore, the maximum drain efficiency is
2
v PK
2
PRF
v
p
p v PK
2R
PK
h=
=
=
=
® h MAX = 78%
PDC VDD iPK 2 RVDD iPK 4 VDD
p
©James Buckwalter
61
Class-A versus Class-B
• Comparing power of Class-A and B
2
VDD
PRF ,A =
2R
2
VDD
PRF ,B =
2R
• Comparing efficiency of Class-A and B
 A  50% B  78%
• What is the cost of class-B amplifier?
©James Buckwalter
62
Class-B Efficiency Revisited
• How does efficiency depend on knee voltage?
• The efficiency depends on the output power
h=
p VRF ,MAX
VRF
4 VDD VRF ,MAX
=
p V MAX -V MIN
4 V MAX +V MIN
PRF
PRF ,max
pæ
V MIN ö PRF
h = çç1÷÷
4 è VDD ø PRF ,max
• The drain efficiency changes with the root of the
output power. Recall for class-A!
1 æ VMIN ö PRF
h = çç1÷÷
2 è VDD ø PRF ,MAX
©James Buckwalter
63
Efficiency vs. Power
Very important! Note
that not only is the
peak power higher
the efficiency is higher
in backoff.
When the average
power is 3 dB lower
than the peak, what is
the efficiency for
class-A and class-B?
©James Buckwalter
64
Class-B Loadline
How do we match to this loadline?
©James Buckwalter
65
Class-B Loadline
• The piecewise loadline shown in the previous
slides seems to suggest a loadline.
• However, we should consider the loadline
based on the fundamental. Therefore, the
voltage swing at the fundamental is (Vmax –
Vmin )/2. The current swing is Imax/2.
• The loadline resistance is the same as class-A!
Vmax -Vmin
RL =
I max
©James Buckwalter
66
Maximum Output Power for Class-B
1
PRF = v RF ,MAX iRF ,MAX
2
1
PRF = (V MAX -VMIN ) I MAX
8
• Again, this is the same as class-A output
power
• So what is the penalty?
©James Buckwalter
67
Gain for Class-B
PRF =
i R
2
pk
8
g v )
(
=
m in
8
2
R
• Compared to the gain for Class-A amplifier the
power gain of class-B is ¼ (or 6 dB) less.
• What is the implication of this? Lower PAE!
©James Buckwalter
68
Gain
©James Buckwalter
69
Features of Class-B
©James Buckwalter
70
CLASS C
©James Buckwalter
71
Class-C Amplifier
• Like class-B, IQ= 0
• Unlike class-B, conduction
angle < 180 deg
• Gain is low since device is
turned on for only a short
period
Harmonics are
shorted
Vmin
Vo
RL
Vo
Vmax
Vout
Vce
Vo
match
match
Iout
Imax
Ic
Idc
©James Buckwalter
Vrf
time
time
72
Class-C Amplifier
Iout
Imax
• IDC < IRF / p
• PRF < 1/4 VRF IRF
• PDC = VDD IDC
VMIN
Harmonics are
shorted
match
Vo
RL
VMAX
VOUT
Vds
VDD
match
VDD
Id
IDC
©James Buckwalter
VRF
time
time
73
Load Impedance Is A Resonant Network
Representative Z values
Vo
Short at all harmonics here
At fo
-j2W
j2W
10 W
j4W
10 W
match
RL
Z
fo
At 2fo
-j1W
Z=RL at fo
Z=0 at 2fo, 3fo, 4fo,…
fo
2fo
©James Buckwalter
74
Class-C Waveform
Ic
Idc
time
ìï i cos f - I when i cosf > I
S
PK
S
I (t ) = í PK
ïî
0 otherwise
I S is the (negative) offset
I
cosf = S ®
iPK
iPK is the amplitude
I FUND =
I FUND =
1 2p
p
2
p
f
ò I (q ) cosq dq = p ò I (q ) cosq dq
2
0
0
f
ò (i
PK
cos 2 q - I S cosq ) dq
0
ö
2 æ1
1
i
f
+
i
sin
2
f
I
sin
f
ç PK
÷
PK
S
ø
p è2
4
ö
2 æ1
1
= iPK ç f + sin 2f - cos f sin f ÷
ø
p è2
4
ö
i æ
1
= PK çf - sin 2f ÷
ø
p è 2
I FUND =
I DC
1
=
2p
I DC =
1
p
f
1
I
q
d
q
=
(
)
ò
2p
0
(iPK sin f - I DDf )
f
ò (i
PK
cosq - I DD )dq
I FUND
0
I FUND
©James Buckwalter
75
Class-C Conduction
• Note the angle φ defined for the waveform
analysis is related to the conduction angle of
the transistor by a factor of two, i.e. 2φ=Φ
• Φ is the conduction angle during which the
current conducts through the transistor. What
happens for Φ of pi or 2pi?
I DC
iPK æ F F
Fö
=
çsin - cos ÷
p è 2 2
2ø
ö
iPK æ F 1
I FUND =
ç - sinF ÷
ø
p è2 2
©James Buckwalter
76
Class-C Efficiency
h=
PRF ,MAX
PDC
(
)
F - sin (F)
v PK iPK
=
=
æ
æFö
æ F öö
2VDD I DC
2 ç 2sin ç ÷ - Fcos ç ÷÷
è2ø
è 2 øø
è
• As conduction angle approaches 0, the efficiency
approaches 100%.
• What is the penalty?
©James Buckwalter
77
Class C Waveform Analysis
• Calculate efficiency in presence of
i pk
h=
h=
Vpk VRF,MAX
F - sin ( F)
f ( F)
=
æ F ö VRF,MAX VDC
æFö
2sin ç ÷ - F cos ç ÷
è2ø
è2ø
p
1 vPK iPK 1 v pk p
=
2 VDC I DC 2 VDC i pk
VFUND
VFUND,MAX
VFUND,MAX
f ( F)
VDC
f ( F) =
æ VMIN ö
POUT
h = f (F) ç1÷
è VDD ø POUT ,MAX
f ( 0) = 1
f (p ) =
p
4
f ( 2p ) =
1
2
F - sin (F)
æFö
æFö
2sin ç ÷ - Fcos ç ÷
è2ø
è2ø
1
2
©James Buckwalter
78
Power Amplifier Comparison
©James Buckwalter
79
Class-C Amplifier Efficiency
• Class C has very good efficiency because whenever the
device has current, Vds is particularly low
Vds
Vrf
Vo
time
ID
Idc
time
©James Buckwalter
80
Class-C Waveform Analysis
Iout
Imax
• How about the loadline
resistance?
RL =
VFUND
I FUND
VMAX -VMIN
2
æF 1
ö
I FUND = I S ç - sin F ÷
è2 2
ø
æ
Fö
I MAX = I S - I O = I S ç1- cos ÷
è
2ø
ö I
I æF 1
F - sinF
I FUND = S ç - sin F ÷ = MAX
ø 2 p 1- cos F
p è2 2
2
æ
Fö
2 ç1- cos ÷
V -V
è
2ø
RL = p MAX MIN
I MAX
F - sinF
Vmin
Vo
30
45
VmaxVout
VFUND =
RL / RL Class A
20
18
16
14
12
10
8
6
4
©James Buckwalter
2
0
0
15
60
75
90
Theta (degrees)
81
Gain and Conduction Angle
Gain (dB)
Class A
Class AB "ideal"
Class AB "real"
6dB
Class B ideal
Class B real
Pin (dBm)
Class C "real"
©James Buckwalter
82
Power Amplifier Comparison
• Maximum voltage swing
is 2Vo – Vmin
• Gain is 6 dB lower for
class-B than class-A,
expect it to be even
lower than class-C.
• Power density is the
same for class A and B
but lower for class C.
©James Buckwalter
83
Other Classes of Amplifiers
• PA research is focused around getting highpower power at high-efficiency.
• Class D Amplifiers
– Push-pull style amplifier
• Class E/F Amplifiers
– Switching amplifiers which can allow 100% PAE
but require care with harmonics
• Class J Amplifier
– Overdriven class-A
©James Buckwalter
84