Gate-Drain Capacitance Behaviour
of the DMOS Power Transistor
under High Current Flow
Christoph Deml1 and Kurt Homann2
1 Siemens AG, Semiconductors, St.-Martin-Str. 76, 81541 Munich, Germany
2 University of Bundeswehr Munich, Institute of Electronics,
Werner-Heisenberg-Weg 39, 85577 Neubiberg, Germany
Abstract
The gate-drain capacitance of a power DMOS
transistor was measured under high current
conditions of up to 250 A. Depending on
VGS a strong nonlinear characteristic was observed. Using the measured capacitance data
the characteristics of the inner MOS transistor and the epi region have been determined separately for parameterisation and
modelling.
Introduction
The characteristic of the gate-drain capacitance has,
due to the Miller -eect the most signicant inuence on the transient behaviour of power DMOS
transistors.
This capacitance is normally specied in data
sheets without current ow. To our knowledge, it is
not yet known how this capacitance behaves under
high current. The reason for this is that this cannot easily be determined because of thermal overload and destruction of the device. To avoid this,
a circuit has been designed to signicantly reduce
self-heating.
Measurement of the Gate Drain
Capacitance at High Current Flow
The basic idea is to apply a constant gate voltage VGS and a saw-tooth drain voltage VDS (t) to
the device and measuring the gate current IG (t)
(Figure 1). Using the measurement circuit of Figure 2 the gate-drain capacity can be determined by
(1)
CGD (VGS ; VDS (t)) = C IIG ((tt)) :
C
DUT
REpi
0
CGD ;ox
0 ()
VD S t
()
A
IG t
()
VDS t
CGB;ox
VGS
CGS;ox
Figure 1: Basic idea of the measurement set-up.
The gate current can be described by
IG V
GS
=const
,CGD0 ;ox dVdtD0 S
D0 S dVDS
= ,CGD0 ;ox dV
dVDS dt (2)
where VD0 S is the eective drain voltage of the inner
MOS-transistor as shown in Figure 1 which can be
determined
Z
1
V 0 =
V 0 dA
(3)
DS
AGD0 ;ox
A 0
DS
GD ;ox
as the average voltage at the surface between gate
oxide and n, epi region (Figure 3).
The gate oxide capacitance (Figure 3) can be
divided into the components
Cox = CGS;ox + CGB;ox + CGD0 ;ox
(4)
overlapping the source, bulk and drain regions of
the transistor. CGS;ox is not eected by the changing drain voltage and only to a very small extent
Nominal
Derivative
High-Pass-Filter
Integrator
2
3
(Differentiator)
A
V
A IC
DUT
G
C
GS
V VDS
,CGD [nF]
I
I
A
GB;ox
GS
DS
p
V
0
V
D0 S
n,
n+
DS
10
ID [A]
Figure 3: Gate oxide capacitances and eective voltages.
VDS [V]
20
12
gate-drain capacitance can be expressed by
=const
:
(5)
100
With this equation it becomes obvious that the nonliniarity of the gate-drain capacitance is caused by
the DC-behaviour of the inner MOS transistor's effective drain voltage VD0 S in respect to the applied
one VDS .
Since dVdt is known and the gate current is measured, the capacitance CGD (VGS ; VDS ) (equations 2
and 5)
DS
CGD = dVIG
dt
DS
V =const
(6)
GS
can be determined. This has been done for a dVdt
of 2 Vs and is shown in Figure 4.
DS
0
9
VGS [V]
6
CGB;ox. Since furthermore CGD0 ;ox CGB;ox the
GS
30
200
Drain
D0 S CGD ,CGD0 ;ox dV
dVDS V
20
A strong VGS dependence { this means current
dependence { exists. The capacitance behaviour
at VGS = 0V corresponds to the data sheet value.
The respective transfer characteristic of the device
is shown in Figure 5.
ox
+5V
dV
GD 0 ;ox
n+
20
0
Figure 4: Measured gate-drain capacitance of the
BUZ 103 SL.
C
Gate
GS;ox
Source
V
12
G
C
C
V
9
1
0
Figure 2: Basic structure of the measurement circuit.
+2V
VGS [V]
6
0
10
3
0
20
VDS [V]
30
Figure 5: Measured transfer characteristic of the
BUZ 103 SL.
As is obvious by the slight decrease in current,
self-heating was not completely avoided.
In order to validate the measurements two dimensional device simulations have been performed on
the structure of Figure 6.
Source
n+
Gate
V
2
VGS [V]
4
5
0
6
10
0
20
30
VDS [V]
Figure 8: Calculated gate-drain capacitance using
dV 0 of the device simulation.
dV
D0 S
p
CGD0;ox dVdVDDS0S [fF]
Validation by Device Simulation
1
D S
DS
V
R
Epi
n,
E pi
Seperation of MOS and Epi
Characteristics
The capacitance CGG is dened by
CGG = dVIG
Drain
dt V =const
GS
,CGD [fF]
The capacitance characteristic could be simulated and veried (Figure 7).
2
0
0
20
0
(8)
where Vox denotes the eective oxide voltage which
equals the average voltage across the oxide.
Z
1
V =
V dA
(9)
Aox
A
ox
ox
6
20
VDS [V]
dVox V
DS
30
Figure 7: Device simulation of the gate-drain capacitance.
Furthermore it could be veried that the product
0
CGD0 ;ox dV
dV (Figure 8) corresponds well with the
D S
simulation.
Therefore it can be assumed, that the drain voltage VD0 S at the end of the MOS-channel behaves
similar to the eective one VD0 S of Figure 3.
DS
IG = Cox dVdtox
The eective oxide voltage can be approximated by
5
10
(7)
In general the gate current can be described as the
displacement current through the gate oxide
ox
VGS [V]
4
:
DS
Figure 6: MEDICI structure for device simulation
and typical subcircuit model.
1
d(VGS , VD0 S )V
=0
DS
(10)
=0
because this simplication has only a minor eect
on equation 13. Equations 7, 8 and 10 result in
CGG V
DS
=0
Cox
D0 S 1 , dV
dVGS V
!
DS
=0
:
(11)
At VGS = VDS = 0 the eective drain voltage of
the inner MOS-transistor is the sum of the contact
voltages from the n, epi region to the source metal.
VD0 S V
GS
=VDS =0
Nn,
= kT
q ln Nn+ + n ;metal (12)
+
Starting with these voltages equation 11 is integrated up to VGS while VDS remains zero. Then
VGS is held constant and equation 5 is integrated
up to VDS . This results in
VD 0 S , C 0
GD ;ox
VZ
DS
0
+ VGS , C1
ox
+ VD0 S CGD (VGS ; VDS ) dVDS
VZ
GS
0
V =V =0
GS
DS
CGG(VGS )V
DS
=0
dVGS
:
9
VD0S [V]
10
VGS [V]
6
30
4
20
2
10
20 0
VDS [V]
VGS [V]
6
100
0
10
0
12
(13)
Using the data of the measured capacitance behaviour (Figure 4) the eective drain voltage VD0 S
has been derived by equation 13. Neglecting the
contact voltages the result is shown in Figure 9 and
correlates well with device simulation [1].
0
20
200
ID [A]
1
0
3
0
3
6
9
VD0S [V]
Figure 10: Calculated transfer characteristic of the
inner MOS using the measured data of Figure 5 and
9.
Figure 9: Calculated drain voltage of the inner MOS
using the measured data of Figure 4.
Using the data of Figure 9 and the measured
transfer characteristic (Figure 5), the inner MOS
(Figure 10) and epi (Figure 11) characteristics
have been determined separately for parametrisation used in compact circuit models.
20
200
Summary
Reference
[1] C. H. Kreuzer, N. Krischke, P. Nance: Physically Based Description of Quasi-Saturation Region of Vertical DMOS Power Transistors. International Electron Devices Meeting. Technical
Digest. IEEE: 1996. Pages 489 - 492.
9
ID [A]
The gate-drain capacitance of a power DMOS transistor was measured under high current conditions
of up to 250 A. Depending on VGS a strong nonlinear characteristic was observed. It has been
shown that this characteristic is caused by the DCbehaviour of the inner MOS transistors eective
drain voltage VD0 S . Conversely this internal voltage was determined by capacitance measurements.
Using the measured capacitance data the characteristics of the inner MOS transistor and the epi region
have been determined separately for parameterisation and modelling.
12
100
0
VGS [V]
0
10
20
VEpi [V]
6
3
0
30
Figure 11: Calculated characteristic of the epi region
using the measured data of Figure 5 and 9.