33 × 17, 1.5 Gbps Digital
Crosspoint Switch
AD8150
FEATURES
FUNCTIONAL BLOCK DIAGRAM
INP
INN
CS
RE
A
7
5
FIRST
RANK
17 ×
7-BIT
LATCH
SECOND
RANK
17 ×
7-BIT
LATCH
INPUT
DECODERS
D
33
OUTPUT
ADDRESS
DECODER
33
17
OUTP
33 × 17
DIFFERENTIAL
SWITCH
MATRIX
17
OUTN
AD8150
WE
UPDATE
01074-001
Low cost
33 × 17, fully differential, nonblocking array
>1.5 Gbps per port NRZ data rate
Wide power supply range: +5 V, +3.3 V, −3.3 V, −5 V
Low power
400 mA (outputs enabled)
30 mA (outputs disabled)
PECL and ECL compatible
CMOS/TTL-level control inputs: 3 V to 5 V
Low jitter: <50 ps p-p
No heat sinks required
Drives a backplane directly
Programmable output current
Optimize termination impedance
User-controlled voltage at the load
Minimize power dissipation
Individual output disable for busing and building
Larger arrays
Double row latch
Buffered inputs
Available in 184-lead LQFP
RESET
Figure 1. Functional Block Diagram
500mV
100mV/
DIV
APPLICATIONS
01074-002
HD and SD digital video
Fiber optic network switching
GENERAL DESCRIPTION
–500mV
AD8150 1 is a member of the Xstream line of products and is a
breakthrough in digital switching, offering a large switch array
(33 × 17) on very little power, typically less than 1.5 W.
Additionally, it operates at data rates in excess of 1.5 Gbps per
port, making it suitable for HDTV applications. Further, the
pricing of the AD8150 makes it affordable enough to be used
for SD applications. The AD8150 is also useful for OC-24
optical network switching.
100ps/DIV
Figure 2. Output Eye Pattern, 1.5 Gbps
The AD8150’s flexible supply voltages allow the user to operate
with either PECL or ECL data levels and will operate down to
3.3 V for further power reduction. The control interface is
CMOS/TTL compatible (3 V to 5 V).
Its fully differential signal path reduces jitter and crosstalk while
allowing the use of smaller single-ended voltage swings. The
AD8150 is offered in a 184-lead LQFP package that operates
over the industrial temperature range of 0°C to 85°C.
1
Patent pending.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
AD8150
TABLE OF CONTENTS
Specifications..................................................................................... 3
High Speed Data Outputs (OUTyyP, OUTyyN) .................... 23
Absolute Maximum Ratings............................................................ 4
Output Current Set Pin (REF).................................................. 24
Maximum Power Dissipiation .................................................... 4
Power Supplies ............................................................................ 25
ESD Caution.................................................................................. 4
Power Dissipation....................................................................... 27
Pin Configuration and Function Descriptions............................. 5
Heat Sinking................................................................................ 28
Typical Performance Characteristics ............................................. 9
Applications..................................................................................... 29
Test Circuit ...................................................................................... 13
AD8150 Input and Output Busing........................................... 29
Control Interface............................................................................. 14
Evaluation Board ............................................................................ 30
Control Interface Truth Tables ................................................. 14
Configuration Programming.................................................... 30
Control Interface Timing Diagrams ........................................ 15
Power Supplies ............................................................................ 30
Control Interface Programming Example .............................. 20
Software Installation .................................................................. 30
Control Interface Description................................................... 21
Software Operation .................................................................... 31
Control Pin Description ............................................................ 21
PCB Layout...................................................................................... 32
Control Interface Translators.................................................... 22
Outline Dimensions ....................................................................... 42
Circuit Description......................................................................... 23
Ordering Guide .......................................................................... 42
High Speed Data Inputs (INxxP, INxxN)................................ 23
REVISION HISTORY
9/05—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Change to Absolute Maximum Ratings......................................... 4
Changes to Maximum Power Dissipation Section....................... 4
Change to Figure 3 ........................................................................... 4
Changes to Figure 40...................................................................... 26
Updated Outline Dimensions ....................................................... 42
Changes to Ordering Guide .......................................................... 42
Revision 0: Initial Version
Rev. A | Page 2 of 44
AD8150
SPECIFICATIONS
At 25°C, VCC = 3.3 V to 5 V, VEE = 0 V, RL = 50 Ω (see Figure 25), IOUT = 16 mA, unless otherwise noted.
Table 1
Parameter
DYNAMIC PERFORMANCE
Max Data Rate/Channel (NRZ)
Channel Jitter
RMS Channel Jitter
Propagation Delay
Propagation Delay Match
Output Rise/Fall Time
INPUT CHARACTERISTICS
Input Voltage Swing
Input Voltage Range
Input Bias Current
Input Capacitance
Input VIN High
Input VIN Low
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage Range
Output Current
Output Capacitance
POWER SUPPLY
Operating Range
PECL, VCC
ECL, VEE
VDD
VSS
Quiescent Current
VDD
VEE
THERMAL CHARACTERISTICS
Operating Temperature Range
θJA
LOGIC INPUT CHARACTERISTICS
Input VIN High
Input VIN Low
Conditions
Min
Typ
Max
1.5
Data rate < 1.5 Gbps
VCC = 5 V
Input to output
50
10
650
50
100
20% to 80%
Differential
Common mode
200
VCC − 2
100
1000
VCC
2
2
VCC − 1.2
VCC − 2.4
Differential (see Figure 25)
VCC − 0.2
VCC − 1.4
800
VCC − 1.8
5
VCC
25
2
VEE = 0 V
VCC = 0 V
3.3
−5
3
5
−3.3
5
0
2
400
All outputs enabled, IOUT = 16 mA
TMIN to TMAX
All outputs disabled
450
30
0
Unit
Gbps
ps p-p
ps
ps
ps
ps
mV p-p
V
μA
pF
V
V
mV p-p
V
mA
pF
V
V
V
V
mA
mA
mA
mA
85
°C
°C/W
VDD
0.9
V
V
30
VDD = 3 V dc to 5 V dc
1.9
0
Rev. A | Page 3 of 44
AD8150
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage VDD − VEE
Internal Power Dissipation 1
AD8150 184-Lead Plastic LQFP (ST)
Differential Input Voltage
Output Short-Circuit Duration
Storage Temperature Range 2
2
4.2 W
VCC − VEE
Observe power
derating curves
−65°C to +125°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Specification is for device in free air (TA = 25°C):
184-lead plastic LQFP (ST): θJA = 30°C/W.
Maximum reflow temperatures are to JEDEC industry standard J-STD-020.
6
MAXIMUM POWER DISSIPIATION
While the AD8150 is internally short-circuit protected, this may
not be sufficient to guarantee that the maximum junction
temperature (125°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the
maximum power derating curves shown in Figure 3.
TJ = 150°C
MAXIMUM POWER DISSIPATION (W)
The maximum power that can be safely dissipated by the
AD8150 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for
plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately 125°C.
Temporarily exceeding this limit may cause a shift in
parametric performance due to a change in the stresses exerted
on the die by the package. Exceeding a junction temperature of
125°C for an extended period can result in device failure.
5
4
3
2
1
–10
01074-003
1
Rating
10.5 V
0
10
20
30
40
50
60
AMBIENT TEMPERATURE (°C)
80
Figure 3. Maximum Power Dissipation vs. Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 4 of 44
70
90
AD8150
1
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
180
181
182
179
138 VEE
137 IN12N
PIN 1
INDICATOR
2
3
136 IN12P
135 VEE
4
5
134 IN11N
133 IN11P
6
7
132 VEE
131 IN10N
8
9
130 IN10P
129 VEE
10
11
128 IN09N
127 IN09P
12
13
126 VEE
125 IN08N
14
15
124 IN08P
123 VEE
16
17
122 IN07N
121 IN07P
18
19
120 VEE
119 IN06N
20
21
AD8150
22
184L LQFP
TOP VIEW
(Not to Scale)
23
24
118 IN06P
117 VEE
116 IN05N
115 IN05P
25
114 VEE
113 IN04N
26
27
112 IN04P
111 VEE
28
29
110 IN03N
109 IN03P
30
31
108 VEE
107 IN02N
32
33
106 IN02P
105 VEE
34
35
104 IN01N
103 IN01P
36
37
102 VEE
101 IN00N
38
39
Figure 4. Pin Configuration
Rev. A | Page 5 of 44
VCC
VEEA0
OUT00P
OUT00N
VEE
VEE
01074-004
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
93
55
94
46
54
95
45
53
96
44
52
43
51
97
50
98
42
49
41
48
100 IN00P
99 VEE
47
40
VEE
OUT15N
OUT15P
VEEA15
OUT14N
OUT14P
VEEA14
OUT13N
OUT13P
VEEA13
OUT12N
OUT12P
VEEA12
OUT11N
OUT11P
VEEA11
OUT10N
OUT10P
VEEA10
OUT09N
OUT09P
VEEA9
OUT08N
OUT08P
VEEA8
OUT07N
OUT07P
VEEA7
OUT06N
OUT06P
VEEA6
OUT05N
OUT05P
VEEA5
OUT04N
OUT04P
VEEA4
OUT03N
OUT03P
VEEA3
OUT02N
OUT02P
VEEA2
OUT01N
OUT01P
VEEA1
VEE
IN20P
IN20N
VEE
IN21P
IN21N
VEE
IN22P
IN22N
VEE
IN23P
IN23N
VEE
IN24P
IN24N
VEE
IN25P
IN25N
VEE
IN26P
IN26N
VEE
IN27P
IN27N
VEE
IN28P
IN28N
VEE
IN29P
IN29N
VEE
IN30P
IN30N
VEE
IN31P
IN31N
VEE
IN32P
IN32N
VEE
VCC
VEE
OUT16N
OUT16P
VEEA16
VEE
183
184
VEE
IN19N
IN19P
VEE
IN18N
IN18P
VEE
IN17N
IN17P
VEE
IN16N
IN16P
VEE
VCC
VDD
RESET
CS
RE
WE
UPDATE
A0
A1
A2
A3
A4
D0
D1
D2
D3
D4
D5
D6
VSS
REF
VEEREF
VCC
VEE
IN15N
IN15P
VEE
IN14N
IN14P
VEE
IN13N
IN13P
VEE
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD8150
Table 3. Pin Function Descriptions
Pin No.
1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31,
34, 37, 40, 42, 46, 47, 92, 93, 99, 102,
105, 108, 111, 114, 117, 120, 123,
126, 129, 132, 135, 138, 139, 142,
145, 148, 172, 175, 178, 181, 184
2
3
5
6
8
9
11
12
14
15
17
18
20
21
23
24
26
27
29
30
32
33
35
36
38
39
41, 98, 149, 171
43
44
45
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Mnemonic
VEE
Type
Power supply
Description
Most Negative PECL Supply (common with other points labeled VEE)
IN20P
IN20N
IN21P
IN21N
IN22P
IN22N
IN23P
IN23N
IN24P
IN24N
IN25P
IN25N
IN26P
IN26N
IN27P
IN27N
IN28P
IN28N
IN29P
IN29N
IN30P
IN30N
IN31P
IN31N
IN32P
IN32N
VCC
OUT16N
OUT16P
VEEA16
OUT15N
OUT15P
VEEA15
OUT14N
OUT14P
VEEA14
OUT13N
OUT13P
VEEA13
OUT12N
OUT12P
VEEA12
OUT11N
OUT11P
VEEA11
OUT10N
OUT10P
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
Power supply
PECL
PECL
Power supply
PECL
PECL
Power supply
PECL
PECL
Power supply
PECL
PECL
Power supply
PECL
PECL
Power supply
PECL
PECL
Power supply
PECL
PECL
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
Most Positive PECL Supply (common with other points labeled VCC)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (unique to this output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (unique to this output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (unique to this output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (unique to this output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (unique to this output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (unique to this output)
High Speed Output Complement
High Speed Output
Rev. A | Page 6 of 44
AD8150
Pin No.
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
94
95
96
97
100
101
103
104
106
107
109
110
112
113
115
116
118
119
121
122
124
125
127
128
130
Mnemonic
VEEA10
OUT09N
OUT09P
VEEA9
OUT08N
OUT08P
VEEA8
OUT07N
OUT07P
VEEA7
OUT06N
OUT06P
VEEA6
OUT05N
OUT05P
VEEA5
OUT04N
OUT04P
VEEA4
OUT03N
OUT03P
VEEA3
OUT02N
OUT02P
VEEA2
OUT01N
OUT01P
VEEA1
OUT00N
OUT00P
VEEA0
IN00P
IN00N
IN01P
IN01N
IN02P
IN02N
IN03P
IN03N
IN04P
IN04N
IN05P
IN05N
IN06P
IN06N
IN07P
IN07N
IN08P
IN08N
IN09P
IN09N
IN10P
Type
Power supply
PECL
PECL
Power supply
PECL
PECL
Power supply
PECL
PECL
Power supply
PECL
PECL
Power supply
PECL
PECL
Power supply
PECL
PECL
Power supply
PECL
PECL
Power supply
PECL
PECL
Power supply
PECL
PECL
Power supply
PECL
PECL
Power supply
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
Description
Most Negative PECL Supply (unique to this output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (unique to this output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (unique to this output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (unique to this output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (unique to this output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (unique to this output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (unique to this output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (unique to this output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (unique to this output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (unique to this output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (unique to this output)
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
Rev. A | Page 7 of 44
AD8150
Pin No.
131
133
134
136
137
140
141
143
144
146
147
150
Mnemonic
IN10N
IN11P
IN11N
IN12P
IN12N
IN13P
IN13N
IN14P
IN14N
IN15P
IN15N
VEEREF
Type
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
R-program
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
173
174
176
177
179
180
182
183
REF
VSS
D6
D5
D4
D3
D2
D1
D0
A4
A3
A2
A1
A0
UPDATE
WE
RE
CS
RESET
VDD
IN16P
IN16N
IN17P
IN17N
IN18P
IN18N
IN19P
IN19N
R-program
Power supply
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Power supply
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
Description
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
Connection Point for Output Logic Pull-Down Programming Resistor
(must be connected to VEE)
Connection Point for Output Logic Pull-Down Programming Resistor
Most Negative Control Logic Supply
Enable/DISABLE Output
(32) MSB Input Select
(16)
(8)
(4)
(2)
(1) LSB Input Select
(16) MSB Output Select
(8)
(4)
(2)
(1) LSB Output Select
Second-Rank Program
First-Rank Program
Enable Readback
Enable Chip to Accept Programming
Disable All Outputs (Hi-Z)
Most Positive Control Logic Supply
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
Rev. A | Page 8 of 44
AD8150
TYPICAL PERFORMANCE CHARACTERISTICS
100
100
VEE = –5V (VOH – VOL = 800mV)
VEE = –3.3V (VOH – VOL = 800mV)
80
JITTER (ps)
60
PK-PK
40
20
60
PK-PK
40
20
–0.2
–0.4
–0.6
–0.8
VOH (V)
–1.0
–1.2
0
–1.4
0
Figure 5. Jitter vs. VOH 1.5 Gbps, PRBS 23
–0.2
–1.2
–1.4
JITTER (ps)
80
60
PK-PK
40
20
60
PK-PK
40
–1.5
–1.0
–0.5
0
01074-009
01074-006
20
RMS
RMS
0
–2.0
0.5
–1.5
–1.0
–0.5
0
0.5
VIN (V)
VIN (V)
Figure 6. Jitter vs. VIH 1.5 Gbps, PRBS 23
Figure 9. Jitter vs. VIH 1.5 Gbps, PRBS 23
100
100
VEE = –3.3V
VEE = –5V
80
JITTER (ps)
80
60
40
60
40
PK-PK
PK-PK
20
20
01074-007
JITTER (ps)
–1.0
VEE = –5V (VIH – VIL = 800mV)
VEE = –3.3V (VIH – VIL = 800mV)
RMS
0
0.1
–0.6
–0.8
VOH (V)
100
80
JITTER (ps)
–0.4
Figure 8. Jitter vs. VOH 1.5 Gbps, PRBS 23
100
0
–2.0
01074-008
0
0
RMS
01074-005
RMS
0.3
0.5
0.7
0.9
DATA RATE (Gbps)
1.1
1.3
01074-010
JITTER (ps)
80
RMS
0
0.1
1.5
Figure 7. Jitter vs. Data Rate, PRBS 23
0.3
0.5
0.7
0.9
DATA RATE (Gbps)
1.1
Figure 10. Jitter vs. Data Rate, PRBS 23
Rev. A | Page 9 of 44
1.3
1.5
AD8150
100
100
VEE = –3.3V
VEE = –5V
80
JITTER (ps)
60
PK-PK
40
20
60
PK-PK
40
20
5
10
15
20
0
25
0
5
10
IOUT (mA)
20
25
Figure 14. Jitter vs. IOUT 1.5 Gbps, PRBS 23
100
100
VEE = –3.3V
VEE = –5V
80
JITTER (ps)
80
60
PK-PK
40
20
60
PK-PK
40
20
0
–25
0
RMS
01074-012
RMS
25
50
75
TEMPERATURE (°C)
100
0
–25
125
Figure 12. Jitter vs. Temperature 1.5 Gbps, PRBS 23
0
01074-015
JITTER (ps)
15
IOUT (mA)
Figure 11. Jitter vs. IOUT 1.5 Gbps, PRBS 23
25
50
75
TEMPERATURE (°C)
100
125
Figure 15. Jitter vs. Temperature 1.5 Gbps, PRBS 23
100
100
80
80
VOLTAGE (INNER EYE)
VOLTAGE (INNER EYE)
TIME DOMAIN
TIME DOMAIN
PERCENT
60
VEE = –3.3V
40
223–1 PSEUDO-RANDOM BIT STREAM, ERROR-FREE AREA
ERROR-FREE PERCENTAGE VALUE WAS COMPUTED
USING THE FOLLOWING FORMULA:
(DATA_PERIOD – PPJITTER) × 100 / DATA_PERIOD
TIME DOMAIN
VINNER 100 / VINNER @500Mbps
VOLTAGE (INNER EYE)
20
0
0
500
1000
DATA RATE (Mbps)
60
VEE = –5V
40
223–1 PSEUDO-RANDOM BIT STREAM, ERROR-FREE AREA
ERROR-FREE PERCENTAGE VALUE WAS COMPUTED
USING THE FOLLOWING FORMULA:
(DATA_PERIOD – PPJITTER) × 100 / DATA_PERIOD
TIME DOMAIN
VINNER 100 / VINNER @500Mbps
VOLTAGE (INNER EYE)
20
01074-013
PERCENT
01074-014
0
0
RMS
01074-011
RMS
1500
Figure 13. AC Performance
0
0
500
1000
DATA RATE (Mbps)
Figure 16. AC Performance
Rev. A | Page 10 of 44
01074-016
JITTER (ps)
80
1500
100
150
80
100
PROPAGTION DELAY (ps)
60
40
600
620
640
660
DELAY (ps)
680
700
–100
–25
710
0
25
50
TEMPERATURE (°C)
75
100
Figure 20. Propagation Delay, Normalized at 25°C vs. Temperature
100
16.5
80
JITTER (ps)
17.0
16.0
15.5
60
PK-PK
40
20
15.0
RMS
01074-018
14.5
–3.3
01074-020
01074-017
580
Figure 17. Variation in Channel-to-Channel Delay, All 561 Points
IOUT (mA)
0
–50
20
0
560
50
–3.6
–3.9
–4.2
–4.7
0
3.0
–5.0
VEE (V)
Figure 18. IOUT vs. Supply, VEE
01074-021
FREQUENCY
AD8150
3.5
4.0
4.5
SUPPLY VOLTAGE (VCC, VEE)
5.0
Figure 21. Jitter vs. Supply 1.5 Gbps, PRBS 23
1V
1V
–1V
200ps/DIV
01074-022
01074-019
200mV/DIV
87.11 RISE
87.36 FALL
20% PROXIMAL
80% DISTAL
200mV/DIV
95.55 RISE
96.32 FALL
20% PROXIMAL
80% DISTAL
–1V
200ps/DIV
Figure 19. Rise/Fall Times, VEE = −3.3 V
Figure 22. Rise/Fall Times, VEE = −5 V
Rev. A | Page 11 of 44
AD8150
–500mV
200ps/DIV
01074-025
01074-023
100mV/DIV
500mV
100mV/DIV
500mV
–500mV
100ps/DIV
Figure 23. Eye Pattern, VEE = −3.3 V, 1.5 Gbps PRBS 23
Figure 24. Eye Pattern, VEE = −5 V, 1.5 Gbps PRBS 23
Rev. A | Page 12 of 44
AD8150
TEST CIRCUIT
VCC
1.65kΩ
VTT
AD8150
P
RL = 50Ω
TEKTRONIX
11801B
P
50Ω
105Ω
IN
OUT
N
N
SD22
SAMPLING
HEAD
50Ω
RL = 50Ω
1.65kΩ
VEE
VEE
01074-024
HP8133A
PRBS
GENERATOR
VCC
VTT
VCC = 0V, VEE = –3.3V OR –5V, VTT = –1.6V
RSET = 1.54kΩ, IOUT = 16mA, VOH = –0.8V, VOL = –1.8V
INTRINSIC JITTER OF HP8133A AND TEKTRONIX 11801B = 3ps RMS, 17ps PK-PK
Figure 25. Eye Pattern Test Circuit
Rev. A | Page 13 of 44
AD8150
CONTROL INTERFACE
CONTROL INTERFACE TRUTH TABLES
The following are truth tables for the control interface.
Table 4. Basic Control Functions
RESET
Control Pins
CS WE RE
UPDATE
Function
0
1
X
1
X
X
X
X
X
X
1
0
0
X
X
1
0
X
0
X
1
0
X
X
0
1
0
0
1
0
Global Reset. Reset all second-rank enable bits to 0 (disable all outputs).
Control Disable. Ignore all logic (but the signal matrix still functions as programmed). D[6:0] are high
impedance.
Single Output Preprogram. Write input configuration data from Data Bus D[6:0] into first rank of
latches for the output selected by the Output Address Bus A[4:0].
Single Output Readback. Readback input configuration data from second rank of latches onto Data
Bus D[6:0] for the single output selected by the Output Address Bus A[4:0].
Global Update. Copy input configuration data from all 17 first-rank latches into second rank of
latches, updating signal matrix connections for all outputs.
Transparent Write and Update. It is possible to write data directly onto rank two. This simplifies logic
when synchronous signal matrix updating is not necessary.
Table 5. Address Data Examples
Output Address Pins
MSB to LSB
A4 A3 A2 A1 A0
0
0
0
0
0
Enable
Bit
D5
0
Input Address Pins
MSB to LSB
D4 D3 D2 D1
0
0
0
0
D6/E
X
D0
0
1
X
1
0
0
<Binary Output Number 1>
1
<Binary Input Number>
<Binary Output Number1>
1
0
0
0
1
0
X
X
X
X
X
X
<Binary Input Number>
X
1
X
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Function
Lower Address/Data Range. Connect Output 00
(A[4:0] = 00000) to Input 00 (D[5:0] = 000000).
Upper Address/Data Range. Connect Output 16
(A[4:0] = 10000) to Input 32 (D[5:0] = 100000).
Enable Output. Connect selected output (A[4:0] = 0 to 16) to
designated input (D[5:0] = 0 to 32) and enable output
(D6 = 1).
Disable Output. Disable specified output (D6 = 0).
Broadcast Connection. Connect all 17 outputs to the same
designated input and set all 17 enable bits to the value of
D6. Readback is not possible with the broadcast address.
Reserved. Any address or data code greater or equal to these
are reserved for future expansion or factory testing.
The binary output number may also be the broadcast connection designator, 10001X.
Rev. A | Page 14 of 44
AD8150
CONTROL INTERFACE TIMING DIAGRAMS
CS INPUT
WE INPUT
A[4:0] INPUTS
D[6:0] INPUTS
tCSW
tCHW
tASW
tAHW
tWP
01074-026
tDSW
tDHW
Figure 26. First-Rank Write Cycle
Table 6. First-Rank Write Cycle
Symbol
tCSW
tASW
tDSW
tCHW
tAHW
tDHW
tWP
Parameter
Setup Time
Chip select to write enable
Address to write enable
Data to write enable
Hold Time
Chip select from write enable
Address from write enable
Data from write enable
Width of Write Enable Pulse
Rev. A | Page 15 of 44
Conditions
TA = 25°C
VDD = 5 V
VCC = 5 V
Min
0
0
15
0
0
0
15
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
AD8150
CS INPUT
UPDATE INPUT
ENABLING
OUT[0:16][N:P]
OUTPUTS
TOGGLE
OUT[0:16][N:P]
OUTPUTS
DISABLING
OUT[0:16][N:P]
OUTPUTS
DATA FROM RANK 1
PREVIOUS RANK 2 DATA
DATA FROM RANK 1
DATA FROM RANK 2
tCSU
tUW
tCHU
tUOE
01074-027
tUOD
tUOT
Figure 27. Second-Rank Update Cycle
Table 7. Second-Rank Update Cycle
Symbol
tCSU
tCHU
tUOE
tUOT
tUOD
tUW
Setup Time
Hold Time
Output Enable Times
Output Toggle Times
Output Disable Times
Width of Update Pulse
Parameter
Chip select to update
Chip select from update
Update to output enable
Update to output reprogram
Update to output disabled
Conditions
TA = 25°C
VDD = 5 V
VCC = 5 V
Min
0
0
15
Rev. A | Page 16 of 44
Typ
Max
25
25
25
40
40
30
Unit
ns
ns
ns
ns
ns
ns
AD8150
CS INPUT
UPDATE INPUT
WE INPUT
ENABLING
OUT[0:16][N:P]
OUTPUTS
INPUT {DATA 0}
INPUT {DATA 2}
INPUT {DATA 1}
tCSU
tCHU
tUW
tUOT
tWOT
tUOE
tWOD
tWHU
01074-028
DISABLING
OUT[0:16][N:P]
OUTPUTS
INPUT {DATA 1}
Figure 28. First-Rank Write Cycle and Second-Rank Update Cycle
Table 8. First-Rank Write Cycle and Second-Rank Update Cycle
Symbol
tCSU
tCHU
tUOE
tWOE 1
tUOT
tWOT
tUOD1
tWOD
tWHU
tUW
1
Setup Time
Hold Time
Output Enable Times
Output Toggle Times
Output Disable Times
Setup Time
Width of Update Pulse
Parameter
Chip select to update
Chip select from update
Update to output enable
Write enable to output enable
Update to output reprogram
Write enable to output reprogram
Update to output disabled
Write enable to output disabled
Write enable to update
Not shown.
Rev. A | Page 17 of 44
Conditions
TA = 25°C
VDD = 5 V
VCC = 5 V
Min
0
0
10
15
Typ
Max
25
25
25
25
25
25
40
40
30
30
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AD8150
CS INPUT
RE INPUT
ADDR 1
D[6:0]
OUTPUTS
ADDR 2
DATA
{ADDR 1}
tCSR
tRDE
DATA
{ADDR 2}
tCHR
tAA
tRHA
tRDD
01074-029
A[4:0]
INPUTS
Figure 29. Second-Rank Readback Cycle
Table 9. Second-Rank Readback Cycle
Symbol
tCSR
tCHR
tRHA
tRDE
tAA
tRDD
Setup Time
Hold Time
Enable Time
Access Time
Release Time
Parameter
Chip select to read enable
Chip select from read enable
Address from read enable
Data from read enable
Data from address
Data from read enable
Rev. A | Page 18 of 44
Conditions
TA = 25°C
VDD = 5 V
VCC = 5 V
10 kΩ
20 pF on D[6:0]
Bus
Min
0
0
5
Typ
Max
15
15
15
30
Unit
ns
ns
ns
ns
ns
ns
AD8150
RESET INPUT
DISABLING
OUT[0:16][N:P]
OUTPUTS
01074-030
tTOD
tTW
Figure 30, Asynchronous Reset
Table 10. Asynchronous Reset
Symbol
tTOD
tTW
Disable Time
Width of Reset Pulse
Parameter
Output disable from reset
Rev. A | Page 19 of 44
Conditions
TA = 25°C
VDD = 5 V
VCC = 5 V
Min
15
Typ
25
Max
30
Unit
ns
ns
AD8150
CONTROL INTERFACE PROGRAMMING EXAMPLE
The following conservative pattern connects all outputs to Input 7, except Output 16, which is connected to Input 32. The vector clock
period, T0, is 15 ns. It is possible to accelerate the execution of this pattern by deleting Vectors 1, 4, 7, and 9.
Table 11. Basic Test Pattern
Vector No.
RESET
CS
WE
RE
UPDATE
A[4:0]
D[6:0]
Comments
0
1
2
3
4
5
6
7
8
9
10
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
xxxxx
xxxxx
10001
10001
10001
10000
10000
10000
xxxxx
xxxxx
xxxxx
xxxxxxx
xxxxxxx
1000111
1000111
1000111
1100000
1100000
1100000
xxxxxxx
xxxxxxx
xxxxxxx
Disable all outputs
7
UPDATE RESET
D[0:6]
7
7
7
7
7
7
7
7
0
0
1
1
2
2
16
16
RANK1
RANK 2
7
All outputs to Input 07
Write to first rank
Output 16 to Input 32
Write to first rank
Transfer to second rank
Disable interface
TO 17 × 33
SWITCH
MATRIX
33
7
7
7
33
7
7
33
7
7
33
17 ROWS OF 7-BIT
LATCHES
1 OF 33
DECODERS
1 OF 17 DECODERS
A[0:4]
RE
Figure 31. Control Interface (Simplified Schematic)
Rev. A | Page 20 of 44
01074-031
WE
AD8150
CONTROL INTERFACE DESCRIPTION
CONTROL PIN DESCRIPTION
The AD8150 control interface receives and stores the desired
connection matrix for the 33 input and 17 output signal pairs.
The interface consists of 17 rows of double-rank 7-bit latches,
one row for each output. The 7-bit data-word stored in each of
these latches indicates to which (if any) of the 33 inputs the
output will be connected.
A[4:0] Inputs
One output at a time can be preprogrammed by addressing the
output and writing the desired connection data into the first
rank of latches. This process can be repeated until each of the
desired output changes has been preprogrammed. All output
connections can then be programmed at once by passing the
data from the first rank of latches into the second rank. The
output connections always reflect the data programmed into the
second rank of latches and do not change until the first rank of
data is passed into the second rank.
Input configuration data pins. In write mode, the binary
encoded data applied to Pins D[6:0] determine which one of 33
inputs is to be connected to the output specified with the A[4:0]
pins. The most significant bit is D5, and the least significant bit
is D0. Bit D6 is the enable bit, setting the specified output signal
pair to an enabled state if D6 is logic high, or to a disabled state,
high impedance, if D6 is logic low.
If necessary for system verification, the data in the second rank
of latches can be read back from the control interface.
At any time, a reset pulse can be applied to the control interface
to globally reset the appropriate second-rank data bits, disabling
all 17 signal output pairs. This feature can be used to avoid
output bus contention on system start-up. The contents of the
first rank remain unchanged.
The control interface pins are connected via logic-level
translators. These translators allow programming and readback
of the control interface using logic levels different from those in
the signal matrix.
To facilitate multiple chip address decoding, there is a chipselect pin. All logic signals except the reset pulse are ignored
unless the chip-select pin is active. The chip-select pin disables
only the control logic interface and does not change the
operation of the signal matrix. The chip-select pin does not
power down any of the latches, so any data programmed in the
latches is preserved.
All control pins are level-sensitive, not edge-triggered.
Output address pins. The binary encoded address applied to
these five input pins determines which one of the 17 outputs is
being programmed (or being read back). The most significant
bit is A4.
D[6:0] Inputs/Outputs
In readback mode, Pins D[6:0] are low impedance outputs,
indicating the data-word stored in the second rank for the
output specified with the A[4:0] pins. The readback drivers
were designed to drive high impedances only, so external
drivers connected to D[6:0] should be disabled during readback
mode.
WE Input
First-rank write enable. Forcing this pin to logic LOW allows
the data on Pins D[6:0] to be stored in the first-rank latch for
the output specified by Pins A[4:0]. The WE pin must be
returned to a logic high state after a write cycle to avoid
overwriting the first-rank data.
UPDATE Input
Second-rank write enable. Forcing this pin to logic low allows
the data stored in all 17 first-rank latches to be transferred to
the second-rank latches. The signal connection matrix will be
reprogrammed when the second-rank data is changed. This is a
global pin, transferring all 17 rows of data at once. It is not
necessary to program the address pins. It should be noted that
after initial power-up of the device, the first-rank data is
undefined. It may be desirable to preprogram all seventeen
outputs before performing the first update cycle.
Rev. A | Page 21 of 44
AD8150
RE Input
Second-rank read enable. Forcing this pin to logic low enables
the output drivers on the bidirectional D[6:0] pins, entering the
readback mode of operation. By selecting an output address
with the A[4:0] pins and forcing RE to logic low, the 7-bit data
stored in the second-rank latch for that output address will be
written to the D[6:0] pins. Data should not be written to the
D[6:0] pins externally while in readback mode. The RE and WE
pins are not exclusive and may be used at the same time, but
data should not be written to the D[6:0] pins from external
sources while in readback mode.
CS Input
Chip select. This pin must be forced to logic low to program or
receive data from the logic interface, with the exception of the
RESET pin, described below. This pin has no effect on the
signal pairs and does not alter any of the stored control data.
RESET Input
Global output disable pin. Forcing the RESET pin to logic low
will reset the enable bit, D6, in all 17 second-rank latches,
regardless of the state of any other pins. This has the effect of
immediately disabling the 17 output signal pairs in the matrix.
It is useful to momentarily hold RESET at a logic low state when
powering up the AD8150 in a system that has multiple output
signal pairs connected together. Failure to do this may result in
several signal outputs contending after power-up. The reset pin
is not gated by the state of the chip-select pin, CS. It should be
noted that the RESET pin does not program the first rank,
which will contain undefined data after power-up.
CONTROL INTERFACE TRANSLATORS
The AD8150 control interface has two supply pins, VDD and VSS.
The potential between the positive logic supply VDD and the
negative logic supply VSS must be at least 3 V and no more than
5 V. Regardless of supply, the logic threshold is approximately
1.6 V above VSS, allowing the interface to be used with most
CMOS and TTL logic drivers.
The signal matrix supplies, VCC and VEE, can be set independent
of the voltage on VDD and VSS, with the constraints that (VDD −
VEE) ≤ 10 V. These constraints will allow operation of the
control interface on 3 V or 5 V while the signal matrix is
operated on 3.3 V or 5 V PECL, or on −3.3 V or −5 V ECL.
Rev. A | Page 22 of 44
AD8150
CIRCUIT DESCRIPTION
resistors (RL) in the differential termination scheme are needed
to bias the emitter followers of the ECL source.
VCC
01074-032
INxxN
VEE
INxxN
ZO
ZO
INxxP
ECL SOURCE
ZO
INxxP
ZO
ECL SOURCE
Figure 32. Simplified Input Circuit
To maintain signal fidelity at the high data rates supported by
the AD8150, the input transmission lines should be terminated
as close to the input pins as possible. The preferred input
termination structure will depend primarily on the application
and the output circuit of the data source. Standard ECL
components have open emitter outputs that require pull-down
resistors. Three input termination networks suitable for this
type of source are shown in Figure 33. The characteristic
impedance of the transmission line is shown as ZO. The
resistors, R1 and R2, in the Thevenin termination are chosen to
synthesize a VTT source with an output resistance of ZO and an
open-circuit output voltage equal to VCC − 2 V. The load
R2
VTT = VCG2V
R2
VEE
(a)
(b)
VCC
ZO
INxxN
ZO
2ZO
INxxP
RL
RL
ECL SOURCE
(c)
VCC
R1
INxxN
VEE
The AD8150 has 33 pairs of differential voltage-mode inputs.
The common-mode input range extends from the positive
supply voltage (VCC) down to include standard ECL or PECL
input levels (VCC − 2 V). The minimum differential input
voltage is less than 300 mV. Unused inputs may be connected
directly to any level within the allowed common-mode input
range. A simplified schematic of the input circuit is shown in
Figure 32.
VCC – 2V
ZO R1
ZO
HIGH SPEED DATA INPUTS (INxxP, INxxN)
INxxP
VCC
01074-033
The AD8150 is a high speed 33 × 17 differential crosspoint
switch designed for data rates up to 1.5 Gbps per channel. The
AD8150 supports PECL-compatible input and output levels
when operated from a 5 V supply (VCC = 5 V, VEE = GND) or
ECL-compatible levels when operated from a −5 V supply (VCC
= GND, VEE = −5 V). To save power, the AD8150 can run from
a 3.3 V supply to interface with low voltage PECL circuits or a
−3.3 V supply to interface with low voltage ECL circuits. The
AD8150 utilizes differential current-mode outputs with
individual disable control, which facilitates busing together the
outputs of multiple AD8150s to assemble larger switch arrays.
This feature also reduces the system to assemble larger switch
arrays, reduces system crosstalk, and can greatly reduce power
dissipation in a large switch array. A single external resistor
programs the current for all enabled output stages, allowing for
user control over output levels with different output
termination schemes and transmission line characteristic
impedances.
Figure 33. AD8150 Input Termination from ECL/PECL Sources: a) Parallel
Termination Using VTT Supply; b) Thevenin Equivalent Termination; and
c) Differential Termination
If the AD8150 is driven from a current-mode output stage such
as another AD8150, the input termination should be chosen to
accommodate that type of source, as explained in the following
section.
HIGH SPEED DATA OUTPUTS (OUTyyP, OUTyyN)
The AD8150 has 17 pairs of differential current-mode outputs.
The output circuit, shown in Figure 34, is an open-collector NPN
current switch with resistor-programmable tail current and output
compliance extending from the positive supply voltage (VCC)
down to standard ECL or PECL output levels (VCC − 2 V). The
outputs may be disabled individually to permit outputs from
multiple AD8150’s to be connected directly. Since the output
currents of multiple enabled output stages connected in this
way sum, care should be taken to ensure that the output
compliance limit is not exceeded at any time; this can be
achieved by disabling the active output driver before enabling
an inactive driver.
Rev. A | Page 23 of 44
AD8150
VCC
OUTyyP
maintain signal fidelity at high data rates, the stubs connecting
the output pins to the output transmission lines or load resistors
should be as short as possible.
OUTyyN
VCC – 2V
VCC
RCOM
AD8150
IOUT
AD8150
01074-034
VEE
VEE
ZO
RL
ZO
RL
RECEIVER
Figure 36. Double Termination of AD8150 Outputs
In this case, the output levels are:
VOH = VCOM − (1 4 ) I OUT R L
VOL = VCOM − (3 4 ) I OUT R L
VSWING = VOH − VOL = (1 2 ) I OUT R L
VCC
VCOM
OUTPUT CURRENT SET PIN (REF)
DCOM
RL
AD8150
OUTyyN
OUTyyN
OUTyyP
OUTyyP
RL
VCOM
RL
01074-035
RCOM
RL
ZO
OUTyyP
To ensure proper operation, all outputs (including unused
output) must be pulled high, using external pull-up networks,
to a level within the output compliance range. If outputs from
multiple AD8150s are wired together, a single pull-up network
may be used for each output bus. The pull-up network should
be chosen to keep the output voltage levels within the output
compliance range at all times. Recommended pull-up networks
to produce PECL/ECL 100K- and 10K-compatible outputs are
shown in Figure 35. Alternatively, a separate supply can be used
to provide VCOM, making RCOM and DCOM unnecessary.
AD8150
ZO
OUTyyN
Figure 34. Simplified Output Circuit
VCC
RL
01074-036
DISABLE
VCOM
RL
OUTyyN
OUTyyP
Figure 35. Output Pull-Up Networks: a) ECL 100K, b) ECL 10K
The output levels are simply:
VOH = VCOM
A simplified schematic of the reference circuit is shown in
Figure 37. A single external resistor connected between the
REF pin and VEE determines the output current for all output
stages. This feature allows a choice of pull-up networks and
transmission line characteristic impedances while still achieving
a nominal output swing of 800 mV. At low data rates, substantial
power savings can be achieved by using lower output swings
and higher load resistances.
VOL = VCOM − I OUT R L
AD8150
IOUT/25
VCC
VSWING = VOH − VOL = I OUT R L
VCOM = VCC − V (D COM ) (10K Mode )
1.25V
REF
RSET
The common-mode adjustment element (RCOM or DCOM) may be
omitted if the input range of the receiver includes the positive
supply voltage. The bypass capacitors reduce common-mode
perturbations by providing an ac short from the common nodes
(VCOM) to ground.
When busing together the outputs of multiple AD8150s or
when running at high data rates, double termination of its
outputs is recommended to mitigate the impact of reflections
due to open transmission line stubs and the lumped capacitance
of the AD8150 output pins. A possible connection is shown in
Figure 36; the bypass capacitors provide an ac short from the
common nodes of the termination resistors to ground. To
Rev. A | Page 24 of 44
VEE
Figure 37. Simplified Reference Circuit
01074-037
VCOM = VCC − I OUT R COM (100K Mode )
AD8150
The resistor value current is given by the following expression:
25
I OUT
Example:
R SET = 1.54 kΩ for I OUT = 16.2 mA
3V TO 5V
The minimum set resistor is RSET,min = 1 kΩ, resulting in IOUT,max =
25 mA. The maximum set resistor is RSET,max = 5 kΩ, resulting in
IOUT,min = 5 mA. Nominal 800 mV output swings can be achieved
in a 50 Ω load using RSET = 1.56 kΩ (IOUT = 16.2 mA) or in a
doubly terminated 75 Ω load using RSET = 1.17 kΩ (IOUT =
21.3 mA).
GND
0.1μF
VDD
VCC
AD8150
CONTROL
LOGIC
VSS
To minimize stray capacitance and avoid the pickup of
unwanted signals, the external set resistor should be located
close to the REF pin. Bypassing the set resistor is not
recommended.
DATA
PATHS
VEE
0.1μF
(ONE FOR EVERY TWO VEE PINS)
01074-038
GND
3V TO 5V
Figure 38. Power Supplies and Bypassing for ECL Operation
POWER SUPPLIES
There are several options for the power supply voltages for the
AD8150, because there are two separate sections of the chip that
require power supplies. These are the control logic and the high
speed data paths. The voltage levels of these supplies can vary,
depending on the system architecture.
Logic Supplies
The control (programming) logic is CMOS and is designed to
interface with any of the various standard single-ended logic
families (CMOS or TTL). Its supply voltage pins are VDD (Pin
170, logic positive) and VSS (Pin 152, logic ground). In all cases
the logic ground should be connected to the system digital
ground. VDD should be supplied at a voltage between 3.3 V and
5 V to match the supply voltage of the logic family that is used
to drive the logic inputs. VDD should be bypassed to ground
with a 0.1 μF ceramic capacitor. The absolute maximum voltage
from VDD to VSS is 5.5 V.
If the data paths are to be dc-coupled to other ECL logic devices
that run with ground as the most positive supply and a negative
voltage for VEE, then this is the proper way to run. However, if
the part is to be ac coupled, it is not necessary to have the
input/output common mode at the same level as the other
system circuits, but it will probably be more convenient to use
the same supply rails for all devices.
For PECL operation, VEE will be at ground potential, and VCC
will be a positive voltage from 3.3 V to 5 V. Thus, the common
mode of the inputs and outputs will be at a positive voltage.
These can then be dc coupled to other PECL operated devices.
If the data paths are ac coupled, then the common-mode levels
do not matter, see Figure 39.
3V TO 5V
0.1μF
VDD
Data Path Supplies
3V TO 5V
VCC
0.1μF
(ONE FOR EACH VCC PIN,
4 REQUIRED)
AD8150
The data path supplies have more options for their voltage
levels. The choices here will affect several other areas, such as
power dissipation, bypassing, and common-mode levels of the
inputs and outputs. The more positive voltage supply for the
data paths is VCC (Pins 41, 98, 149, and 171). The more negative
supply is VEE, which appears on many pins that will not be listed
here. The maximum allowable voltage across these supplies is
5.5 V.
Rev. A | Page 25 of 44
CONTROL
LOGIC
VSS
GND
DATA
PATHS
VEE
GND
01074-039
RSET =
The first choice in the data path power supplies is to decide
whether to run the device as ECL (emitter-coupled logic) or
PECL (positive ECL). For ECL operation, VCC will be at ground
potential, and VEE will be at a negative supply between −3.3 V
and −5 V. This will make the common-mode voltage of the
inputs and outputs a negative voltage (see Figure 38).
Figure 39. Power Supplies and Bypassing for PECL Operation
VCC
VEE
VEE
VEE
139
131
9
130
10
129
11
128
12
127
13
126
14
125
15
124
16
123
17
122
18
121
19
120
20
119
21
AD8150
118
22
184L LQFP
TOP VIEW
(Not to Scale)
117
23
24
116
115
Figure 40. Bypassing Schematic
Rev. A | Page 26 of 44
VCC
VEE
VEE
OUT00P C60
OUT00N 0.01μF
VEE
VEE
92
91
90
89
88
87
86
85
84
83
82
93
81
94
46
80
95
45
79
96
44
78
43
77
97
76
98
42
75
99
41
74
100
40
73
101
39
72
102
38
71
103
37
70
104
36
69
105
35
68
106
34
67
107
33
66
108
32
65
109
31
64
110
30
63
111
29
62
112
28
61
113
27
60
114
26
59
25
VEE
IN12N
IN12P
VEE
IN11N
IN11P
VEE
IN10N
IN10P
VEE
IN09N
IN09P
VEE
IN08N
IN08P
VEE
IN07N
IN07P
VEE
IN06N
IN06P
VEE
IN05N
IN05P
VEE
IN04N
IN04P
VEE
IN03N
IN03P
VEE
IN02N
IN02P
VEE
IN01N
IN01P
VEE
IN00N
IN00P
VEE
01074-050
140
IN13N
IN13P
141
142
143
IN14N
IN14P
144
IN15N
IN15P
145
146
148
149
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
VDD
RESET
CS
RE
WE
UPDATE
A0
A1
A2
A3
A4
D0
D1
D2
D3
D4
D5
D6
168
169
170
171
172
173
IN16N
IN16P
174
175
176
IN17N
IN17P
177
178
179
147
VCC
VEE
180
181
IN18N
IN18P
VEE
IN19N
IN19P
132
8
58
OUT16N
OUT16P
VEE
VEE
133
7
57
VEE
134
6
56
C15
0.01μF
135
55
VCC
136
54
C11
0.01μF
137
53
VEE
C30
0.01μF
138
52
C32
0.01μF
IN22P
IN22N
VEE
IN23P
IN23N
VEE
IN24P
IN24N
VEE
IN25P
IN25N
VEE
IN26P
IN26N
VEE
IN27P
IN27N
VEE
IN28P
IN28N
VEE
IN29P
IN29N
VEE
IN30P
IN30N
VEE
IN31P
IN31N
VEE
IN32P
IN32N
VCC
5
51
VCC
C14
0.01μF
4
50
VEE
C10
0.01μF
3
49
IN21P
IN21N
VDD
PIN 1
INDICATOR
2
48
VEE
1
47
VEE
IN20P
IN20N
VCC
VEE
VEE
OUT15N
OUT15P
VEE
OUT14N
OUT14P
VEE
OUT13N
OUT13P
VEE
OUT12N
OUT12P
VEE
OUT11N
OUT11P
VEE
OUT10N
OUT10P
VEE
OUT09N
OUT09P
VEE
OUT08N
OUT08P
VEE
OUT07N
OUT07P
VEE
OUT06N
OUT06P
VEE
OUT05N
OUT05P
VEE
OUT04N
OUT04P
VEE
OUT03N
OUT03P
VEE
OUT02N
OUT02P
VEE
OUT01N
OUT01P
VEE
C31
0.01μF
VCC
182
184
C29
0.01μF
R203
1.5kΩ
C13
0.01μF
183
VCC
C9
0.01μF
C7
0.01μF
C4
0.01μF
VEE
VCC
VSS
VEE
C5
0.01μF
VCC
C8
0.01μF
C6
0.01μF
VEE
VCC
VCC
C12
0.01μF
VCC
150
VEE
VEE
VCC
VEE
AD8150
AD8150
POWER DISSIPATION
For analysis, the power dissipation of the AD8150 can be
divided into three separate parts. These are the control logic,
the data path circuits, and the (ECL or PECL) outputs, which
are part of the data path circuits, but can be dealt with
separately. The first of these, the control logic, is CMOS
technology and does not dissipate a significant amount of
power. This power will, of course, be greater when the logic
supply is 5 V than when it is 3 V, but overall it is not a significant
amount of power and can be ignored for thermal analysis.
This says that there will always be a minimum of 30 mA
flowing. ICC will increase by a factor that is proportional to both
the number of enabled outputs and the programmed output
current.
The power dissipated in this circuit section will simply be the
voltage of this section (VCC − VEE) times the current. For a worst
case, assume that VCC − VEE is 5.0 V, all outputs are enabled and
the programmed output current is 25 mA. The power dissipated
by the data path logic will be
[
= 826 mW
ROUT
AD8150
]
P = 5.0 V {25 mA + 4.5 mA + (25 mA 20 mA × 3 mA ) × 17}
VCC
VDD
IOUT
DATA
PATHS
CONTROL
LOGIC
I, DATA PATH
LOGIC
VEE
GND
01074-040
VSS
VOUT LOW – VEE
GND
Figure 41. Major Power Consumption Paths
The data path circuits operate between the supplies VCC and
VEE. As described in the power supply section, this voltage can
range from 3.3 V to 5 V. The current consumed by this section
will be constant, so operating at a lower voltage can save about
40 percent in power dissipation.
The power dissipated in the data path outputs is affected by
several factors. The first is whether the outputs are enabled or
disabled. The worst case occurs when all of the outputs are
enabled. The current consumed by the data path logic can be
approximated by
[
]
I CC = 30 mA + 4.5 mA + (I OUT 20 mA × 3 mA )
× (# of outputs enabled )
The power dissipated by the output current depends on several
factors. These are the programmed output current, the voltage
drop from a logic low output to VEE, and the number of enabled
outputs. A simplifying assumption is that one of each (enabled)
differential output pair will be low and draw the full output
current (and dissipate most of the power for that output), while
the complementary output of the pair will be high and draw
insignificant current. Thus, the power dissipation of the high
output can be ignored, and the output power dissipation for
each output can be assumed to occur in a single static low
output that sinks the full output-programmed current.
The voltage across which this current flows can also vary,
depending on the output circuit design and the supplies that are
used for the data path circuitry. In general, however, there will
be a voltage difference between a logic low signal and VEE. This
is the drop across which the output current flows. For a worst
case, this voltage can be as high as 3.5 V. Thus, for all outputs
enabled and the programmed output current set to 25 mA, the
power dissipated by the outputs is
P = 3.5 V (25 mA ) × 17 = 1.49 W
Rev. A | Page 27 of 44
AD8150
HEAT SINKING
Depending on several factors in its operation, the AD8150 can
dissipate 2 W or more. The part is designed to operate without
the need for an explicit external heat sink. However, the package
design offers enhanced heat removal via some of the package
pins to the PC board traces.
The VEE pins on the input sides of the package (Pins 1 to 46 and
Pins 93 to 138) have finger extensions inside the package that
connect to the paddle on which the IC chip is mounted. These
pins provide a lower thermal resistance from the IC to the VEE
pins than pins that just have a bond wire. As a result, these pins
can be used to enhance the heat removal process from the IC to
the circuit board and ultimately to the ambient.
The VEE pins described above should be connected to a large
area of circuit board trace material to take the most advantage
of their lower thermal resistance. If there is a large area available
on an inner layer that is at VEE potential, then vias can be
provided from the package pin traces to this layer. There should
be no thermal-relief pattern when connecting the vias to the
inner layers for these VEE pins. Additional vias in parallel and
close to the pin leads can provide an even lower thermal
resistive path. If possible to use, 2 oz. copper foil will provide
better heat removal than 1 oz.
The AD8150 package has a specified thermal impedance, θJA, of
30°C/W. This is the worst case still-air value that can be
expected when the circuit board does not significantly enhance
the heat removal from the package. By using the concept
described above or by using forced-air circulation, the thermal
impedance can be lowered.
For an extreme worst case analysis, the junction rise above the
ambient can be calculated assuming 2 W of power dissipation
and θJA of 30°C/W to yield a 60°C rise above the ambient. There
are many techniques described above that can mitigate this
situation. Most actual circuits will not result in such a high rise
of the junction temperature above the ambient.
Rev. A | Page 28 of 44
AD8150
APPLICATIONS
AD8150 INPUT AND OUTPUT BUSING
Although the AD8150 is a digital part, in any application that
runs at high speed, analog design details will have to be given
very careful consideration. At high data rates, the design of the
signal channels will have a strong influence on the data integrity
and its associated jitter and ultimately bit error rate (BER).
While it might be considered very helpful to have a suggested
circuit board layout for any particular system configuration, this
is not something that can be practically realized. Systems come
in all shapes, sizes, speeds, performance criteria, and cost
constraints. Therefore, some general design guidelines will be
presented that can be used for all systems and judiciously
modified where appropriate.
High speed signals travel best, that is, maintain their integrity,
when they are carried by a uniform transmission line that is
properly terminated at either end. Any abrupt mismatches in
impedance or improper termination will create reflections that
will add to or subtract from parts of the desired signal. Small
amounts of this effect are unavoidable, but too much will distort
the signal to the point that the channel BER will increase. It is
difficult to fully quantify these effects because they are
influenced by many factors in the overall system design.
A constant-impedance transmission line is characterized by
having a uniform cross-sectional profile over its entire length.
In particular, there should be no stubs, which are branches that
intersect the main run of the transmission line. These can have
an electrical appearance that is approximated by a lumped
element, such as a capacitor, or if long enough, as another
transmission line. To the extent that stubs are unavoidable in a
design, their effect can be minimized by making them as short
as possible and as high an impedance as possible.
Figure 36 shows a differential transmission line that connects
two differential outputs from AD8150s to a generic receiver. A
more generalized system can have more outputs bused and
more receivers on the same bus, but the same concepts apply.
The inputs of the AD8150 can also be considered a receiver.
The transmission lines that bus all of the devices together are
shown with terminations at each end.
The individual outputs of the AD8150 are stubs that intersect
the main transmission line. Ideally, their current-source outputs
would be infinite impedance, and they would have no effect on
signals that propagate along the transmission line. In reality,
each external pin of the AD8150 projects into the package and
has a bond wire connected to the chip inside. On-chip wiring
then connects to the collectors of the output transistors and to
ESD protection diodes.
Unlike some other high speed digital components, the AD8150
does not have on-chip terminations. While the location of such
terminations would be closer to the actual end of the
transmission line for some architectures, this concept can limit
system design options. In particular, it is not possible to bus
more than two inputs or outputs on the same transmission line
and it is not possible to change the value of these terminations
to use them for different impedance transmission lines. The
AD8150, with the added ability to disable its outputs, is much
more versatile in these types of architectures.
If the external traces are kept to a bare minimum, the output
will present a mostly lumped capacitive load of about 2 pF. A
single stub of 2 pF will not seriously adversely affect signal
integrity for most transmission lines, but the more of these
stubs, the more adverse their influence will be.
One way to mitigate this effect is to locally reduce the
capacitance of the main transmission line near the point of stub
intersection. Some practical means for doing this are to narrow
the PC board traces in the region of the stub and/or to remove
some of the ground plane(s) near this intersection. The effect of
these techniques will locally lower the capacitance of the main
transmission line at these points, while the added capacitance of
the AD8150 outputs will compensate for this reduction in
capacitance. The overall intent is to create as uniform a
transmission line as possible.
In selecting the location of the termination resistors, it is
important to keep in mind that, as their name implies, they
should be placed at either end of the line. There should be no,
or minimal, projection of the transmission line beyond the
point where the termination resistors connect to it.
Rev. A | Page 29 of 44
AD8150
EVALUATION BOARD
An evaluation board has been designed and is available to
rapidly test the main features of the AD8150. This board lets the
user analyze the analog performance of the AD8150 channels
and easily control the configuration of the board by a standard PC.
Differential inputs and outputs provide the interface for all
channels with the connections made by a 50 Ω SMB-type
connector. This type of connector was chosen for its rapid
mating and unmating action. The use of SMB-type connectors
minimizes the size and minimizes the effort of rearranging
interconnects that would be required if using SMA-type
connectors.
CONFIGURATION PROGRAMMING
The board is configurable by one of two methods. For ease of
use, custom software is provided that controls the AD8150
programming via the parallel port of a PC. This requires a usersupplied standard printer cable that has a DB-25 connector at
one end (parallel- or printer-port interface) and a Centronixtype connector at the other that connects to P2 of the AD8150
evaluation board. The programming with this scheme is done
in a serial fashion, so it is not the fastest way to configure the
AD8150 matrix. However, the user interface makes it very
convenient to use this programming method.
If a high speed programming interface is desired, the AD8150
address and data buses are directly available on P3. The source
of the program signals can be a piece of test equipment, such as
the Tektronix HFS-9000 digital test generator, or some other
user-supplied hardware that generates programming signals.
When using the PC interface, the jumper at W1 should be
installed and no connections should be made to P3. When
using the P3 interface, no jumper is installed at W1. There are
locations for termination resistors for the address and data
signals if these are necessary.
POWER SUPPLIES
The AD8150 is designed to work with standard ECL logic
levels. This means that VCC is at ground and VEE is at a negative
supply. The shells of the I/O SMB connectors are at VCC
potential. Thus, when operating in the standard ECL
configuration, test equipment can be directly connected to the
board, because the test equipment will also have its connector
shells at ground potential.
Operating in PECL mode requires VCC to be at a positive
voltage while VEE is at ground. Since this would make the shells
of the I/O connectors at a positive voltage, it can cause problems
when directly connecting to test equipment. Some equipment,
such as battery operated oscilloscopes, can be floated from
ground, but care should be taken with line-powered equipment
so that a dangerous situation is not created. Refer to the test
equipment’s manual.
The voltage difference from VCC to VEE can range from 3 V to 5 V.
Power savings can be realized by operating at a lower voltage
without any compromise in performance.
A separate connection is provided for VTT, the termination
potential of the outputs. This can be at a voltage as high as VCC,
but power savings can be realized if VTT is at a voltage that is
somewhat lower. Please consult elsewhere in the data sheet for
the specification for the limits of the VTT supply.
As a practical matter, current on the evaluation board will flow
from the VTT supply through the termination resistors and then
through the AD8150 from its outputs to the VEE supply. When
running in ECL mode, VTT will want to be at a negative supply.
Most power supplies will not allow their ground to connect to
VCC and will not allow their negative supply to connect to VTT.
This will require them to source current from their negative
supply, which will not return to the ground terminal. Thus, VTT
should be referenced to VEE when running in ECL mode, or a
true bipolar supply should be used.
The digital supply is provided to the AD8150 by the VDD and
VSS pins. VSS should always be at ground potential to make it
compatible with standard CMOS or TTL logic. VDD can range
from 3 V to 5 V and should be matched to the supply voltage of
the logic used to control the AD8150. However, since PCs use 5 V
logic on their parallel port, VDD should be at 5 V when using a
PC to program the AD8150.
SOFTWARE INSTALLATION
The software to operate the AD8150 is provided on two 3.5"
floppy disks. The software is installed by inserting Disk 1 into
the floppy drive of a PC and running the setup.exe program.
This will routinely install the software and prompt the user to
change to Disk 2. The setup program will also prompt the user
to select the directory location to store the program.
After running the software, the user will be prompted to
identify which (of three) software driver is used with the PC’s
parallel port. The default is LPT1, which is most commonly
used. However, some laptops commonly use the PRN driver. It
is also possible that some systems are configured with the LPT2
driver.
If it is not known which driver is used, it is best to select LPT1
and proceed to the next screen. This will show a full array of
buttons that allows the connection of any input to output of the
AD8150. All of the outputs should be in the output off state
immediately after the program starts running. Any of the active
buttons can be selected with a mouse click, which will send out
one burst of programming data.
Rev. A | Page 30 of 44
AD8150
After this, the PC keyboard’s left or right arrow key can be held
down to generate a steady stream of programming signals out of
the parallel port. The CLOCK test point on the AD8150
evaluation board can be monitored with an oscilloscope for any
activity (a user-supplied printer cable must be connected). If
there is a square wave present, then the proper software driver
is selected for the PC’s parallel port.
If there is no signal present, then another driver should be tried
by selecting the Parallel Port menu item from the File pulldown menu selection under the title bar. Select a different
software driver and carry out the above test until signal activity
is present at the CLOCK test point.
SOFTWARE OPERATION
The off column can be used to disable whichever output one
chooses. To disable all outputs, click the Global Reset button.
This will select the full column of OFF buttons.
Two scratchpad memories (Memory 1 and Memory 2) are
provided to conveniently save a particular configuration.
However, these registers are erased when the program is
terminated. For long-term storage of configurations, the disk’s
storage memory should be used. The Save and Load selections
can be accessed from the File pull-down menu under the title
bar.
01074-041
Any button can be clicked in the matrix to program the inputto-output connection. This will send the proper programming
sequence out of the PC parallel port. Since only one input can
be programmed to a given output at a time, clicking a button in
a horizontal row will cancel previous selections in that row.
However, any number of outputs can share the same input.
Refer to Figure 42.
A shortcut for programming all outputs to the same input is to
use the broadcast feature. After clicking on the Broadcast
Connection button, a window will appear that will prompt the
user to select which input should be connected to all outputs.
The user should type in an integer from 0 to 32 and then click
OK. This will send out the proper program data and return to
the main screen with a full column of buttons selected under
the chosen input.
Figure 42. Evaluation Board Controller
Rev. A | Page 31 of 44
AD8150
01074-042
PCB LAYOUT
Figure 43. Component Side
Rev. A | Page 32 of 44
01074-043
AD8150
Figure 44. Circuit Side
Rev. A | Page 33 of 44
01074-044
AD8150
Figure 45. Silkscreen Top
Rev. A | Page 34 of 44
01074-045
AD8150
Figure 46. Solder Mask Top
Rev. A | Page 35 of 44
01074-046
AD8150
Figure 47. Silkscreen Bottom
Rev. A | Page 36 of 44
01074-047
AD8150
Figure 48. Solder Mask Bottom
Rev. A | Page 37 of 44
01074-048
AD8150
Figure 49. INT1 (VEE)
Rev. A | Page 38 of 44
01074-049
AD8150
Figure 50. INT2 (VCC)
Rev. A | Page 39 of 44
AD8150
VCC
IN00P
P4
R20
105Ω
P5
IN00N
R21
1.65kΩ
R40
1.65kΩ
VCC
IN06P
R58
1.65kΩ
VCC
IN12P
P28
P16
R39
105Ω
P17
IN06N
R38
1.65kΩ
R89
1.65kΩ
VCC
IN18P
P29
R56
1.65kΩ
IN12N
VCC
IN24P
P52
P40
R57
105Ω
R94
1.65kΩ
R90
105Ω
P41
IN18N
R91
1.65kΩ
R116
1.65kΩ
IN30P
P53
IN24N
R92
1.65kΩ
R117
105Ω
P65
R118
1.65kΩ
VEE
VEE
VEE
VEE
VCC
VCC
VCC
VCC
VCC
VCC
P6
R24
105Ω
P7
IN01N
R23
1.65kΩ
R41
1.65kΩ
IN07P
R59
1.65kΩ
P30
P18
R42
105Ω
P19
IN07N
R43
1.65kΩ
IN13P
R60
105Ω
P31
IN13N
R61
1.65kΩ
R88
1.65kΩ
IN19P
R95
1.65kΩ
IN25P
P54
P42
R87
105Ω
P43
IN19N
R86
1.65kΩ
R115
1.65kΩ
OUT09P
OUT09N
IN31P
R96
105Ω
P55
IN25N
R97
1.65kΩ
R114
105Ω
P67
R113
1.65kΩ
OUT10N
VEE
VEE
VEE
VCC
VCC
VCC
VCC
VCC
VCC
P8
IN02P
R27
105Ω
P9
P20
IN08P
R45
105Ω
IN02N
IN14P
R63
105Ω
P33
P21
R26
1.65kΩ
P32
R46
1.65kΩ
IN08N
R85
1.65kΩ
P44
IN20P
R84
105Ω
R64
1.65kΩ
IN14N
R98
1.65kΩ
P56
IN26P
R99
105Ω
P57
P45
R83
1.65kΩ
IN20N
R100
1.65kΩ
IN26N
VEE
VEE
VEE
VEE
VCC
VCC
VCC
VCC
VCC
P10
IN03P
R30
105Ω
P11
R47
1.65kΩ
P22
IN09P
R48
105Ω
IN03N
R49
1.65kΩ
VEE
P12
IN04P
IN04N
R32
1.65kΩ
R66
105Ω
R50
1.65kΩ
P24
IN15N
IN10N
R68
1.65kΩ
P36
P37
R70
1.65kΩ
IN16N
VEE
VCC
VCC
VCC
P14
IN05P
R36
105Ω
P15
R35
1.65kΩ
VEE
IN05N
P26
IN11P
R54
105Ω
P27
R55
1.65kΩ
VEE
IN11N
R71
1.65kΩ
P38
IN17P
R72
105Ω
P39
VEE
IN17N
P68
IN21N
R79
1.65kΩ
P48
R173
49.9Ω
R170
49.9Ω
R111
105Ω
OUT11N
R172
49.9Ω
R110
1.65kΩ
VEE
OUT12P
R185
49.9Ω
R183
49.9Ω
IN27P
R102
105Ω
OUT13P
R103
1.65kΩ
IN27N
OUT13N
R180
49.9Ω
R182
49.9Ω
VCC
IN22P
OUT14P
R104
1.65kΩ
P60
R195
49.9Ω
IN28P
R105
105Ω
OUT14N
R193
49.9Ω
P61
R77
1.65kΩ
IN22N
IN28N
R106
1.65kΩ
VEE
VEE
VCC
VCC
R76
1.65kΩ
P50
IN23P
R75
105Ω
R107
1.65kΩ
P62
OUT15P
R190
49.9Ω
OUT15N
R192
49.9Ω
VEE
IN23N
P86
P85
VTT
OUT01P
R125
49.9Ω
OUT01N
R127
49.9Ω
P84
VTT
P102
P101
VTT
P100
P99
VTT
OUT02P
R130
49.9Ω
OUT02N
R132
49.9Ω
P82
P81
OUT03P
VTT
OUT03N
P80
P79
OUT04P
VTT
OUT04N
P78
P77
OUT05P
VTT
OUT05N
P76
R108
105Ω
R109
1.65kΩ
IN29N
OUT06P
VTT
OUT06N
P74
P73
VTT
R133
49.9Ω
OUT16P
R200
49.9Ω
R198
49.9Ω
R145
49.9Ω
R143
49.9Ω
R150
49.9Ω
R152
49.9Ω
OUT07N
R153
49.9Ω
P72
P98
P97
VTT
P96
P95
VTT
P94
P93
VTT
P92
VTT
P90
P89
VTT
P88
C16
0.01μF
P71
VCC
VTT
C82
0.01μF
VCC
VTT
P70
C83
0.01μF
VTT
Figure 51. Input/Output Connections and Bypassing
R142
49.9Ω
R155
49.9Ω
VTT
OUT16N
R140
49.9Ω
OUT07P
VEE
Rev. A | Page 40 of 44
R135
49.9Ω
VTT
P91
P75
IN29P
P63
R74
1.65kΩ
OUT00N
R122
49.9Ω
VTT
IN32N
VEE
R78
105Ω
P49
R175
49.9Ω
IN32P
P59
P51
R73
1.65kΩ
P58
VCC
R69
105Ω
VEE
R53
1.65kΩ
R81
105Ω
OUT11P
R112
1.65kΩ
OUT12N
R101
1.65kΩ
VEE
IN16P
VEE
R37
1.65kΩ
IN21P
R80
1.65kΩ
VCC
IN10P
R52
1.65kΩ
P46
VEE
R51
105Ω
P25
R82
1.65kΩ
P47
R67
1.65kΩ
VCC
R33
105Ω
P13
IN09N
VEE
VCC
R34
1.65kΩ
P34
IN15P
P35
P23
R29
1.65kΩ
R65
1.65kΩ
R163
49.9Ω
P69
VEE
R31
1.65kΩ
R165
49.9Ω
IN31N
VEE
R62
1.65kΩ
R121
49.9Ω
P83
OUT10P
VEE
R44
1.65kΩ
R162
49.9Ω
P103
OUT00P
P66
VEE
R28
1.65kΩ
OUT08N
P87
IN30N
VEE
IN01P
R160
49.9Ω
P64
R93
105Ω
VEE
R25
1.65kΩ
OUT08P
VCC
01074-051
VCC
R19
1.65kΩ
AD8150
CLK
A1
4
74HC14
VSS P2 25
5
1
A1
2
6
3
74HC14
4
5
VSS
6
7
VDD
8
9
10
VSS
OUT_EN
Q0
D1
Q1
D2
Q2
D3
Q3
D2
Q2
D3
Q3
1
J28
J4
J29
J5
J30
J6
J31
J7
J32
J8
J33
J9
J34
J10
J35
J11
J36
J12
J37
J13
J38
J14
J39
J15
J40
J16
J41
J17
J42
J18
J43
J19
J44
J20
J45
J21
J46
J22
J47
J23
J48
J24
J49
J25
J50
163A1
VSS
2
VSS
A4
VEE
J27
R12
49Ω
153D6
R13
49Ω
154D5
R14
49Ω
162A2
4
5
VCC
J3
VSS
3
VEE
A3
15
D4 74HC74 Q4
7
14
D5
Q5
8
13
D6
Q6
9
12
Q7
D7
10
CLK 11
GND
VSS
A4
VCC
18
J26
161A3
164A0
VDD
J2
VSS
74HC132
VSS P3 14
P3 8
P3 12
P3 28
P3 26
P3 24
P3 22
P3 20
P3 18
P3 40
P3 38
P3 36
P3 34
P3 32
P3 30
P3 16
P3 10
P3 6
Q1
VSS
VSS
P3 13
P3 7
P3 11
P3 27
P3 25
P3 23
P3 21
P3 19
P3 17
P3 39
P3 37
P3 35
P3 33
P3 31
P3 29
P3 15
P3 9
P3 5
D1
160A4
R11
49Ω
VSS
Q0
20
19
J1
6
VSS
VCC
D0
16
5
VDD
OUT_EN
17
4
17
16
R10
49Ω
W1
WRITE
RESET
READ
D0
A4
A3
A2
A1
A0
D6
D5
D4
D3
D2
D1
UPDATE
CHIP_SELECT
VDD
3
18
R9
49Ω
VSS
P2 7
P2 3
P2 8
P2 4
P2 2
2
R8
49Ω
VSS
READ
RESET
WRITE
UPDATE
CHIP_SELECT
1
R7
49Ω
VSS
VDD
20
19
A2
15
D4 74HC74 Q4
14
D5
Q5
13
D6
Q6
12
D7
Q7
11
CLK
GND
VSS
R1
20kΩ
VCC
D0
155D4
R15
49Ω
156D3
R16
49Ω
157D2
R17
49Ω
158D1
R18
49Ω
6
VSS
159D0
74HC132
TP5
TP6
TP4
TP20
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP7
TP8
VDD
VDD
VSS
R2
49kΩ
VSS
VSS
VSS
VSS
VSS
R3
49kΩ
R4
49kΩ
R5
49kΩ
R6
49kΩ
WRITE
166
READ
167
VTT P1 6
+
RESET
169
A1
8
74HC14
A1
11
10
CHIP_SELECT
168
UPDATE
165
9
VCC P1 1
P1 2
+
C3
10μF
C1
10μF
VEE P1 3
P1 4
VDD P1 7
VSS
13
VCC
VCC
74HC14
A4
9
VEE
VEE
+
P1 5
10
A1, 4 PIN 14 IS TIED TO VDD.
A1, 4 PIN 7 IS TIED TO VSS.
VDD
VDD
VDD
VDD
VDD
C2
10μF
VSS
P104
P105
Figure 52. Control Logic and Bypassing
Rev. A | Page 41 of 44
74HC14
A1
12
VTT
VTT
C86
0.1μF
C87
0.1μF
VSS
C88
0.1μF
VSS
C89
0.1μF
VSS
8
74HC132
A4
12
13
11
74HC132
VSS
01074-052
3
P2 5
2
74HC14
DATA
DATA
A1
1
CLK P2 6
AD8150
OUTLINE DIMENSIONS
0.75
0.60
0.45
22.20
22.00 SQ
21.80
1.60
MAX
184
1
139
138
PIN 1
20.20
20.00 SQ
19.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
93
92
46
47
VIEW A
0.40
BSC
LEAD PITCH
VIEW A
0.23
0.18
0.13
ROTATED 90° CCW
Figure 53. 184-Lead Low Profile Quad Flat Package [LQFP]
(ST-184)
Dimensions shown in millimeters
ORDERING GUIDE 1
Model
AD8150AST
AD8150ASTZ 2
AD8150-EVAL
1
2
Temperature Range
0°C to 85°C
0°C to 85°C
Package Description
184-Lead Low Profile Quad Flat Package [LQFP]
184-Lead Low Profile Quad Flat Package [LQFP]
Evaluation Board
Package Option
ST-184
ST-184
Details of lead finish composition can be found on the ADI website at www.analog.com by reviewing the Material Description of each relevant package.
Z = Pb-free part.
Rev. A | Page 42 of 44
AD8150
NOTES
Rev. A | Page 43 of 44
AD8150
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01074–0–9/05(A)
Rev. A | Page 44 of 44