N
Comlinear CLC018
8 x 8 Digital Crosspoint Switch, 1.4Gbps
General Description
Features
The Comlinear CLC018 is a fully differential 8x8 digital crosspoint
switch capable of operating at data rates exceeding 1.4Gbps per
channel. Its non-blocking architecture utilizes eight independent
8:1 multiplexers to allow each output to be independently
connected to any input and any input to be connected to any or
all outputs. Additionally, each output can be individually disabled
and set to a high-impedance state. This TRI-STATE® feature
allows flexible expansion to larger switch array sizes.
■
Low channel-to-channel crosstalk allows the CLC018 to provide
superior all-hostile jitter of 50pspp . This excellent signal
fidelity along with low power consumption of 850mW make the
CLC018 ideal for digital video switching plus a variety of data
communication and telecommunication applications.
Applications
■
■
■
■
■
■
■
■
■
Fully differential signal path
Non-Blocking
Flexible expansion to larger array sizes
with very low power
Single +5V/-5V or dual ±5V operation
TRI-STATE® outputs
Double row latch architecture
64-lead PQFP package
Serial digital video routing (SMPTE 259M)
Telecom/datacom switching
ATM SONET
Key Specifications
The fully differential signal path provides excellent noise immunity,
and the I/Os support ECL and PECL logic levels. In addition, the
inputs may be driven single-ended or differentially and accept a
wide range of common mode levels including the positive supply.
Single +5V or -5V supplies or dual +5V supplies are supported.
Dual supply mode allows the control signals to be referenced to
the positive supply (+5V) while the high-speed I/O remains ECL
compatible.
■
■
■
■
Comlinear CLC018
8 x 8 Digital Crosspoint Switch, 1.4Gbps
December 1996
High speed: >1.4Gbps
Low jitter:
< 50pspp for rates < 500Mbps
< 100pspp for rates < 1.4Gbps
Low power: 850mW with all outputs active
Fast output edge speeds: 250ps
Output Eye Pattern, 1.4Gbps
The double row latch architecture utilized in the CLC018
allows switch reprogramming to occur in the background during
operation. Activation of the new configuration occurs with a
single “configure” pulse. Data integrity and jitter performance on
unchanged outputs are maintained during reconfiguration. Two
reset modes are provided. Broadcast reset results in all outputs
being connected to input port DI0. TRI-STATE® Reset results in
all outputs being disabled.
The CLC018 is fabricated on a high-performance BiCMOS process
and is available in a 64-lead plastic quad flat pack (PQFP).
150ps/div
8
8
8 x 8 Switch Matrix
DI0 – DI7
CLC018
Basic Block Diagram
DO0 – DO7
CNFG
LE
Configuration
Registers
LE
Load
Registers
RES
LOAD
8
3-8
Decoder
CS
3
Input Address
© 1996 National Semiconductor Corporation
Printed in the U.S.A.
TRI
Output Address
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CLC018 Electrical Characteristics
PARAMETERS
(VCC = 0V, VEE = -5V, V LL = 0V; unless specified) 1
CONDITIONS
TYP
CLC018
DYNAMIC PERFORMANCE
max. data rate/channel (NRZ)
channel jitter
UNITS
NOTES
1.4
50
100
0.75
±200
250
10
Gbps
pspp
pspp
ns
ps
ps
ps
2
3
3
+25°C
data rate <500Mbps
data rate <1.4Gbps
propagation delay (input to output)
propagation delay match
output rise/fall time
duty cycle distortion
MIN/MAX RATINGS
+25°C
-40 to 85°C
CONTROL TIMING: CONFIGURATION
OA bus to LOAD ↑ setup time (T1)
LOAD ↓ to OA bus hold time (T2)
IA bus, TRI to LOAD ↓ setup time (T3)
LOAD ↓ to IA bus, TRI hold time (T4)
min. pulse width : (T5)
LOAD
CNFG
LOAD ↑ to CNFG ↑ delay (T6)
CNFG ↑ to valid data delay (T7)
CNFG ↑ to output TRI-STATE® delay (T8)
CNFG ↑ to output active delay (T9)
15
0
5
5
ns
ns
ns
ns
10
10
0
20
20
70
ns
ns
ns
ns
ns
ns
CONTROL TIMING: RESET
TRI to RES ↑ setup time (T10)
RES ↓ to TRI hold time (T11)
min. pulse width: RES (T12)
RES ↑ to TRI-STATE® mode delay (T13)
RES ↑ to broadcast mode delay (T14)
5
5
10
20
70
ns
ns
ns
ns
ns
STATIC PERFORMANCE
signal I/O:
min. input swing, differential
input voltage range lower limit
input voltage range upper limit
input bias current
output current
output voltage swing
output voltage range lower limit
output voltage range upper limit
control inputs:
input voltage - HIGH
VIH min
input voltage - LOW
VIL max
input voltage - HIGH
VIH min
input voltage - LOW
VIL max
input current - HIGH
input current - LOW
MISCELLANEOUS PERFORMANCE
VCC supply current
VCC supply current
VLL supply current
VLL supply current
input capacitance
output capacitance
4
5
6
7
8
150
-2
0.4
1.5
10.7
800
-2.5
0
RLoad = 75Ω
VLL = +5V
VLL = +5V
VIH = VLL
VIL = VLL -5V
all outputs active
all outputs TRI-STATE®
VLL = 0V
VLL = +5V
200
200
0.4/3.1
8.53/12.80
640/960
0.3/3.8
7.20/14.3
540/1060
-1
-4
4
1
1
-100
-0.5
-4.5
4.5
0.5
0.2/2.0
-200/10
157
7
2.5
7
1.5
2
127/202
3/11
1.7/3.3
A
mVpp
V
V
µA/output
mA
mV
V
V
A, 9
A
-0.5
-4.5
4.5
0.5
0.1/2.5
-250/15
V
V
V
V
µA
µA
A
A
A
A
A
A
119/217
2/12
1.5/3.5
mA
mA
mA
mA
pF
pF
A, 10, 11
A
A
A
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Notes
7) Refer to the Configuration Timing Diagram.
8) Refer to the Reset Timing Diagram.
9) The bias current for high speed data input depends on the number
of data outputs that are selecting that input.
10) The VCC supply current is a function of the number of active data
outputs. I VCC ≈ 18*N + 7mA where N is an integer from 0 to 8.
11) IVEE = IVCC + IVLL.
A) J-level spec. is 100% tested at +25°C.
1) VLL and all V EE supply pins are bypassed with 0.01µF ceramic
capacitor.
2) Bit error rate less than 10-9 over >50% of the bit cell interval.
3) Measured using a pseudo-random (223-1 pattern) binary sequence
with all other channels active with an uncorrelated signal.
4) Spread in propagation delays for all input/output combinations.
5) Measured between the 20% and 80% levels of the waveform.
6) Difference in propagation delay for output low-to-high vs. output
high-to-low transition.
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2
Absolute Maximum Ratings
supply voltage (V CC - VEE)
VLL maximum
VLL minimum
storage temperature range
lead temperature (soldering 4 sec)
ESD rating
Ordering Information
-0.3, +6.0V
VCC +6V
VCC -0.5V
-65° to +150°C
+260°C
TBD
Model
CLC018AJVJQ
Description
64-pin PQFP
Package Thermal Resistance
qJA
75°C/W
Package
Recommended Operating Conditions
supply voltage (V CC - VEE)
operating temperature
VLL
Temperature Range
-40°C to +85°C
64-pin PQFP
4.5V to 5.5V
-40° to +85°C
VCC or VCC+5V
qJC
15°C/W
Reliability Information
Transistor count
MTTF (based on limited life test data)
3000
TBD
CLC018 Typical Performance
Percent Eye Opening vs. Data Rate
Jitter vs. Data Rate
Output Current vs. Supply Voltage
100
40
13
12.5
Jitter (ps rms)
30
25
32x32
Fixture
20
15
10
8x8
Fixture
80
Output Current (mA)
Percent Eye Opening
35
60
40
20
12
11.5
11
10.5
5
9
8.5
0
0
100
300
500
700
900
1100
8
500
1300
700
900
1100
1300
4.5
Output Current vs. Temperature 018 Plot1
Prop. Delay vs. Temperature
850
165
10
9.5
Supply Current (mA)
11.5
Prop. Delay (ps)
170
10.5
800
750
700
650
9
600
10
40
70
100
5.5
160
155
150
145
140
-50
Temperature (°C)
5.3
-20
10
40
70
-50
100
Temperature (°C)
018 Plot4
-20
10
40
70
100
Temperature (°C)
018 Plot5
018 Plot6
64
Vcc
DI5
DI5
Vcc
DI4
DI4
Vcc
DI3
DI3
Vcc
DI2
DI2
Vcc
DI1
DI1
VEE
CLC018 Pin Definitions
1
Vcc
DI6
DI6
Vcc
DI7
DI7
Vcc
CS
RES
CNFG
LOAD
VEE
Vcc
DO7
DO7
Vcc
Top View
CLC018
64 Lead PQFP
Vcc
DI0
DI0
VLL
IA0
IA1
IA2
TRI
OA0
OA1
OA2
Vcc
DO0
DO0
Vcc
DO1
DO6
DO6
Vcc
DO5
DO5
Vcc
DO4
DO4
Vcc
DO3
DO3
Vcc
DO2
DO2
VEE
DO1
-20
5.1
Total Supply Current vs. Temperature
018 Plot3
018 Plot2
900
11
4.9
Supply Voltage
12
-50
4.7
Data Rate (Mbps)
Data Rate (Mbps)
Output Current (mA)
10
9.5
3
018 Pinout
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Pin Descriptions
Power Pins
VCC is the most positive rail for the data path. When the data is ECL compatible levels, then VCC should be connected
to GND, for PECL data (+5V referenced ECL) then VCC is connected to the +5V supply. Please refer to the device
operation section in this datasheet for recommendations on the bypassing and ground/power plane requirements
of this device.
VEE is the most negative rail for the data path. When the data is ECL compatible levels, then VEE is connected to a
-5.2V power supply, for PECL data (+5V referenced ECL) then VEE is connected to GND. Please refer to the
device operation section in this datasheet for recommendations on the bypassing and ground/power plane
requirements of this device.
VLL is the logic level power supply. If the control signals are to be referenced to +5V, then VLL is connected to a
+5V supply, if control signals are to be ECL compatible then VLL is connected to GND. Please refer to the device
operation section in this datasheet for recommendations on the bypassing and ground/power plane requirements
of this device.
Data Input
___Pins
___
DI0 and DI0 through DI7 and D17 are the data input pins to the CLC018. Depending upon how the Power pins are
connected (please refer to the Power Pin section above) the data may be either differential ECL, or differential
PECL. To drive the CLC018 inputs with a single ended signal, please refer to the section “Using Single Ended
Data” in the OPERATION section of this datasheet.
Data Output
____Pins
____
DO0 and DO0 through DO7 and DO7 are the data output pins to the CLC018. The CLC018 outputs are differential
current outputs which can be converted to ECL or PECL compatible outputs through the use of load resistors
please refer to the “Output Interfacing” paragraph in the OPERATION section of this datasheet for more details.
Control Pins
IA2, IA1 and IA0 comprise a three bit input selection address bus. The input port to be addressed is placed on this
bus. IA2 represents the Most Significant Bit (MSB) so if input port 6 is to be addressed, IA2, IA1, IA0 should have
1, 1, 0 asserted on them. The IA bus should be driven with CMOS levels, if VLL is +5V, then these levels will be
+5V referenced (standard CMOS), if VLL is connected to GND, then the input levels are referenced to the -5V and
GND supplies.
OA2, OA1 and OA0 comprise the output selection address bus. The output port selected by the OA bus will be
connected to the input port selected on the IA bus when the data is loaded into the configuration registers. OA2
is the MSB, so if OA2, OA1, OA0 is set to 0, 0, 1 then output port 1 will be selected.
CS is an active high chip select input. When CS is high, the RES, LOAD, and CNFG pins will be enabled.
LOAD is a latch control for the LOAD register. When LOAD is high, the load register is transparent, with it’s outputs
following the state of the IA bus, and being presented to the inputs of the Configuration register selected by the
OA bus. When LOAD is low, the outputs of the Load register are latched.
RES is a reset control to the configuration and load registers. A high going pulse on the RES pin will program the
switch matrix to one of two possible states: if TRI is low, then all outputs are connected to input #0, if TRI is high,
then all outputs are put in TRI-STATE® condition.
TRI will program the selected output to be in a high impedance or TRI-STATE® condition.
CNFG is the configuration register latch control. When CNFG is high the Configuration register is made transparent,
and the switch matrix is set to the state loaded into the Load registers. When CNFG is low, the state of the switch
matrix is latched.
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4
Timing Diagrams
TRI
RES
t10
t12
t11
DATA
OUT
Invalid Data
t13
Figure 1: Timing Diagram – “TRI-STATE®” Reset
018 Fig4
TRI
RES
t10
t12
t11
DATA
OUT
Invalid Data
t14
Figure 2: Timing Diagram – “Broadcast” Reset
018 Fig5
OA
TRI
IA
LOAD
CNFG
Old
Data
DATA
OUT
t1
t3
t5
t2
Invalid
Data
Valid
Data
t5
t4
t7,t8,t9
t6
Figure 3: Timing Diagram – Switch Configuration
5
018 Fig6
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CLC018 Operation
Hysteresis
Control
Input Interfacing
The inputs to the CLC018 are high impedance differential
inputs (see the equivalent input circuit in Figure 4). The
CLC018 can be operated with either ECL or PECL (+5V
referenced ECL), depending upon the power supply
connections. The inputs are differential and must both be
within the range of VCC - 2V to VCC + 0.4V in order to
function properly.
MC10E1652
Figure 6: Single Ended Input to CLC018
Output Interfacing
018 FigC
The outputs of the CLC018 are differential, current source
outputs. They can be converted to ECL compatible
levels with the use of resistive loads as shown in Figure
7. If a 1N4148 diode is used to set VOH, then the output
swings will have a similar temperature coefficient to
10KECL. For most commercial temperature range applications, a 75Ω resistor can be used as shown in Figure
8. Many circuits with differential inputs, such as the
CLC016 Data Retimer With Automatic Rate Selection, do
not require true ECL levels. Then the load resistors can be
connected directly to the positive rail, as shown in Figure 9.
200Ω
200Ω
DI
CLC018
CLC018
Figure 4: Equivalent Input Circuit
75Ω
DOX
Single Ended Inputs
018 FigA
Differential inputs are the preferred method
of providing
DOX
data to the CLC018, however, there are times when the
only signal available is single ended. To use the CLC018
with a single ended input, the unused input pin needs to
be biased at a point higher than the low logic level,
and lower than the high logic level. For best noise
performance, the middle of the range is best. For ECL
signals this point is about 2 diode drops below ground. It
is possible to bias the unused input with a low pass
filtered version of the data, as shown in Figure 5. In
some coding schemes there are pathological patterns
that result in there being long sequences with no data
transitions, during these patterns, the bias on the unused
input will drift towards the other input reducing the noise
immunity, which makes this scheme undesirable. The
most robust solution to use for single ended inputs, is to
place a comparator with hysteresis in front of the
CLC018, such a part is the MC10E1652. See Figure 6
for an example of how to hook this up.
75Ω
75Ω
75Ω
DOX
DOX
Figure 7: Generating 10KECL
Outputs
018 FigD
IN4148
75Ω
CLC018
CLC018
75Ω
75Ω
75Ω
DOX
DOX
DOX
DOX
Figure 8: Generating ECL Outputs
CLC018
CLC018
CLC016
75Ω
DIX
DIX
Figure 5: Single Ended Input to CLC018
75Ω
Data
Retimer
DOX
DDI
DOX
DDI
Figure 9: Connecting the CLC018 to the CLC016
018 FigG
018 FigB
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IN4148
75Ω
VEE
Input
Signal
DIX
DIX
VCC
DI
CLC018
Input
Signal
6
75Ω
018 FigD
Power Supplies, Grounding, Bypassing
The CLC018 has three power supplies, with VCC and VEE
each having several pins. VLL supplies power to the control circuitry of the CLC018.
There are three
possible modes in which to operate the CLC018, with
different combinations of voltages that are to be applied
to each of the power supplies in each mode. The table
below describes these three modes.
from high to low. To load the LOAD registers, place the
three bit address of the register that you want to load (the
output port which you want to configure), on the OA bus,
then place the address of the input port which you want
to connect that output to, and the TRI-STATE® status on
the IA bus , and provide a high going pulse to the LOAD
pin. To configure the entire chip, repeat this process for
each of the registers. At this point, all of the configuration
information will be stored in the Load Registers. To
implement the new configuration, apply a positive going
pulse to the CNFG pin and the Load Register contents
are transferred into the Configuration Registers and the
new configuration is established. If the CS pin is low, the
contents of the registers are not allowed to change
regardless of what you do, so during loading of the
registers, and implementation of the new configuration,
CS must be held high. There is an additional pin RES,
which allows you to set the entire switch matrix into one
of two states instantaneously. By applying a positive
going pulse to the RES pin, all outputs will either be
connected to input 0 (if TRI is low) or will be set to the
high impedance state (if TRI is high).
When a digital output switches, parasitic capacitances at
various internal and external nodes need to be charged
and discharged. The amount of current used to charge
these nodes depends upon the edge rates and the size
of the parasitic capacitances. The CLC018 outputs
transition in 250ps, and as a result, it does not take much
stray capacitance to generate rather large transient
currents. Two keys to minimizing the impact of these
transients are to have lots of bypassing, and a good
ground plane. For best performance, there should be
a 0.01 to 0.1µF cap on each power pin to GND, and
located as close to the pin as is practicable.
Configuring the Switch
The CLC018 can be configured so that each output can
be connected to any of the eight inputs, or can be in
TRI-STATE® mode. The configuration is stored in a bank
of eight, four bit registers, one for each output port.
These registers are known as the CONFIGURATION
REGISTERS. The first three bits in each of these
registers represent the input port which is to be
connected to the register, the fourth bit controls whether
that output port is in the TRI-STATE® mode or not. There
is a second bank of eight four bit registers, the LOAD
REGISTERS, whose contents are latched into the
configuration registers when the CNFG signal transitions
Supply Operation
Single -5V
Single +5V
Dual ±5V
ECL
PECL
ECL
-5V/GND
GND/+5V
GND/+5V
I/O Data Level
Control Signal Low/High
Expanding the Switch Size
The CLC018 was designed to be easy to expand to
larger array sizes, without paying a significant penalty in
either speed or power. The power dissipation of the
expanded array will be dominated by the number of
active outputs, therefore power will increase linearly with
the array size, even though the number of components
required increases as the square of the array size. As an
example, a single CLC018 can be used for an 8x8 array,
and it will dissipate about 0.85W. If a 32 x 32 array is
built, it will require 16 CLC018s, but will consume only
about 4W.
Connection
+5V
+5V
0.01µF
VCC
VLL
VCC
VEE
+5V
0.01µF
0.01µF
VLL
VCC
VEE
VLL
VEE
0.01µF
0.01µF
-5V
Key Information
-5V
1. Bypass each V EE supply
1. Bypass each V CC supply
with a 0.01µF capacitor.
with a 0.01µF capacitor.
2. Connect VCC and VLL to the 2. Bypass the V LL supply with
ground plane.
a 0.01µF.
3. A power plane isn’t required 3. Connect VEE to the ground
for VEE but can be used.
plane.
4. Use a +5V power plane
for VCC.
1. Bypass each V EE supply
with a 0.01µF capacitor.
018 Table Diag.
2. Bypass the V LL supply with
a 0.01µF.
3. Connect VCC to the ground
plane.
4. A power plane isn’t required
for +5V (V LL) or -5V (VEE)
supplies, but can be used.
Table: Interfacing of the Power Supplies and Bypass Capacitors
7
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Expanding the Number of Output Ports
To expand the number of output ports in a switch array,
the inputs of multiple CLC018s are connected in parallel.
The bus that is used to connect the input ports should be
a controlled impedance transmission line as shown in
Figure 10. To control the switch array, the IA, OA and TRI
busses are all connected in parallel and a decoder is
used to assert high the CS of the CLC018 that is to be
addressed. This is also shown in Figure 10.
IA3
TRI
3
OAO:2
CS
IN
OA
CLC018
8
IN
OA3
8
OUT
IA
OUT
TRI
RLS
CS
CS
IN
OAO:2
OUT
IN
3
IA
CS OA3
CLC018
OUT
IA
IAO:2
OA
CLC018
8
TRI
3
IAO:2
8
Figure 11: Expanded Input Ports
TRI
3
018 FigI
INPUTS
CS OA5
IN
8
CLC018
OUT
IN
IA
8
8
8
RS1
8
CT1
CS
TRI
Term.
IN
TRI
CT2
CS
IN
TRI
OUT
CT3
CS
IN
TRI
OUT
TRI
OUT
8
RS2
Figure 10: 8 x 16 Crosspoint Example
018 FigH
CS
Term.
Expanding the Number of Input Ports
Expanding the number of inputs in a switch array can be
accomplished by wire-ORing the outputs together, and
TRI-STATE®ing the outputs of the CLC018s that do not
have their inputs selected. The output bus needs to be a
controlled impedance transmission line with a proper
termination network connected to it. This is shown in
Figure 11. To do this, the circuit has used a 1-of-2
decoder with complemented outputs to connect to the
TRI pins of the CLC018s in the array. This way, all
CLC018s are programmed simultaneously, and all of
them except for the one with the selected input, are
placed in the TRI-STATE® mode.
IN
CS
OUT
IN
TRI
OUT
TRI
OUT
8
RS3
CS
Term.
IN
CS
IN
TRI
OUT
CS
IN
TRI
OUT
TRI
OUT
8
RS4
CS
Term.
IN
CS
IN
TRI
OUT
CS
IN
TRI
OUT
TRI
OUT
8
Term.
Expanding both Inputs and Outputs
To increase both the number of inputs and outputs in an
array, you apply both the input port and output port
expansion techniques simultaneously. In Figure 12, this
is shown for the case of a 24 input by 32 output switch
array. Note that both input and output busses need to be
controlled impedance transmission lines. The CS pins
for rows of CLC018s are connected together and
become the row select inputs, whereas the TRI pins are
connected together for the columns of CLC018s and
become the column select pins.
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IN
TRI
CS
Term.
Term.
CT1
IA3
IA4
1 of 4
Select
RS1
CT2
OA3
CT3
OA4
NC
1 of 4
Select
RS2
RS3
RS4
018 FigJ
Figure 12: 24 x 32 output Switch Array
8
O
U
T
P
U
T
S
Calculating the Power Dissipation
in an Expanded Array
The power dissipated by a CLC018 is approximately
100mW per active output, plus about 50mW quiescent
power. Therefore a single CLC018 dissipates about 8 x
100mW + 50mW or about 850mW. When in an expanded
array, each CLC018 will dissipate the 50mW quiescent,
but only those with active outputs will be dissipating the
100mW per output. Therefore in an N x M array (an 8xN
input by 8xM output switch) the total power dissipation,
will all outputs active will be 800mW x M + MxNx50mW.
Therefore a 32 x 32 switch array dissipates about 4W.
of a resistor from the driver to either power or GND, if the
driver is a low impedance driver, (Voltage source output)
then the source termination will consist of series
resistors. Figure 13 shows several different examples of
how transmission lines might be set up in an array of
CLC018s.
Input Bussing
(Voltage Source Driver)
CLC018
CLC018
CLC018
IN
IN
IN
Input
Zo
Controlled
Impedance
Transmission
Lines,
and other Layout Techniques
When signals are being sent over a distance which is
comparable to, or greater than 1/4 the wavelength of the
signals, then controlled impedance transmission lines
must be used to prevent the wave characteristics from
distorting the signal. In the case of the CLC018, with
transition times of the outputs of 250ps, the signals being
handled have frequency components of a few GHz, and
the corresponding distances over which problems can
arise are about an inch. The two most common methods
for generating controlled impedance transmission lines
on a printed circuit board (PCB) are to use microstrip,
where there is a trace on an outer layer of the board, over
a ground plane that is buried in the board or is on the
back of the board, or stripline, where the signal trace is
sandwiched between two ground planes. For proper
operation, the busses need to be terminated both at the
beginning and at the end of the bus. The idea behind the
termination is to make impedance at the ends of the
transmission line match the characteristic impedance of
the line. If the thing driving the line has a high impedance
(current source output), then the termination will consist
Transmision Line
Zo
Output Bussing
(Current Outputs)
Zo
Zo
CLC016
_ 100Ω
Zo ~
IN
OUT
OUT
OUT
CLC018
CLC018
CLC018
Figure 13: Input/Output Bussing
018 Fig13
A good reference to see how to calculate Microstrip and
Stripline impedances as well as to glean many high
speed design and layout tips is the Motorola MECL
System Design Handbook.
Overshoot and ringing are the result of poorly terminated
transmission lines. If there is overshoot and ringing,
there is excess energy that is likely to be coupled into
other nodes of the circuit, this will lead to degraded jitter
specifications. Accordingly, it is important to take care to
design your board so that all high speed digital lines are
properly terminated.
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Comlinear CLC018
8 x 8 Digital Crosspoint Switch, 1.4Gbps
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Lit #150018-002