7
Modulation Strategies
Michael Giesselmann
Texas Tech University
Hossein Salehfar
7.1
7.2
7.3
PWM Signals with DC Average • PWM Signals for
AC Output
University of North Dakota
Hamid A. Toliyat
7.4
Texas A&M University
Tahmid Ur Rahman
Texas A&M University
Introduction
Six-Step Modulation
Pulse Width Modulation
7.5
7.6
7.7
Third Harmonic Injection for Voltage Boost
of SPWM Signals
Generation of PWM Signals Using Microcontrollers
and DSPs
Voltage Source–Based Current Regulation
Hysteresis Feedback Control
Introduction • Principles of the Hysteresis Feedback Control
Circuits • Design Procedure • Experimental
Results • Conclusions
7.8
Space-Vector Pulse Width Modulation
How the SVPWM Works • Implementation • Switching
Signals
7.1 Introduction
Michael Giesselmann
In this chapter, modulation techniques for power electronics circuits are discussed. Modulation techniques are strategies to control the state of switches in these circuits. Switch mode is preferred to linear
operation since switches ideally do not dissipate any power in either the ON or OFF state. Depending
on the switches that are being used, it may only be possible to control the turn on instants. However,
most modern power semiconductors such as IGBTs can be turned on and off tens of thousands of times
per second on command. In parallel with the development of these modern power semiconductors, new
modulation techniques have emerged. In the following sections, a number of modulation techniques
along with their advantages and disadvantages will be discussed. Most figures have been generated using
MathCAD® 2000 [1]. The examples for the digital modulation techniques and the voltage source–based
current control techniques have been generated using PSpice®[2].
References
1. MathCAD® 2000 Professional, MathSoft Engineering & Education, Inc., 101 Main Street, Cambridge,
MA 02142-1521, http://www.mathsoft.com.
2. PSpice® Documentation, 555 River Oaks Parkway, San Jose, CA 95134, U.S.A.; (408)-943-1234;
http://pcb.cadence.com/.
© 2002 by CRC Press LLC
7.2 Six-Step Modulation
Michael Giesselmann
Six-step modulation represents an early technique to control a three-phase inverter. Six-step modulation
uses a sequence of six switching patterns for the three phase legs of a full-bridge inverter to generate a
full cycle of three-phase voltages. A switch pair connected between the positive DC bus and the negative
DC bus represents a phase leg. The output terminal is the midpoint of the two switches. Only one switch
of a phase leg may be turned on at any given time to prevent a short circuit between the DC buses. One
state of the inverter leg represents the case when the upper switch is turned on whereas the opposite state
is represented by the lower switch being turned on. If each phase leg has these two states, the inverter has
3
2 = 8 possible switching states. Six of these states are active states, whereas the two states in which either
all of the upper or all of the lower switches are turned on are called zero states, because the line-to-line
output voltage is zero in these cases. The six discrete switching patterns for six-step modulation are shown
in Fig. 7.1a to f. For clarity, free-wheeling diodes have been omitted. After the switching pattern shown
in Fig. 7.1f, the cycle begins anew with the switching pattern shown in Fig. 7.1a. Note that in subsequent
patterns, only a single inverter leg changes states. The switching patterns shown in Fig. 7.1a to f represent
the following inverter states in the following order:
•
•
•
•
•
•
Positive peak of Phase A
Negative peak of Phase C
Positive peak of Phase B
Negative peak of Phase A
Positive peak of Phase C
Negative peak of Phase B
The aforementioned inverter states are equally spaced in a circle with 60° of phase shift between them.
This is illustrated in Fig. 7.2. The hexagon in Fig. 7.2 represents the trace of a voltage vector around a
circle for six-step modulation. This scheme could be extended to space vector modulation, if the voltage
vector would not make discrete 60° steps, but would alternate at high speed between two adjacent states.
The switching control would be such that the average time spend in the previous state is gradually
decreasing, whereas the average time spent in the next state is gradually increasing. Also by inserting zero
states, the magnitude of the output voltage could be controlled.
Figure 7.3 shows the phase to neutral waveform of one inverter leg for six-step operation if the neutral point
is considered the midpoint between the positive and negative bus. The resulting line-to-line output voltage
is shown in Fig. 7.4. This waveform is closer to a sinusoid than the phase to neutral voltage but it still has a
considerable amount of harmonics. Figure 7.5 shows the spectrum of the line-to-line voltage for six-step
operation normalized to the fundamental frequency. The lowest harmonic component is the 5th harmonic.
The advantages of six-step modulation are the simplicity of the procedure and the ability to use slowswitching, high-power devices like GTOs. However, the harmonic content of the output voltage and the
inability to control the magnitude of the output voltage are serious drawbacks. Because of these drawbacks
and due to the recent advances in high-power IGBT technology, this modulation scheme is today seldom
considered for new designs.
7.3 Pulse Width Modulation
Michael Giesselmann
Pulse width modulation (PWM) is the method of choice to control modern power electronics circuits. The
basic idea is to control the duty cycle of a switch such that a load sees a controllable average voltage. To
achieve this, the switching frequency (repetition frequency for the PWM signal) is chosen high enough
that the load cannot follow the individual switching events. Switching, rather than linear operation of the
© 2002 by CRC Press LLC
FIGURE 7.1 (a) GTO inverter indicating conducting switches for step 1 in six step sequence. (b) GTO inverter
indicating conducting switches for step 2 in six-step sequence. (c) GTO inverter indicating conducting switches for
step 3 in six-step sequence. (d) GTO inverter indicating conducting switches for step 4 in six-step sequence. (e) GTO
inverter indicating conducting switches for step 5 in six-step sequence. (Continued)
© 2002 by CRC Press LLC
GTO3
3
GTO1
1
C
B
A
GTO6
6
(f)
FIGURE 7.1
(Continued.) (f) GTO inverter indicating conducting switches for step 6 in six-step sequence.
FIGURE 7.2
Graphical representation of the vector positions of the inverter states in a circle for six-step modulation.
FIGURE 7.3
Phase to neutral waveform of the inverter for six-step operation.
© 2002 by CRC Press LLC
FIGURE 7.4
Line-to-line waveform of the inverter for six-step operation.
FIGURE 7.5
Spectrum of the line-to-line voltage for six-step operation normalized to the fundamental frequency.
power semiconductors, is of course done to maximize the efficiency because the power dissipation in a
switch is ideally zero in both states. In a typical case, the switching events are just a “blur” to the load,
which reacts only to the average state of the switch.
PWM Signals with DC Average
There are a number of different methods to generate periodic rectangular waveforms with varying duty
cycle. A standard method is the so-called carrier-based PWM technique, which compares a control signal
with a triangular (or sawtooth shaped) waveform. Figure 7.6 shows an example of a triangular waveform
with 10-kHz repetition (switching) frequency. By comparing this signal with a reference level, which can
vary between 0 and 1 V, a PWM signal with a duty cycle between 0 and 100% is generated. Because of
the triangular carrier, the relation between the reference level and the resulting duty cycle is linear.
Figure 7.7 shows an example where a PWM signal with 80% duty cycle is created. This method works
very well for duty cycles in the range from 5% up to 95% as shown in Figs. 7.8 and 7.9. However, if the
reference signal exceeds 100% or falls below 0%, the resulting PWM signal would be always on or always
off, respectively. This is called overmodulation. This regime must be avoided by proper conditioning of
the control signal. In addition, for control signals resulting in PWM signals with duty cycle values as
high as 99% or as low as 1%, the switch may never fully reach the opposite state and spend an undue
amount of time in transitions. Therefore, it is typically recommended to limit the control signal to a
range, which avoids overmodulation as well as extremely narrow pulses.
© 2002 by CRC Press LLC
FIGURE 7.6
Triangular carrier wave for PWM modulation with a duty cycle between 0 and 100%.
FIGURE 7.7
Triangular carrier wave and PWM signal for 80% duty cycle.
FIGURE 7.8
Triangular carrier wave and PWM signal for 95% duty cycle.
© 2002 by CRC Press LLC
FIGURE 7.9
FIGURE 7.10
Triangular carrier wave and PWM signal for 5% duty cycle.
Spectrum of a PWM signal with 25% duty cycle.
The spectrum of a typical PWM signal with 25% duty cycle with a switching frequency of 10 kHz is
shown in Fig. 7.10. The DC magnitude of 25% is clearly visible. The harmonics are multiples of the
carrier frequency. The lowest harmonic is located at 10 kHz. This spectrum might look dramatic,
especially in comparison with Fig. 7.5, but the reader should be reminded that, due to the switching
speed of modern power semiconductors, the carrier frequency can be chosen sufficiently high that the
harmonics can be easily filtered with capacitors and inductors of small size.
PWM Signals for AC Output
In addition to a DC reference signal, any other waveform could be used as the modulation signal as long
as the highest frequency of its AC components are at least an order of magnitude less than the frequency
of the carrier signal. Figure 7.11 shows an example of a carrier waveform, which is symmetrical with
respect to the zero level. To generate a sinusoidal output voltage for an inverter, which is often desired,
this carrier can be modulated with a sinusoidal reference signal. An example is shown in Fig. 7.12. Note
that for clarity, the ratio between the carrier frequency and the frequency of the modulation signal is
lower than recommended for actual implementation. The resulting sinusoidal PWM (SPWM) voltage
drives one phase leg of an inverter. If the voltage level is +1, the upper switch is on, and vice versa. After
filtering out the switching frequency components, the resulting output voltage has the shape and frequency of the modulation signal. For the remaining phase legs, the same technique, with reference signals
© 2002 by CRC Press LLC
FIGURE 7.11
Triangular carrier wave AC modulation.
FIGURE 7.12
Illustration of the generation of sinusoidal PWM (SPWM) signals.
that are phase shifted by 120 and 240°, is used. The amplitude of the output voltage can be controlled
by varying the ratio between the peak of the modulation signal and the peak of the carrier wave. If the
amplitude of the modulation signal exceeds the amplitude of the carrier, overmodulation occurs and the
shape of the fundamental of the output voltage deviates from the modulation signal.
To appreciate the spectral content of sinusoidal PWM signals, a 20-kHz triangular carrier has been modulated with a 500-Hz sinusoid with an amplitude of 80% of the carrier signal. The resulting SPWM signal is
shown in Fig. 7.13. The spectrum of this PWM signal is shown in Fig. 7.14. The fundamental with an amplitude
of 0.8 is located at 500 Hz. The harmonics are grouped around multiples of the carrier frequency [1].
It should be pointed out that this modulation scheme is far superior to the six-step technique described
earlier, because the difference between the switching frequency and the fundamental is much larger.
Therefore, the carrier frequency components can be easily removed with LC filters of small size [2]. In
addition, the amplitude of the output voltage can be controlled simply by varying the amplitude ratio
between the modulation signal and the carrier. If six-step modulation is used, the DC bus voltage would
have to be controlled in order to control the amplitude of the output voltage.
© 2002 by CRC Press LLC
20-kHz carrier modulated with 500 Hz
1
0.5
SPWM(t)
Sin(t)
0
0.5
1
0
0.2
0.4
0.6
0.8
1
t
ms
FIGURE 7.13
20-kHz carrier modulated with 500 Hz.
FIGURE 7.14
Spectrum of the SPWM signal shown in Fig. 7.13.
1.2
1.4
1.6
1.8
2
References
1. Mohan, N., Undeland, T., and Robbins, W., Power Electronics: Converters, Applications, and Design,
2nd ed., John Wiley & Sons, New York, 1995.
2. Von Jouanne, A., Rendusara, D., Enjeti, P., and Gray, W., Filtering techniques to minimize the effect
of long motor leads on PWM inverter fed AC motor drive systems, IEEE Trans. Ind. Appl., July/Aug.,
919–926, 1996.
7.4 Third Harmonic Injection for Voltage Boost of SPWM Signals
Michael Giesselmann
It can be shown (Mohan et al.[1], p. 105) that if a three-phase input voltage is rectified using a standard
three-phase rectifier, the resulting DC voltage is equal to 1.35 times the rms value of the AC line–line
input voltage. If this DC voltage is used to feed a three-phase inverter using the SPWM modulation
technique described above, the theoretical maximum AC line–line output voltage is only 82.7% of the
AC line–line input voltage feeding the rectifier (Mohan et al.[1], p. 228). To boost the output voltage
without resorting to overmodulation, the third harmonic of the fundamental frequency can be added to
the modulation signal. Figure 7.15 shows an example, where a third harmonic with an amplitude of
21.1% has been added to the fundamental modulation signal.
© 2002 by CRC Press LLC
FIGURE 7.15
Sinusoidal modulation signal with and without added 3rd harmonic.
FIGURE 7.16
Line-to-line signal showing the voltage boost obtained by 3rd harmonic injection.
The amplitude of the fundamental has been increased to 112% in this example. It can be seen, that
the peak amplitude of the resulting signal does not exceed the amplitude of the pure sinusoid with
100% amplitude. By inspection of Fig. 7.15 it is easy to see that the voltage–time integral will be higher
if a 3rd harmonic is added to the reference signal for the phase to neutral voltage. This voltage boost
beyond the previously mentioned value of 82.7% is very desirable, to retrofit induction motors with
adjustable speed drives in existing installations. The 3rd harmonic components exactly cancel each other
in the line-to-line voltages of the inverter. This is because the phase shift of the fundamental signals is
120° and therefore the phase shift of the 3rd harmonic is 3 × 120 = 360°. Therefore, the 3rd harmonic
voltages precisely cancel and result in a pure sinusoidal output voltage being applied to the motor. This
is shown in Fig. 7.16, which illustrates the voltage boost that is obtained.
© 2002 by CRC Press LLC
Reference
1. Mohan, N., Undeland, T., and Robbins, W., Power Electronics: Converters, Applications, and Design,
2nd ed., John Wiley & Sons, New York, 1995.
7.5 Generation of PWM Signals Using Microcontrollers
and DSPs
Michael Giesselmann
Modern power electronics controllers are rapidly moving toward digital implementation. Typical solutions consist of microcontrollers or DSPs. In addition, coprocessors, such as the ADMC200/201 from
Analog Devices, are available that are specifically designed to support inverter control. Most of the
processors, such as the 68HC12B32 from Motorola, that are commonly used to control power electronics
have built-in hardware support for PWM generation. Figure 7.17 shows the basic principle of their digital
PWM generation.
For clarity, the circuit shown in Fig. 7.17 has only 4-bit resolution for the duty cycle of the generated
PWM signals, resulting in only 16 discrete duty cycles. In actual applications, 8 to 12 bits of resolution
is typical. In Fig. 7.17, a digital counter (74163) counts from zero to its maximum value and repeats the
cycle afterward. The count is continuously compared with a digital value representing the duty cycle
using a hardware comparator (7485). The PWM signal is available on the output of the comparator.
Figure 7.18 shows the simulation results from the example circuit shown in Fig. 7.17. The duty cycle in
this example is 3/16.
If more than one channel is present, the PWM signals can be left, right, or center aligned. To be center
aligned, up–down counters are used, which count up to their maximum count and then back to zero
bits
before starting the next cycle. The maximum count (2 − 1) is determined by the number of stages
(bits) the digital counter has. In a digital PWM modulator each counter has an associated period register.
The content of this register determines the maximum count at which the counter resets. If this number
bits
is less than the maximum count (2 − 1), the repetition (switching) frequency is increased and the
FIGURE 7.17
Principle of digital PWM signal generation.
FIGURE 7.18
Simulation results from the circuit shown in Fig. 7.17.
© 2002 by CRC Press LLC
resolution of the duty cycle is decreased for a given clock speed. It is often important to make the correct
trade-off between the switching frequency and the resolution.
The advantage of hardware support for PWM generation is that the processor typically only needs to
access any registers if the duty cycle is to be changed, since the period is typically only initialized once
upon program start-up. It should also be mentioned that the duty cycle registers are typically “doublebuffered,” meaning that an update of a duty cycle does not need to be synchronized with the current
state of the counter. In double-buffered systems, the new duty cycle will only be chosen once the previous
period is completed to avoid truncated PWM signals. If necessary, a software override can disable this
feature.
7.6 Voltage Source–Based Current Regulation
Michael Giesselmann
In motor drive applications, it is often desired to control directly the input current of the motor to control
the torque. DC control also limits dynamics resulting from the electrical characteristics of the machine.
Controlling the torque provides direct control over the angular acceleration, which is essential for precise
motion control. Current control is typically performed in the innermost loop of a cascaded feedback
control loop arrangement [1]. However, most power electronics converters are circuits with controllable
voltage output. To achieve current control, the voltage of the power electronics converter can be controlled
in such a way, that the desired current is obtained. Several methods can be used to achieve this:
• A feedback control loop, typically using a PI controller can be used control the current.
• The necessary voltage can be calculated in real time and applied to the motor.
• The necessary voltage for fast transients can be calculated in real time and applied to the motor
and the residual error can be corrected by a PI controller.
Examples illustrating each of the schemes are described in the following. Figure 7.19 shows an example
of a DC motor in which the current is controlled by adjusting the applied voltage using a PI controller
such that the current follows the desired trajectory. The result is presented in Fig. 7.20, which shows that
the current indeed follows the desired value at all times.
Sometimes even better results and higher loop bandwidth can be obtained if known information about
the motor and the load is used to calculate the required voltage in real time. Figure 7.21 shows some
fundamental equations of a permanent magnet (PM) DC motor. Here a capacitor is used to represent
the kinetic energy stored in the machine. Therefore, the second voltage loop equation in Fig. 7.21
represents the voltage across the motor at all times. To test this theory, the “compensator” in the circuit
shown in Fig. 7.22 calculates this voltage and applies the result to the DC motor. The subcircuit of the
FIGURE 7.19
Voltage source–based current control using a PI feedback loop.
© 2002 by CRC Press LLC
FIGURE 7.20
Simulation result for the circuit shown in Fig. 7.19.
d
Vs = Rrot⋅Irot + Lrot⋅ − Irot + Km⋅ω
dt
1
1
−⋅Ceq⋅E2
−⋅J⋅ω2 = 2
2
d
Vs = Rrot⋅Irot + Lrot⋅−Irot + 1
−⋅
Ceq
dt
Voltage loop equation
Ceq = J⋅
ω
2
2
E
= J2
Km
Irot dt
Equivalent Capacitance
Voltage loop equation
FIGURE 7.21
Fundamental equations for the PM DC machine.
FIGURE 7.22
Voltage source–based current control using a feedforward approach.
compensator is shown in Fig. 7.23. The result is identical to that shown in Fig. 7.20. However, for the
correct implementation of this scheme, the load and the inertia of the system needs to be known precisely,
which is not realistic. Therefore, the best strategy is to implement the first two terms on the right side
of the second voltage loop equation in Fig. 7.21 using a compensator and to use a PI controller to eliminate
the residual error.
The advantage of the mixed (compensator and PI residual controller) approach is that the fast dynamics
are covered by the feedforward path through the compensator, whereas the effect of the slower integral
term is taken care of by the PI controller. The compensator will immediately apply the correct voltage to
overcome the ohmic resistance of the winding and to establish the correct current slope in the rotor inductance. As the machine accelerates, the PI controller adds the appropriate voltage to offset the back-emf
© 2002 by CRC Press LLC
FIGURE 7.23
Subcircuit for the compensator shown in Fig. 7.22.
FIGURE 7.24 Voltage source–based current control using a feedforward approach for the fast transients and a PI
controller for the residual error.
of the motor. An example for this approach is shown in Fig. 7.24. Again, the results are identical to the
ones shown in Fig. 7.20.
Reference
1. Mohan, N., Electric Drives, An Integrative Approach, MNPERE, Minneapolis, MN, 2001.
7.7 Hysteresis Feedback Control
Hossein Salehfar
This section presents a hysteresis feedback control technique for DC-DC buck converters operating in
both continuous and discontinuous conduction modes. A dead band with a high boundary above the
voltage reference and a low boundary below the voltage reference are used to avoid chattering in the
switch. The output voltage is regulated by comparing it to a reference voltage and the difference between
the two voltages (error) is used to turn ON or OFF the switch. Regardless of where the voltage starts,
switching takes place as soon as a boundary is encountered.
Initially, the switch turns ON because the output voltage of the converter is below the turn-on boundary.
The output voltage then rises at a rate limited only by the inductor, the capacitor, and the load. The
switch then turns OFF when the output voltage crosses the upper boundary and it remains OFF until
© 2002 by CRC Press LLC
the output voltage falls below and crosses the lower boundary where the switch is turned ON again. Once
the voltage is between the upper and lower boundaries, switching actions will keep it in that vicinity
under all conditions. This type of operation becomes independent of line, load, inductor, and capacitor
values. Hysteresis control in principle eliminates the output variations other than the ripples. The system
will stay close to the desired output voltage even if the input voltage, the load, or the component values
change. Hysteresis control also provides an immediate response to dynamic disturbances. The control
circuit is very simple and relatively straightforward to design and physically implement.
Introduction
Because of their high efficiency, compact size, and low cost, switching power supplies continue to gain
popularity. Switching power supplies could be as high as three times more efficient than linear power
supplies and in some cases eight times smaller in size. The heart of a switching power supply is its switch
control circuit. Generally, the control circuit is a negative-feedback control loop connected to the switch
through a comparator and a pulse width modulator (PWM). This control circuit regulates the output
voltage against changes in the load and the input voltage. A feedforward loop may also be used to
compensate for changes in the input voltage. Several topologies of switching power supplies have been
developed and used. DC-DC buck converters are one of the widely used topologies.
The PWM-based voltage and current mode feedback controllers used in buck converters are widely
used to improve line regulation [1]. Apparently, however, PWM voltage mode controllers have disadvantages. Since the input voltage is a significant parameter in the loop gain, any changes in the input
voltage will alter the gain and will change the dynamics of the system. The central issue is that a voltage
mode controller alone cannot correct any disturbances or changes until they are detected at the output.
In the voltage-based controllers the compensation loop is difficult to implement. A limitation of the
current mode controllers is the limit on the duty ratio. If the duty ratio exceeds 50%, then instability
occurs [1]. In the current mode controllers a sensing resistor is used in the current loop, which increases
the power losses in the converter. Most feedback controllers in buck converters use both the PWM voltage
and current mode controllers to produce a better steady-state response and to reduce the voltage overshoots
during start-ups.
Feedforward controllers may also be used to improve the line regulation in applications with a wide
range of input voltages and loads [1, 2]. An apparent disadvantage of these types of controllers, however,
is that the feedforward scheme with its direct sensing of the input quantities may have adverse effects
when the converter is subjected to abrupt line transients. The sensing of input voltage through the
feedforward loop may induce large-signal disturbances that could upset the normal duty cycle of the
control mode. These concerns appear to be legitimate in light of the fact that such an effect is often
observed with other forms of feedforward controls as well [2].
Most buck converters are designed for a continuous-current mode operation [3]. What if changes in
the load or input voltage cause the system to operate in a discontinuous-current mode? In these situations,
a voltage-based hysteresis feedback control circuit is a viable alternative [4–6]. Hysteresis feedback controllers enable buck converters to operate in both continuous- and discontinuous-current modes. With
the ability of the system to operate in both modes, the size of the inductor and the capacitor are minimized
compared with the other standard converters where a minimum size of the inductor is required to produce
a continuous-current mode [3]. A minimum size of the capacitor is also required to limit the output
voltage ripples as well. The output voltage of a hysteresis controller is stable and exhibits a robust behavior.
The output is maintained even under extreme changes in the load, the line, or in the component values
[4]. In some cases, the hysteresis controller determines the output ripple. The voltage-based hysteresis
feedback controller presented in this section combines the advantages of both the PWM voltage and
current-based controllers but it does not require a PWM circuit. It needs only a comparator circuit,
which make it simpler and cheaper to build. Hysteresis controllers work well with DC-DC buck converters.
But they do not work with other types of DC converters. If they are used, for example, with a boost
converter, the results could be disastrous [4].
© 2002 by CRC Press LLC
Vref
Vo
+
+
+
Vcc
-
+V
GS
S1
+
L
+
Vin
S2
C
Rload
Vout
-
-
FIGURE 7.25
The basic circuit of a hysteresis controller for buck converters.
Principles of the Hysteresis Feedback Control Circuits
The main function of a DC-DC converter is to provide a good output voltage regulation. The output
voltage must be maintained at the desired level against all changes in the input voltage or the load. The
converter must act quickly to correct errors in the output voltage due to changes in the input voltage or
in the load.
Figure 7.25 shows the basic circuit of the hysteresis controller for a buck converter. The circuit consists
of a comparator and a switch (transistor). The comparator compares the output voltage Vout to a
reference voltage Vref. If Vout > Vref, the switch is turned OFF. If Vout < Vref, the switch is turned ON. This
process repeats and Vout is maintained at a value close to Vref. However, the circuit in Fig. 7.25 leads to
chattering in the switch. In an attempt to keep Vout equal to Vref, the switch chatters when it rapidly
turns ON and OFF as Vout moves back and forth across Vref. In power converters, an excessively fast
switching action associated with chattering is destructive and it is therefore essential to avoid this
condition.
Chattering is eliminated in hysteresis controllers by creating a dead band around Vref. The dead band
is created by using an upper boundary above Vref and a lower boundary below Vref. The space between
the two boundaries is the dead band. Figure 7.26 shows the circuit of the hysteresis controller with a
dead band. R1 and R2 resistors are added to the control circuit to provide the required dead band. The
values of R1 and R2 determine the upper boundary and the lower boundary of the dead band.
The comparator in Fig. 7.26 is a Schmitt trigger. The input voltage V+ of the positive terminal of the
op-amp is no longer a fixed reference voltage Vref as is the case in the basic comparator (without R1 and
R2) in Fig. 7.25. V+ now depends on Vref, Vo, R1, and R2. It switches from one boundary of the dead band
to another. During the initial start-up of the buck converter, the input to the negative terminal (−) of
the op-amp (Vout) is a small positive value and is less than V+. The amplifier will be saturated so that
© 2002 by CRC Press LLC
Feedback Control Circuit
Vref
R2
V cc
R1
Vo
V+
+
-
+
VGS
+
L
S1
+
Vin
C
S2
Rload
Vout
-
-
FIGURE 7.26
The basic circuit of the hysteresis controller with a dead band.
Vo = Vcc, thus the switch is turned ON. V+ then becomes
R2 Vo
R 1 V ref
- + ---------------V + = ---------------R1 + R2 R1 + R2
(7.1)
As time progresses, Vout will increase gradually in the positive direction. The output voltage, Vo, remains
unchanged at Vcc until Vout is equal to V+. The op-amp will then enter its linear region and Vo will decrease
and thus V+ will decrease as well. This process will continue until Vo reaches zero and the op-amp will
again saturate. The voltage V+ will no longer be given by Eq. (7.1) but is given:
R 1 V ref
V + = ---------------R1 + R2
(7.2)
Equations (7.1) and (7.2) represent the control boundaries of the control circuit. Equation (7.1) defines
the upper boundary and Eq. (7.2) gives the lower boundary of the dead band. The dead band is computed
by subtracting Eq. (7.2) from Eq. (7.1). The dead band is given by Eq. (7.3).
R2 Vo
∆D b = ---------------R1 + R2
R1 and R2 may be chosen to give the required value of ∆Db /Vo.
© 2002 by CRC Press LLC
(7.3)
Vout
Upper Boundary
Vupper
Vref
Vlower
Transistor OFF
Transistor ON
Lower Boundary
VGS
0
FIGURE 7.27
time
Time behavior of a buck converter under hysteresis control.
When the output voltage Vout is inside the dead band, the switch is OFF. Regardless of where the voltage
starts, switching starts as soon as a boundary is encountered. In Fig. 7.27 the converter start-up process
is illustrated. The transistor turns ON initially because the output voltage Vout is below the turn-on
boundary. The output voltage rises from 0 to Vupper at a rate limited only by the inductor (L), the capacitor
(C), and the load. The transistor then turns OFF as the voltage crosses the upper boundary and remains
OFF until the output voltage falls below and crosses the lower boundary where the transistor is turned
ON at Vlower . Once the voltage is between the boundaries, switching actions will keep it within the control
boundaries under all conditions.
The operation of the system becomes independent of the line, the load, the inductor, and the capacitor
values. The system will stay close to the desired output voltage Vref even if the component values or the
load changes drastically. A major drawback of this, however, is that the controller gives rise to an
overvoltage during start-ups. But this problem can be solved by choosing the correct inductor and
capacitor values that will allow the system to rise exponentially and settle somewhat close to the desired
output voltage, while maintaining the desired ripple voltage. Initial voltage overshoots during start-ups
can sometimes damage loads that are sensitive to high voltages or they may trigger the overvoltage
protection circuits. Thus, it is essential to prevent such occurrences from happening.
Design Procedure
In the steady-state mode, the output voltage of the converter depends on the input voltage (Vin), the
switching frequency (fs ), and the on duration of the switching period (ton). This output voltage is given
in Eq.(7.4):
V out = t on f s V in = DV in
© 2002 by CRC Press LLC
(7.4)
The product ton fs is defined as the duty ratio D. The output voltage Vout is regulated by changing D while
fs is kept constant. This method is widely used in DC-DC converters. Another approach to regulating
Vout is to vary fs and keep D constant. However, this method is undesirable because it is difficult to filter
the ripples in the input and output signals of the converter.
The hysteresis control of the buck converter is a fixed boundary control. Vout is regulated by the
switching action of the switch as Vout crosses the upper or the lower boundary of the dead band of the
hysteresis. In the hysteresis control of converters, fs as well as D are not fixed values, but they change with
the converter conditions. For a given set of converter parameters, both fs and D are determined by the
boundaries of the hysteresis. The frequency fs and the duty ratio D are not used as control parameters
in the design of hysteresis controllers. However, using a hysteresis controller, the basic operating principles
of the buck converter do not change. The output voltage ripples of the converter depend on the dead
band of the controller. As the dead band increases or decreases, the output voltage ripples will increase
or decrease as well. The voltage ripple specifications can be guaranteed by setting the dead band of the
controller at 50% of the ripple specifications with a suitable inductor value.
A properly designed hysteresis controller has excellent steady-state and dynamic properties. Its response
quickly changes from its starting point to its desired operating value. Fixed boundary controllers have
some important operating advantages. These controllers are stable under extreme disturbance conditions
and can be chosen to directly guarantee the ripple specifications or other operating issues in a converter.
The implementation of the hysteresis controller is illustrated by a design example.
Design Example
A DC-DC buck converter with voltage-based hysteresis control is designed to verify the method discussed
in this section. Let Vout = 5 V and let the load vary between 1 and 5 Ω. The input voltage Vin also varies
between 16 and 24 V with a nominal value of 20 V. The maximum ripple voltage is set at ±1%. A nominal
switching frequency of fs = 100 kHz is chosen. The output voltage ripple is then
∆V out
------------- = 2%
V out
(7.5)
∆V out = 0.02 × 5 = 0.1 V
The dead band is chosen to be 50% of the output voltage ripple to account for the small increase in
the ripple level due to the natural response of the RLC circuit of the converter, after the switch is turned
OFF, and to meet the required voltage ripple specification. The system will not meet the voltage ripple
specification if the dead band is chosen to be equal to the output voltage ripple. The dead band is then
∆D b = 0.5 × 0.1 = 0.05 V
(7.6)
Vo
R 1 = R 2  --------- – 1
 ∆D b 
(7.7)
Eq. (7.3) is solved for R1:
Let R2 = 100 Ω and Vo = 10 V. Then R1 is
R1 = 100(10/0.05 − 1) = 19900 Ω
These resistor values produce a dead band that meets the output ripple specification. The maximum and
minimum values of the load current are
Iout,max = Vout/Rmin = 5/1 = 5 A
© 2002 by CRC Press LLC
(7.8)
and
Iout,min = Vout/Rmax = 5/5 = 1 A
(7.9)
Let the inductor current and the capacitor voltage swings be 10%. The inductor must limit the current
swing at maximum load. The total current swing is as follows. Since
∆I L
------------- = 10%
I out,max
using Eq. (7.8), Iout,max = 5 A, then
∆I L = 0.1 × 5 = 0.5 A
(7.10)
The capacitor voltage swing is
∆V
------------c- = 10%
∆V out
∆V c = 0.1 × 0.1 = 0.01V
(7.11)
The equivalent series resistance (ESR) of the capacitor C must be included in the calculations. Since the
waveform of the output ripple voltage is approximately sinusoidal, the output ripple voltage is then
∆V out =
2
( ∆V c ) + ( ∆V RC )
2
(7.12)
where ∆VRC is the voltage ripple across the capacitor resistance RC. Note that ∆VRC is usually much
greater than ∆Vc. Thus a close approximation of the peak-to-peak output voltage ripple is obtained as
follows:
∆V out ≅ ∆V RC
≅ ∆I c R c
≅ ( ∆I L – ∆I R )R c
(7.13)
With the result from Eq. (7.10), the inductor L is
V out ( V in – V out )
5 ( 20 – 5 )
L = -----------------------------------= ----------------------------------- = 75 mH
V in f s ∆I L
20 ( 100000 )0.5
(7.14)
The value of the capacitor is
∆I L
0.5
- = ----------------------------------- = 62.5mF ≅ 65mF
C = --------------8f s ∆V c
8 ( 100000 )0.01
(7.15)
The value of ESR of the capacitor can be determined from Eq. (7.13):
∆V out
0.1
- = -------------------- = 0.25 Ω
R C = --------------------∆I L – ∆I R
0.5 – 0.1
© 2002 by CRC Press LLC
(7.16)
FIGURE 7.28
The output voltage of the buck converter using feedback hysteresis control.
The output waveform of the buck converter at 1 A load is shown in Fig. 7.28. As can be seen in Fig. 7.28,
there are no excessive voltage overshoots during the start-up of the converter and Vout is kept within the
specified boundaries of the hysteresis.
Transient overshoots, undershoots, and recovery times to step changes in the load and in the input
are important performance parameters in buck converters. Since the current in the inductor cannot
change instantaneously, the transient response is inherently inferior to that of the linear converters. The
recovery time to step changes in the line and in the load is controlled by the characteristic of the feedback
loop of the controller. Transient overshoots and undershoots resulting from step load changes can be
analyzed and calculated in the following manner. The AC output impedance is
V in – V out
Z out = --------------------∆I load
(7.17)
di
V L = −L -------L
dt
(7.18)
Since
© 2002 by CRC Press LLC
and
dv
I out = C ----dt
(7.19)
L∆I out
Z out = -----------------------------( V in – V out )C
(7.20)
thus,
As a result, for an increasing current, the change in the output voltage will be as follows:
2
L∆I out
∆V out,min = ∆I out Z out = -----------------------------( V in – V out )C
(7.21)
and for a decreasing current, the change in the output voltage is
2
L∆I out
∆V out,max = -------------V out C
(7.22)
The transient undershoot for a load change from 1 to 5 A can be determined from Eq. (7.21).
2
2
L∆I out
0.000075 ( 5 – 1 )
- = ----------------------------------------- = 1.231 V
∆V out,min = -----------------------------( V in – V out )C
( 20 – 5 )0.000065
(7.23)
The transient overshoot for the load change from 5 to 1 A can be determined using Eq. (7.22).
2
2
L∆I out
0.000075 ( 5 – 1 )
∆V out,max = -------------= ---------------------------------------- = 3.692 V
V out C
5 ( 0.000065 )
(7.24)
Simulation Results
A DC-DC buck converter with a hysteresis feedback control circuit is constructed and simulated using
the PSpice program. The results of the simulation were then compared to the theoretical results obtained
in Eqs. (7.23) and (7.24) above. Figure 7.29 shows the results from the simulation. The transient behavior
of the output voltage and the current of the converter can be obtained from Fig. 7.29. The maximum
transient overshoot voltage for a load change from 5 to 1 A is found to be
∆V out,max = 6.3463 – 5 = 1.3463 V
(7.25)
and the minimum transient undershoot voltage for a load change from 1 to 5 A is
∆V out,min = 5.0 – 3.4724 = 1.5276 V
(7.26)
These results show that the controller has significantly reduced the overshoot transient. The overshoot
value from the simulation is 36.47% of the theoretical value obtained using Eq. (7.24). However, a small
increase in the undershoot transient is observed. The undershoot value from the simulation increased
by 24.1% compared to the value obtained from Eq. (7.23). One can also see that the system has gone
from a continuous-current mode to a discontinuous-current mode and back to a continuous-current
mode. The switch is turned OFF when the output voltage crosses the upper boundary. The system then
degrades linearly until it is back into a continuous-current mode where the switch is turned ON again
and it continues its switching operation within the continuous-current mode region.
© 2002 by CRC Press LLC
FIGURE 7.29 Simulation results, showing the transient analysis of the output voltage and current of the hysteresis
feedback control for DC-DC buck converters.
Experimental Results
A DC-DC buck converter with a hysteresis feedback control circuit was physically built to verify the
method under variable input and load conditions. The converter was built using an International Rectifier
IRF540 power MOSFET, an International Rectifier Schottky MBR1045 diode, an inductor L = 75 µH,
and a filter capacitor C = 65 µF. The DC input voltage, Vin, was set between 16 and 24 V, the nominal
output voltage, Vout, was 5 V and the load resistance Rload was set between 1 and 5 Ω. The hysteresis
feedback control circuit was built using a Motorola MC34081 operational amplifier as a comparator with
a slew rate of 25 V/µS and resistors R1 = 19900 Ω, R2 = 100 Ω. The resulting waveforms were observed
using the Lab-View program on a Pentium II PC. The output voltage waveform of the converter for a
load change from 1 to 5 A, and vice versa, is shown in Fig. 7.30 with the input voltage Vin fixed at a
nominal value of 20 V.
As expected, the transient undershoot for a load change from 1 to 5 A is found to be
∆V out,min = 5.05 – 4.55 = 0.5 V
(7.27)
which is 32.73% of that obtained from simulation and 40.62% of the theoretical value determined by
Eq. (7.23). The transient overshoot for a load change from 5 to 1 A is found to be
∆V out,max = 5.75 – 5.05 = 0.7 V
(7.28)
which is 51.99% of that obtained from simulation and 18.96% of the theoretical value obtained using
Eq. (7.24). The recovery time to the steady-state value of 5 V after an overshoot or undershoot is somewhat
© 2002 by CRC Press LLC
FIGURE 7.30
The transient response of the output voltage as load changes from 1 to 5A, and vice versa.
FIGURE 7.31
The transient response of the output voltage for a load change from 2 to 3 A, and vice-versa.
longer as compared to that from the simulation. This is due to the natural response of the RLC circuit
in the system. The response decays gradually toward the steady-state value.
Figure 7.31 shows another transient response for a load change from 2 to 3 A, and vice versa. Here
the recovery time to the steady-state value of 5 V is much shorter compared to the result shown in
Fig. 7.30. Because the overshoot and the undershoot transients in this case are minimal, the resulting
response time is much faster. This is mainly because the switching frequency is dependent on the natural
response of the RLC circuit. The switching will only occur when the transient is within the boundary
limits. Thus, one of the disadvantages of this type of feedback controller is a slower response time.
The waveform of the start-up transient response of the converter at 1-A load is shown in Figs. 7.32
and 7.33. These figures indicate that there are no excessive voltage overshoots during the start-up of the
converter. Furthermore, the output ripple voltage of the converter is within the desired specification.
© 2002 by CRC Press LLC
FIGURE 7.32
The start-up transient response at 1-A load.
FIGURE 7.33
Zoom-in for the start-up transient response at 1-A load in Fig. 7.32.
From Fig. 7.33, one finds the ripple voltage to be
∆V out = 4.995 – 4.97 = 0.025 V = 25 mV
(7.29)
which is five times less than the desired specification. The waveform of the start-up transient response
of the converter at 5 A load is shown in Figs. 7.34 and 7.35. As expected, here also there are no excessive
voltage overshoots during the start-up.
© 2002 by CRC Press LLC
FIGURE 7.34
The start-up transient response at 5-A load.
FIGURE 7.35
Zoom-in for the start-up transient response at 5-A load in Fig. 7.34.
The output voltage ripple of the buck converter is still within the desired specification. From Fig. 7.35,
the ripple voltage is determined to be
∆V out = 5.05 – 5.02 = 0.03 = 30 mV
(7.30)
which is within the desired specification. The waveform of the output voltage due to changes in the input
voltage is shown in Fig. 7.36. The input voltage was sequentially changed from the nominal value of 20 V
to 16 V to 24 V to 16 V and back to 20 V again. The load was fixed at 1 A.
As can be seen from Fig. 7.36, there is a small discrepancy in the output voltage due to changes in the
input voltage. The output voltage is no longer maintained at a steady-state value of 5 V. Moreover, at the
switching times between different levels of the input voltage, the output seems to decrease suddenly to
zero and then returns back to a value close to 5 V. However, these sudden and sharp drops in the output
voltage were not actually observed on the scope used for measurements. These sharp voltage drops seem
to be caused by the slow response of the data acquisition card used in the experiment. Figure 7.37 shows
another output voltage transient response to the same input voltages as the previous case except now the
© 2002 by CRC Press LLC
FIGURE 7.36
The output voltage response to various step changes in the input voltage at 1-A load.
FIGURE 7.37
Output voltage response to various step change of input voltage at 2.5-A load.
load was fixed at 2.5 A. As Fig. 7.37 shows, there is an increase in the discrepancy of the output voltage.
As the load increases and the input voltage decreases, the output voltage drops proportionally. But, on
the other hand, as the input voltage increases, the output voltage maintains its steady-state value close
to 5 V.
Conclusions
A voltage-based hysteresis feedback control circuit for DC-DC buck converters has been discussed in this
section. Details of the design and analysis of the control circuit were presented. The basic concept of the
controller was verified using simulation and actual experimental results. Results have shown that the buck
converter with hysteresis control has a good load regulation. Line regulation is good over a wide range
of load values. However, line regulation is good only over a limited range of input voltage values. The
best values of line regulation were obtained at low-load resistance values. The buck converter with
© 2002 by CRC Press LLC
hysteresis control is simple to design and implement and it is suitable for practical applications. The
hysteresis feedback loop decreases the overshoots in the buck converter. Results have also shown that the
switching frequency of the buck converter with hysteresis control is dependent on the RLC circuit of
the converter which causes a slow response time. A study of the dynamic behavior of the hysteresis
controller to improve its response time is recommended for future research.
References
1. R. E. Tarter, Solid-State Power Conversion Handbook, Wiley, New York, 1993, 484–491.
2. S. S. Kelkar and F. C. Y. Lee, A fast time domain digital simulation technique for power converters:
application of a buck converter with feedforward compensation, IEEE Trans. Power Electron., PE-1,
21–31, January 1986.
3. D. W. Hart, Introduction to Power Electronics, Prentice-Hall, Englewood Cliffs, NJ, 1997, 194.
4. P. T. Krein, Elements of Power Electronics, Oxford University Press, New York, 1998, 666–674.
5. E. Vosicher and E. Lougee, Hysteretic controller fits process needs, PCIM Power Electron. Syst. Mag.,
January 2000.
6. L. Hodson and R. Nowakowski, Hysteretic controller IC enables PC power supply to meet advanced
CPU requirements, PCIM Power Electron. Syst. Mag., July 2000.
7.8 Space-Vector Pulse Width Modulation
Hamid A. Toliyat and Tahmid Ur Rahman
One of the most preferred pulse width modulation (PWM) strategies today is space-vector modulation
(SVPWM). This kind of scheme in voltage source inverter (VSI) drives offers improved bus voltage
utilization and less commutation losses. Three-phase inverter voltage control by space-vector modulation
includes switching between the two active and zero voltage vectors so that the time interval times the
voltages in the chosen sectors equals the command voltage times the time period within each switching
cycle. During the switching cycle the reference voltage is assumed to be constant as the time period
would be very low. By simple digital calculation of the switching time one can easily implement the
SVPWM scheme. However, the switching sequence may not be unique.
How the SVPWM Works
For a three-phase voltage source inverter as depicted in Fig. 7.38, each pole voltage may assume one of
the two values depending upon whether the upper switch or the lower switch is on. Therefore, only
eight combinations of switches are possible; these are shown in Fig. 7.39. Of these, two of them have
zero states. Zero states occur when either the upper three or the lower three switches are conducting
simultaneously.
The switches are termed as SA1, SA2 for pole A, SB1 and SB2 for pole B, and SC1 and SC2 for pole
C. Different states are defined as follows:
A = 0 if SA1 off and SA2 on
1 if SA1 on and SA2 off
B = 0 if SB1 off and SB2 on
1 if SB1 on and SB2 off
C = 0 if SC1 off and SC2 on
1 if SC1 on and SC2 off
© 2002 by CRC Press LLC
SA1
SB1
SC1
SA2
SB2
SC2
Vdc
FIGURE 7.38
Six-switch voltage source inverter.
The instantaneous values of the line-to-line voltages of the inverter can be obtained from the above
logic relations given by
V AB = V dc ( A – B )
V BC = V dc ( B – C )
(7.31)
V CA = V dc ( C – A )
where Vdc is the DC bus voltage and VAB, VBC, VCA are the line-to-line voltages. The line-to-neutral voltages
are given by
1
V A = -- ( V AB – V CA )
3
1
V B = -- ( V BC – V AB )
3
1
V C = -- ( V CA – V BC )
3
(7.32)
Replacing the values of line-to-line voltages in the previous set of equations yields the line-to-neutral
voltages of the inverter:
V
V A = ------dc- ( 2A – B – C )
3
V
V B = ------dc- ( 2B – C – A )
3
V
V C = ------dc- ( 2C – A – B )
3
© 2002 by CRC Press LLC
(7.33)
State 2 : [ 1 1 0 ]
State 1 : [ 1 0 0 ]
+
+
Vdc
Vdc
-
-
A
B
A
C
C
State 4 : [ 0 1 1 ]
State 3 : [ 0 1 0 ]
+
+
Vdc
Vdc
-
-
A
B
A
C
B
C
State 6 : [ 1 0 1 ]
State 5 : [ 0 0 1 ]
+
+
Vdc
Vdc
-
-
A
B
A
C
B
C
State 8 : [ 1 1 1 ]
State 0 : [ 0 0 0 ]
+
+
Vdc
Vdc
-
-
A
FIGURE 7.39
B
B
A
C
B
C
Possible switching pattern of the inverter.
For state 1, the values are
2
V A = --V dc
3
1
V B = – --V dc
3
1
V C = – --V dc
3
© 2002 by CRC Press LLC
(7.34)
By using the following transformation for a balanced three-phase system, the space vector for sector
1 with α and β components is given by
V sa
V sb
=
2 1
-3 0
cos 120°
sin 120°
VA
cos 240°
VB
cos 240°
VC
(7.35)
Therefore, for the first sector space vector Vs1 will be given by
V s1 =
2
j0
-- V dc e
3
(7.36)
2
j ( k−1 )60°
-- V dc e
3
(7.37)
All the other six nonzero states are given by
V sk =
where the values of k vary from 1 to 6.
This divides the plane into six equal regions within a regular hexagon. These voltage vectors are of
equal magnitude and mutually phase-displaced by 60°. Figure 7.40 shows the realizable voltage space
vectors for a three-phase VSI. Whenever the reference vector is in a sector, the switches work according
to the time interval Tm and Tm+1 set by the projection of the vector on the adjacent sides as shown in
Fig. 7.41. The [111] and the [000] states are defined as the zero states and they lie on the origin. Suppose
it is necessary to generate a space-vector modulator for the following voltage system:
V an = V 1 cos ( w m t – g )
V bn = V 1 cos ( w m t + 120 – g )
(7.38)
V cn = V 1 cos ( w m t – 120 – g )
js β
Vs 3
Vs 2
M = 1 . 15
sect 2
M = .5
sect 3
sect 1
Vs1
Vs 4
sect 6
sect 4
sect 5
Vs 5
FIGURE 7.40
Possible space vectors.
© 2002 by CRC Press LLC
Vs 6
sβ
jsβ
V s2
*
Vs
Sector1
Vy
θ
FIGURE 7.41
vector.
Time interval calculation for the space
VX
sα
V s1
The system of voltages can be resolved into two components. These components in the stationary α
and β axes are given as below:
V sa = V 1 sin ( w m t – g )
V sb = −V 1 cos ( w m t – g )
(7.39)
These two voltages can be combined as
V s = – jV 1 e
=
j ( w m t−g )
= V1 e
j ( w t−90 )
2
-- MV dc e m
3
j ( w m t−90 )
(7.40)
assuming g to be zero
where M is the modulation index. The voltage vector refers to a circular trajectory within the hexagon
with an angular frequency of ωm. The maximum voltage that can be achieved is proportional to the
radius of the largest circle inscribed within the hexagon.
Implementation
First the position of the rotating vector is computed by taking the arctangent of the ratio between its two
different quadrature axes components. The switching time interval calculation is the tricky part for this
scheme. If the voltage vector lies in the first sector, the time intervals can be expressed as depicted in
Fig. 7.41.
To synthesize a reference voltage vector V ref to its adjacent states and to obtain a minimum switching
frequency for that the total cycle T cycle should be divided into three segments T m , T m+1 , T 0 . Using simple
geometry in Fig. 7.41 yields
T m + T m+1 + T 0 = T cycle
V ref × T cycle = T m × V sm + T m+1 × V S ( m+1 )
(7.41)
For a voltage vector residing in the first sector the equation can be expressed as
V ref × T cycle = T 1 × V s1 + T 2 × V s2
By taking the components of the reference voltages in the quadrature axis,
T2
- × V s2 sin 60°
V ref sin q = ---------T cycle
© 2002 by CRC Press LLC
(7.42)
or
sin q
T 2 = T cycle × M × ---------------sin 60°
where
V ref
M = ----------V s2
(7.43)
Similarly it can be shown that
sin ( 60° – q )
T 1 = T cycle × M × -----------------------------sin 60°
The rest of the cycle can be divided between and T0 and T8. This can be expressed as
T cycle – T 1 – T 2 = T 0
(7.44)
Switching Signals
As has been mentioned previously, the switching sequence is not unique. Of all these, the most prominent
uses minimum inverter switching frequency, which is obtained by transitioning from one inverter state
to another only by switching one inverter pole. The total zero time is divided between the two zero states.
Figure 7.42 clearly demonstrated the switching in Sector 1. Here, the cycle begins in State 0, i.e., [000],
with each inverter pole being successively toggled until State 8, [111], is obtained. The pattern is then
reversed to complete the modulation cycle. Figure 7.42 shows the times from the start of each modulation
cycle at which the inverter poles are toggled, TAon, TBon, and TCon, respectively. Taking the variations from
one sector to another into consideration, it is possible to tabulate these times as functions of both the
active and zero state times. It can be easily seen that from one state to the other only one inverter pole
is toggled.
The other type of switching is a bus-clamped one. Under this scheme, the switching is done in one
sector using two inverter poles only. One of the poles remains clamped to the higher node. This makes
switching easier. This is also called a 60° bus-clamped scheme because the pole is clamped for 60° (see
Fig. 7.43). Now, one can alternate between [111] and [000] for the zero states in adjacent sectors. It is
termed odd 60° bus-clamped switching if state 8 or [111] is used in odd sectors and vice versa.
For example, in case of a space vector in the first sector, the switching will be done according to the
sequence [111], [110], [100], [110], [111]. So the upper switch of A is clamped to the positive terminal.
The next sector would have a switching pattern that would look like this: [000], [010], [110], [010],
[000]. Here the lower switch of C will be clamped to the negative terminal and all of the inverter legs
will toggle when there is a change in sector. It is worth noting that the even sector only uses the [000] states.
In implementing space-vector modulation on a DSP or microcontroller, one must limit the space
vector voltage. The required voltage can sometimes be over the range of the inverter. This may occur in
cases where one needs to use current regulation from a current controller. There are two ways to limit
the current. One is to limit it by the radius of the circle inscribed within the hexagon and the other one
by limiting the interval time within Tcycle.
© 2002 by CRC Press LLC
Ts
S
∗
SA
∗
SB
000 100 110
111
110 100 000
∗
SC
T0
2
Tm
2
Tm +1
2
T8
Tm +1
2
Tm
2
T0
2
T A on
T Bon
T Con
FIGURE 7.42
Switching signals for the SVPWM.
Ts
S
∗
A
∗
SB
S
∗
C
T8
2
FIGURE 7.43
Tm+1
2
Tm
2
Switching signals for the bus-clamped SVPWM.
© 2002 by CRC Press LLC
Tm+1
2
T8
2
Vsvm,1
Vsvm
DVsvm
2π
3
2π
π
3
wmt
Sector 1 Sector 2 Sector 3 Sector 4 Sector 5 Sector 6
FIGURE 7.44
The modulating function of space-vector modulation with harmonic contents.
The limiting conditions can be given by the following equations:
2
2
( V sa ) + ( V sb ) > V s1
T m + T m+1 < T cycle
(7.45)
(7.46)
As mentioned previously, space-vector modulation provides 15% more bus utilization. The spacevector modulating function can be expressed as a sinusoidal and a triangular distorting waveform with
a frequency three times the fundamental. This results in flattening of the peaks of the modulation signal,
and, hence, a higher maximum voltage is achieved. This is shown in Fig. 7.44.
References
S. Ogasawara, H. Akagi, and A. Nabae, A novel PWM scheme of voltage source inverter based on space
vector theory, European Power Electron. Conf. Rec., Aachen, Germany, 1197–1202, 1989.
A. M. Tryzynadlowski, The Field Orientation Principle in Control of Induction Motors, Kluwer Academic
Publishers, Dordrecht, The Netherlands, 1994.
H. Van Der Broeck, H. Skudelny, and G. Stanke, Analysis and realization of a pulse width modulator
based on voltage space vectors, IEEE-IAS Conf. Rec., 244–251, 1986.
© 2002 by CRC Press LLC