2004-2005 SAIF Project Report
Cascaded Multilevel Inverter
Fault-Tolerance Study
Submitted by
Dr. Xiaomin Kou
Assistant Professor
Electrical Engineering Department
August 26 2005
I. INTRODUCTION
Among the various types of multilevel inverter topologies, the load-terminal side cascaded inverter
(LTCMI) [1-3] has drawn considerable attentions in recent years and has become one of the major
candidates for several industry and military applications. Siemens recently introduced the SIMOVERT
drive which is composed of two cascaded multi-level inverters, the structure of which has been outlined in
[1, 2]. The US Navy has founded some projects on the related topics and treated the LTCMI as one of the
major candidates for the next generation naval propulsion system. The main advantage of the cascaded
multilevel inverter over the standard multi-level inverter is that it offers more voltage vectors per number
of power semiconductor devices that can improve the power quality. The main disadvantage of multilevel
converters is that they require more power semiconductor devices. This feature is significant since the
drive performance increases with the number of voltage vectors while the drive cost, complexity, and
conduction losses climb up with the increasing of power semiconductor numbers. More importantly, the
decreasing stability becomes the major concern for sensitive industry and military applications. Most
studies on multilevel inverters are focused on the topology and control aspects. However, inverter faulttolerance now becomes a very important topic considering reduction of downtime in industrial processes
and survivability of Naval ship propulsion systems. This research intends to look into the fault-tolerant
issue of the LTCMI, and search for some strategies to improve the stabilities.
II. LTCMI TOPOLOGY
Figure 1 shows the LTCMI topology. As can be seen, inverter building blocks can be cascaded to the
two sides of the three-phase load terminals. Consider the cascade-3/3 load side terminated multilevel
inverter, which can be constructed by either two 3-level DCMIs (Diode Clamped Multilevel Inverter) as
shown in Figure 2 or two 3-level FCMIs (Flying Capacitor Multilevel Inverter) as shown in Figure 3. By
varying the level of the two cascaded inverters as well as the dc voltage, an infinite number of voltage
vector diagrams can be obtained. In order to gauges the ability of cascaded multilevel inverter and make it
comparable to the conventional multilevel inverters, the maximal distention case has been discussed in [1,
2], which normally provides nine equivalent converting levels for a cascade-3/3 inverter system. For the
cascade-3/3 inverter system, the over-distention case studied by the principle investigator (PI) of this
proposal in [3] future extended the equivalent converting levels to eleven in spite of some missing space
vectors. If the dc voltage ratio is set to vdc2:vdc1 = 1:3, it can provide nine effective line-to-ground voltage
levels and is maximally distended as an equivalent nine-level conventional inverter. If the dc voltage ratio
is set to vdc2:vdc1 = 1:4, the over-distention operation [3] results in. Figure 4.a and 4.b shows the space
vector plot of the cascade-3/3 inverter under maximal- or over-distention operation.
+
n1-level
multilevel
converter
vdc1
-
ias
ibs
+
vbs
- - vcs
+
vas
+
+
ics
Motor
Load
n2-level
multilevel
converter
vdc2
-
Figure 1. The load terminal cascade
multilevel inverter topology.
+
vc 1
-
+
Tx1
x
Tx3
+
vc 2
-
ic
Tx2
ic
vdc
- -
D1
D2
+
Tx1
+
+
Tx2
vdc
-
vx1
-
Tx2
x
vxg
Tx4
-
+
vxg
Tx1
-
Figure 2. per-phase 3-level diode Figure 3. Per-phase two-cell flying
clamped inverter topology.
capacitor inverter topology.
-vdss
vdss
s
vqs
s
vqs
a) vdc1 : vdc2 = 3 : 1
(maximal distention)
b) vdc1 : vdc2 = 4: 1
(over-distention operation)
Figure 4. Voltage vector plot for the cascade-3/3 inverter
vdss
vdss
s
vqs
a) vdc1 : vdc2 = 3 : 1
s
vqs
b) vdc1 : vdc2 = 4 : 1
(maximal distention)
Figure 5. Cascade-3/2 inverter space vector plot
When a single-switch-fault occurs in the cascade-3/3 inverter, the converter containing the fault switch
may be reduced to a 2-level inverter through the controls, and the inverter system can then be reduced to a
cascade-3/2 inverter, which may generate six fictitious line-to-ground voltage levels under maximal
distention operation. However, The maximal distention operation of the cascade-3/2 inverter requires the
dc voltage ratio to be vdc2:vdc1 = 1:4, which is not equal to the 1:3 ratio of the original 9-level maximally
distended cascade-3/3 inverter case. Under the circumstance that the dc voltage sources are nonadjustable,
when single-switch-fault happens, the cascade-3/3 inverter will be reduced to a cascade-3/2 inverter with
a fixed 1:3 dc ratio. The related voltage space vector plot is shown in Figure 5.a. It can be seen that this
space vector distribution is not a desired case and has tremendous uneven distributed derivations. Figure
5.b. is the desired space vector plot of the maximally distended cascade-3/2 inverter. Therefore, when
single-switch-fault occurs in the cascade-3/3 inverter, in order to have the converter working as a desired
cascade-3/2 converter, new solutions needs to be discovered.
III. NEW DISCOVERY
It has been discussed that the over-distension operation of the cascade-3/3 inverter actually requires a
1:4 dc voltage ratio, which is the same ratio as the maximal distended cascade-3/2 inverter. Therefore, a
proposed LTMI fault-tolerance design can be set to work under the over-distension mode when it is faultfree, which may provide eleven fictitious line-to-ground voltage levels. Although there are several
missing space vectors around the outer loop, the control technique introduced in [3] can configure the
inverter to work as an equivalent eleven-level inverter. When the modulation index is higher than 91.7%
of the physical modulation limitations, the control can bypass the missing vectors with no redundant
states. This will slightly degrade the performance compared to conventional eleven-level inverter. When
the modulation index is lower than 91.7%, the control can configure the inverter to utilize the redundant
space vector of the missing switching levels. Although the line-to-ground voltages still contain missing
levels, the phase voltages obtain a performance as good as the conventional eleven-level inverter. In
addition, the modulation technique can also be used to balance the capacitor voltages. When singleswitch-fault happens, the cascade-3/3 LTMI will be reduced to a cascade-3/2 or -2/3 inverter, which may
provide six fictitious voltage-converting levels. If the fault situation is very serious on one of the
inverters, it can be reconfigured or completely taken out from the system so that the neutral point of the
fault side can be shorted, then the inverter system can be converted back to a conventional 3-level
inverter. Due to the fact that DCMI has less switching state redundancies compared to FCMI, the faulttolerance operation mentioned above is easy to implement on a cascade-3/3 FCMI inverter.
III. SIMULATION
Due to the lack of advanced simulation software, the PI wasn’t able to perform a very decent simulation
study on this project. The PI planed to use the Matlab/Simulink software (Purchased by the department)
plus the SimPower block to perform the study but later found out they are only licensed for teaching
related classroom use and with limited functionalities, which greatly limited the full-scale simulation
studies. A full-version simulation package can easily cost up to tens of thousand dollars, which is
impossible to be covered by the limited budget. However, the PI did spend time to evaluate the simulation
software package. It has been found that the current version of SimPower blocks built on top of the
Simulink is not yet suitable for advanced simulation study of multilevel power converters. The main
difficulty lies in the physical modeling method of the switching devices adopted by the system. Current
sources are used to model the switching devices. It is very hard to put several switches in series using
their models. The series connections of multiple switches are the fundamental requirement of the
multilevel inverters. Special treatment may be added to the test system, but it will greatly increase the
number of the dynamic states which makes the simulation extremely slow. One phase of a simple threelevel flying capacitor inverter was created but it took several hours to finish a straight forward simulation
period of just several seconds. A cascaded 3/3 inverter will have totally 6 such phase legs and a lot more
complex gate controls, which makes the use of SimPower impractical. It is still possible to use the
original coding techniques of Matlab with the help of Simulink to perform the type of simulation studies
as multilevel inverter fault-tolerance, but this is a long and low efficient approach. The PI will keep
digging into this once suitable version of software become available.
IV. HARDWARE AND STUDENT INVOLVEMENT
With the limited budget, the PI has mainly focused his hardware study on the gate driver part of the
inverters. Some students who enrolled in the Power Electronics class (2004 Fall semester) have involved
in the process. Gate drivers for the single switch, 2-level switching pairs, H-bridge as well as multilevel
inverters have been studied through student projects and/or independent studies [5]. The PI has put
considerable amount of the time to guide and supervise the students’ study and research on the related
topics and have reached some very good results. The PI has created a presentation which includes more
information on the research project. The PI plans to share the presentation with the colleagues in the
coming UWP research poster days. You may find the presentation from the attachment.
V. SUMMARY
A research on the fault-tolerant issue of the cascaded multilevel inverters has been performed. A new
idea has been presented which can have a better power quality control when single switch fault presents.
Full scale computer simulation wasn’t done due to the software availability. However, the targeted
simulation package has been evaluated and it can be concluded that the current version of the software
package itself is not a good candidate for the related researches. Gate drivers related hardware tests have
been performed with the great involvement of EE students.
Reference:
1. K.A. Corzine, S.D. Sudhoff, and C.A. Whitcomb, "Performance Characteristics of a Cascaded Two-Level
Converter", IEEE Transactions on Energy Conversion, volume 14, number 3, pages 433-439, September 1999.
2. K.A. Corzine and S.D. Sudhoff, "High State Count Power Converters: an Alternate Direction in Power
Electronics Technology," SAE Transactions, Journal of Aerospace, Section 1, pages 124-135, 1998.
3. X. Kou, K.A. Corzine and M. Wielebski, “The Over-Distension Operation of the Cascaded multilevel inverter”,
accepted by the IEEE International Electric Machines and Drives Conference, Madison, 2003.
4. X. Kou, K.A. Corzine, Y. Familant, “A Unique Fault-Tolerant Design for Flying Capacitor Multilevel Inverters”,
Conference Proceedings of the IEEE International Electric Machines and Drives Conference, Pages 531-538,
Madison, June 2003.
5. Project reports submitted by EE students enrolled in the EE4430 Power Electronics class.
Attachment: Research Presentation