Data Conversion Handbook
I ANALOG
I DEVICES
Walt Kester, Editor
with the technical staff of Analog Devices
A Volume in the Analog Devices Series
ELSEVIER
AMSTERDAM • BOSTON • HEIDELBERG • LONDON
NEW YORK • OXFORD • PARIS • SAN DIEGO
SAN FRANCISCO • SINGAPORE • SYDNEY • TOKYO
Newnes is an imprint of Elsevier
Contents
Foreword
xvii
Preface
xix
Acknowledgments
xxi
Chapter 1: Data Converter History
3
Section 1-1: Early History
The Early Years: Telegraph to Telephone
The Invention of PCM
The Mathematical Foundations of PCM
The PCM Patents of Alec Harley Reeves
PCM and the Bell System; World War II through 1948
Op Amps and Regenerative Repeaters: Vacuum Tubes to Solid-State
Section 1-2: Data Converters of the 1950s and 1960s
Commercial Data Converters: 1950s
Commercial Data Converter History: 1960s
Data Converter Architectures
Section 1-3: Data Converters of the 1970s
Monolithic Data Converters of the 1970s
Bipolar Process IC DACs of the 1970s
CMOS IC DACs of the 1970s
Monolithic ADCs of the 1970s
Hybrid Data Converters of the 1970s
Modular Data Converters of the 1970s
Section 1-4: Data Converters of the 1980s
Monolithic DACs of the 1980s
Monolithic ADCs of the 1980s
Monolithic Flash ADCs of the 1980s
Hybrid and Modular DACs and ADCs of the 1980s
Section 1-5: Data Converters of the 1990s
Monolithic DACs of the 1990s
Monolithic ADCs of the 1990s
Hybrid and Modular DACs and ADCs of the 1990s
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52
Section 1-6: Data Converters of the 2000s
Chapter 2: Fundamentals of Sampled Data Systems
Section 2-1: Coding and Quantizing
Unipolar Codes
Gray Code
Bipolar Codes
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57
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62
Contents
Complementary Codes
DAC and ADC Static Transfer Functions and DC Errors
Section 2-2: Sampling Theory
The Need for a Sample-and-Hold Amplifier (SHA) Function
The Nyquist Criteria
:
Baseband Antialiasing Filters
Undersampling (Harmonic Sampling, Bandpass Sampling, IF Sampling,
Direct IF-to-Digital Conversion)
Antialiasing Filters in Undersampling Applications
Section 2-3: Data Converter AC Errors
Theoretical Quantization Noise of an Ideal N-Bit Converter
Noise in Practical ADCs
Equivalent Input Referred Noise
Noise-Free (Flicker-Free) Code Resolution
Dynamic Performance of Data Converters
Integral and Differential Nonlinearity Distortion Effects
Harmonic Distortion, Worst Harmonic, Total Harmonic Distortion (THD),
Total Harmonic Distortion Plus Noise (THD + N)
Signal-to-Noise-and-Distortion Ratio (SINAD), Signal-to-Noise Ratio (SNR),
and Effective Number of Bits (ENOB)
Analog Bandwidth
Spurious Free Dynamic Range (SFDR)
Two-Tone Intermodulation Distortion (IMD)
Second- and Third-Order Intercept Points, 1 dB Compression Point
Multitone Spurious Free Dynamic Range
Wideband CDMA (WCDMA) Adjacent Channel Power Ratio (ACPR) and Adjacent
Channel Leakage Ratio (ADLR)
Noise Power Ratio (NPR)
Noise Factor (F) and Noise Figure (NF)
Aperture Time, Aperture Delay Time, and Aperture Jitter
A Simple Equation for the Total SNR of an ADC
ADC Transient Response and Overvoltage Recovery
ADC Sparkle Codes, Metastable States, and Bit Error Rate (BER)
DAC Dynamic Performance
DAC Settling Time
Glitch Impulse Area
DAC SFDR and SNR
Measuring DAC SNR with an Analog Spectrum Analyzer
DAC Output Spectrum and sin (x)/x Frequency Roll-off
Oversampling Interpolating DACs
Section 2-4: General Data Converter Specifications
Overall Considerations
Logic Interface Issues
•.
Data Converter Logic: Timing and other Issues
Section 2-5: Defining the Specifications
65
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Contents
Chapter 3: Data Converter Architectures
147
Section 3-1: DAC Architectures
147
DAC Output Considerations
Basic DAC Structures
The Kelvin Divider (String DAC)
Thermometer (Fully-Decoded) DACs
Binary-Weighted DACs
R-2RDACs
Segmented DACs
Oversampling Interpolating DACs
Multiplying DACs
Intentionally Nonlinear DACs
Counting, Pulsewidth-Modulated (PWM) DACs
Cyclic Serial DACs
Other Low Distortion Architectures
DAC Logic Considerations
148
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170
.-.-
Section 3-2: ADC Architectures
175
The Comparator: A 1-Bit ADC
High Speed ADC Architectures
Flash Converters
Successive Approximation ADCs
Subranging, Error Corrected, and Pipelined ADCs
Serial Bit-Per-Stage Binary and Gray Coded (Folding) ADCs
Counting and Integrating ADC Architectures
A. H. Reeves'5-Bit Counting ADC
Charge Run-Down ADC
Ramp Run-Up ADC
Tracking ADC
Voltage-to-Frequency Converters (VFCs)
Dual Slope/Multislope ADCs
Optical Converters
Resolver-to-Digital Converters (RDCs) and Synchros
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Section 3-3: Sigma-Delta Converters
231
Historical Perspective
Sigma-Delta (E-A) or Delta-Sigma (A-Z)?
Basics of Sigma-Delta ADCs
Idle Tone Considerations
Higher Order Loop Considerations
Multibit Sigma-Delta Converters
Digital Filter Implications
Multistage Noise Shaping (MASH) Sigma-Delta Converters
High Resolution Measurement Sigma-Delta ADCs
Sigma-Delta DACs
Chapter 4: Data Converter Process Technology
'.
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240
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242
243
244
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249
257
Section 4-1: Early Processes
257
Vacuum Tube Data Converters
257
vii
Contents
Solid State, Modular, and Hybrid Data Converters
Calibration Processes
Section 4-2: Modern Processes
Bipolar Processes
Thin Film Resistor Processes
Complementary Bipolar (CB) Processes
CMOS Processes
!
Data Converter Processes and Architectures
Section 4-3: Smart Partitioning
When Complete Integration Isn't the Optimal Solution
Why Smart Partitioning is Necessary
What's Changing?
Chapter 5: Testing Data Converters
Section 5-1: Testing DACs
Static DAC Testing
End-Point Errors
Linearity Errors
Superposition and DAC Errors
Measuring DAC DNL and INL Using Superposition
Measuring DAC INL and DNL Where Superposition Does Not Hold
Testing DACs for Dynamic Performance
Settling Time
Glitch Impulse Area
Oscilloscope Measurement of Settling Time and Glitch Impulse Area
Distortion Measurements
Section 5-2: Testing ADCs
A Brief Historical Overview of Data Converter Specifications and Testing
Static ADC Testing
Back-to-Back Static ADC Testing
Crossplot Measurements of ADC Linearity
Servo-Loop Code Transition Test
Computer-Based Servo-Loop ADC Tester
Histogram (Code Density) Test with Linear Ramp Input
Dynamic ADC Testing
Manual "Back-to-Back" Dynamic ADC Testing
Measuring Effective Number of Bits (ENOB) Using Sinewave Curve Fitting
FFT Basics
FFT Test Setup Configuration and Measurements
Verifying the FFT Accuracy
Generating Low Distortion Sinewave Inputs
„
Noise Power Ratio (NPR) Testing
Measuring ADC Aperture Jitter Using the Locked-Histogram Test Method
Measuring Aperture Delay Time
Measuring ADC Aperture Jitter Using FFTs
Measuring ADC Analog Bandwidth Using FFTs
Settling Time ,.
via
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343
Contents
Overvoltage Recovery Time
Video Testing, Differential Gain and Differential Phase
Bit Error Rate (BER) Tests
Chapter 6: Interfacing to Data Converters
Section 6-1: Driving ADC Analog Inputs
AmpliferDC and AC Performance Considerations
Rail-Rail Input Stages
Output Stages
Gain and Level-Shifting Circuits Using Op Amps
Op Amp AC Specifications and Data Converter Requirements
Driving High Resolution Z-A Measurement ADCs
Driving Single-Ended Input Single-Supply 1.6 V to 3.6 V Successive Approximation ADCs
Driving Single-Supply ADCs with Scaled Inputs
Driving Differential Input CMOS Switched Capacitor ADCs
Single-Ended Drive Circuits for Differential Input CMOS ADCs
Differential Input ADC Drivers
Driving ADCs with Differential Amplifiers
Dual Op Amp Drivers
Fully Integrated Differential Amplifier Drivers
Driving Differential Input ADCs with Integrated Differential Drivers
Section 6-2: ADC and DAC Digital lnterfaces(and Related Issues)
Power-On Initialization of Data Converters
Initialization of Data Converter Internal Control Registers
Low Power, Sleep, and Standby Modes
Single-Shot Mode, Burst Mode, and Minimum Sampling Frequency
ADC Digital Output Interfaces
ADC Serial Output Interfaces
ADC Serial Interface to DSPs
ADC Parallel Output Interfaces
DAC Digital Input Interfaces
DAC Serial Input Interfaces to DSPs
DAC Parallel Input Interfaces to DSPs
Section 6-3: Buffering DAC Analog Outputs
Differential to Single-Ended Conversion Techniques
Single-Ended Current-to-Voltage Conversion
Differential Current-to-Differential Voltage Conversion
An Active Low-Pass Filter for Audio DAC
Section 6-4: Data Converter Voltage References
Section 6-5: Sampling Clock Generation
Oscillator Phase Noise and Jitter
"Hybrid" Clock Generators
Driving Differential Sampling Clock Inputs
Sampling Clock Summary
Chapter 7: Data Converter Support Circuits
Section 7-1: Voltage References
Precision Voltage References
ix
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348
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443
Contents
Types of Voltage References
Bandgap References
Buried Zener References
XFET References
Voltage Reference Specifications
Tolerance
Drift....;
Supply Range
Load Sensitivity
Line Sensitivity
Noise
Scaled References
Voltage Reference Pulse Current Response
Low Noise References for High Resolution Converters
Section 7-2: Low Dropout Linear Regulators
Linear Voltage Regulator Basics
Pass Devices and their Associated Trade Offs
Low Dropout Regulator Architectures
The anyCAP Low Dropout Regulator Family
Design Features Related to DC Performance
Design Features Related to AC Performance
A Basic Pole-Splitting Topology
The anyCAP Pole-Splitting Topology
The anyCAP LDO series devices
Functional Diagram and Basic 50 mA LDO Regulator
LDO Regulator Thermal Considerations
LDO Regulator Controllers
Regulator Controller Differences
A Basic 5 V/l A LDO Regulator Controller
Selecting the Pass Device
Thermal Design
Sensing Resistors for LDO Controllers
PCB Layout Issues
A 2.8 V/8 A LDO Regulator Controller
Section 7-3: Analog Switches and Multiplexers
CMOS Switch Basics
Error Sources in the CMOS Switch
Applying the Analog Switch
1 GHz CMOS Switches
Video Switches and Multiplexers
Video Crosspoint Switches
Digital Crosspoint Switches
Switch and Multiplexer Families from Analog Devices
Parasitic Latchup in CMOS Switches and Muxes
Section 7-4: Sample-and-Hold Circuits
Introduction and Historical Perspective
444
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..477
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..508
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519
519
Contents
Basic SHA Operation
Track Mode Specifications
Track-to-Hold Mode Specifications
Hold Mode Specifications
Hold-to-Track Transition Specifications
SHA Architectures
Internal SHA Circuits for IC ADCs
SHA Applications
521
522
522
526
528
529
531
533
Chapter 8: Data Converter Applications
539
Section 8-1: Precision Measurement and Sensor Conditioning
Applications of Precision Measurement £-A ADCs
Weigh Scale Design Analysis Using the AD7730 ADC
Thermocouple Conditioning Using the AD7793
Direct Digital Temperature Measurements
Microprocessor Substrate Temperature Sensors
Applications of ADCs in Power Meters
539
540
544
549
551
555
558
Section 8-2: Multichannel Data Acquisition Systems
563
Data Acquisition System Configurations
Multiplexing
Filtering Considerations in Data Acquisition Systems
Complete Data Acquisition Systems on a Chip
Multiplexing Inputs to E-A ADCs
Simultaneous Sampling Systems
Data Distribution Systems
Data Distribution Using an Infinite Sample-and-Hold
Section 8-3: Digital Potentiometers
Modern Digital Potentiometers in Tiny Packages
Digital Potentiometers with Nonvolatile Memory
One-Time Programmable (OTP) Digital Potentiometers
Digital Potentiometer AC Considerations
Application Examples
563
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567
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570
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578
581
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584
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587
Section 8-4: Digital Audio
597
Sampling Rate and THD + N Requirements for Digital Audio
Overall Trends in Digital Audio ADCs and DACs
Voiceband Codecs
High Performance Audio ADCs and DACs in Separate Packages
High Performance Multichannel Audio Codecs and DACs
Sample Rate Converters
Section 8-5: Digital Video and Display Electronics
Digital Video
Digital Video Formats
Serial Data Interfaces
Digital Video ADCs and DACs: Decoders, and Encoders
Specifications for Video Decoders and Encoders
Display Electronics
Flat Panel Display Electronics
xi
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596
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600
602
607
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608
612
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614
615
619
Contents
CCD Imaging Electronics
Touchscreen Digitizers
622
627
Section 8-6: Software Radio and IF Sampling
633
Evolution of Software Radio
A Receiver Using Digital Processing at Baseband
Narrowband IF-Sampling Digital Receivers
Wideband IF-Sampling Digital Receivers
Increasing ADC Dynamic Range Using Dither
Wideband Radio Transmitter Considerations
Cellular Telephone Handsets
The Role of ADCs and DACs in Cellular Telephone Handsets
SoftFone® and Othello Radio Chipsets from Analog Devices
Time-Interleaved IF Sampling ADCs with Digital Post-Processors
Advanced Digital Post Processing
Advanced Filter Bank (AFB)
AFB Design Example: The AD12400 12-Bit, 400 MSPS ADC
Section 8-7: Direct Digital Synthesis (DDS)
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635
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639
649
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661
662
667
671
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673
677
Introduction to DDS
Aliasing in DDS Systems
Frequency Planning in DDS Systems
Modern Integrated DDS Systems
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681
682
684
Section 8-8: Precision Analog Microcontrollers
Characteristics of the MicroConverter Product Family
Some E-A MicroConverter Applications
ADuC7xxx MicroConverter Products Based on the ARM7 Processor Core
Chapter 9: Hardware Design Techniques
693
694
700
702
709
Section 9-1: Passive Components
Capacitors
Dielectric Absorption
Capacitor Parasitics and Dissipation Factor
Tolerance, Temperature, and Other Effects
Assemble Critical Components Last
Resistors and Potentiometers
Resistor Parasitics
Thermoelectric Effects
Voltage Sensitivity, Failure Mechanisms, and Aging
Resistor Excess Noise
Potentiometers
Inductance
Stray Inductance
Mutual Inductance
Ringing
Parasitic Effects in Inductors
Q or "Quality Factor"
Don't Overlook Anything
XII
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Contents
Section 9-2: PC Board Design Issues
..;
733
Resistance of Conductors
733
Voltage Drop in Signal Leads—"Kelvin" Feedback
735
Signal Return Currents
,
736
Grounding in Mixed Analog/Digital Systems
737
Ground and Power Planes
738
Double-Sided versus Multilayer Printed Circuit Boards
739
Multicard Mixed-Signal Systems
740
Separating Analog and Digital Grounds
740
Grounding and Decoupling Mixed-Signal ICs with Low Digital Currents
742
Treat the ADC Digital Outputs with Care
...........743
Sampling Clock Considerations
:....
.,.;.. 744
The Origins of the Confusion about Mixed-Signal Grounding: Applying SinglerCard
Grounding Concepts to Multicard Systems
'.
746
Summary: Grounding Mixed-Signal Devices with Low Digital Currents in a
Multicard System
747
Summary: Grounding Mixed-Signal Devices with High Digital Currents in a
Multicard System
748
Grounding DSPs with Internal Phase-Locked Loops
748
Grounding Summary
749
Some General PC Board Layout Guidelines for Mixed-Signal Systems
750
Skin Effect
751
Transmission Lines
753
Be Careful With Ground Plane Breaks
753
Ground Isolation Techniques
754
Static PCB Effects
756
Sample MINIDIP and SOIC Op Amp PCB Guard Layouts
758
Dynamic PCB Effects
760
Stray Capacitance
761
Capacitive Noise and Faraday Shields
762
The Floating Shield Problem
762
Buffering ADCs Against Logic Noise
763
Section 9-3: Analog Power Supply Systems
767
Linear IC Regulation
768
Some Linear Voltage Regulator Basics
768
Pass Devices
770
±15 V Regulator Using Adjustable Voltage ICs
770
Low Dropout Regulator Architectures
771
Fixed-Voltage, 50/100/200/500/1000/1500 mA LDO Regulators
772
Adjustable Voltage, 200 mA LDO Regulator
774
Charge-Pump Voltage Converters
775
Regulated Output Charge-Pump Voltage Converters
776
Linear Post Regulator for Switching Supplies
778
Grounding Linear and Switching Regulators
779
Power Supply Noise Reduction and Filtering
782
Capacitors
782
Contents
Ferrites
Card Entry Filter
Rail Bypass/Distribution Filter
Local High Frequency Bypass/Decoupling
Section 9-4: Overvoltage Protection
In-Circuit Overvoltage Protection
General Input Common Mode Limitations
Clamping Diode Leakage
A Flexible Voltage Follower Protection Circuit
Common-Mode Overvoltage Protection Using CMOS Channel Protectors
CM Overvoltage Protection Using High CM Voltage In Amp
Inverting Mode Op Amp Protection Schemes
Amplifier Output Voltage Phase-Reversal
An Output Phase-Reversal Do-it-Yourself Test
Fixes for Output Phase-Reversal
Input Differential Protection
Protecting In Amps Against Overvoltage
Overvoltage Protection Using CMOS Channel Protectors
Digital Isolators
Out-of-Circuit Overvoltage Protection
ESD Models and Testing
Section 9-5: Thermal Management
Thermal Basics
Heat Sinking
Data Converter Thermal Considerations
Section 9-6: EMI/RFI Considerations
EMI/RFI Mechanisms
EMI Noise Sources
EMI Coupling Paths
Noise Coupling Mechanisms
Reducing Common-Impedance Noise
Noise Induced by Near-Field Interference
Reducing Capacitance-Coupled Noise
Reducing Magnetically-Coupled Noise
Passive Components: Your Arsenal Against EMI
Reducing System Susceptibility to EMI
A Review of Shielding Concepts
General Points on Cables and Shields
Input-Stage RFI Rectification Sensitivity
Background: Op Amp and In Amp RFI Rectification Sensitivity Tests
An Analytical Approach: BJT RFI Rectification
An Analytical Approach: FET RFI Rectification
Reducing RFI Rectification Within Op amp and In Amp Circuits
Op Amp Inputs
In Amp Inputs
Amplifier Outputs and EMI/RFI
xiv
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789
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793
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823
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836
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837
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839
839
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846
846
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848
849
849
850
852
Contents
Printed Circuit Board Design for EMI/RFI Protection
Choose Logic Devices Carefully
Design PCBs Thoughtfully
Designing Controlled Impedances Traces on PCBs
Microstrip PCB Transmission Lines
Some Microstrip Guidelines
Symmetric Stripline PCB Transmission Lines
Some Pros and Cons of Embedding Traces
Dealing with High-Speed Logic
Section 9-7: Low Voltage Logic Interfacing
852
853
853
854
855
855
856
857
858
867
Voltage Tolerance and Voltage Compliance
Interfacing 5 V Systems to 3.3 V Systems using NMOS FET "Bus Switches"
3.3 V/2.5 V Interfaces
3.3 V/2.5 V, 3.3 V/1.8 V, 2.5 V/1.8 V Interfaces
Hot Swap and Hot Plug Applications of Bus Switches
Internally Created Voltage Tolerance / Compliance
Section 9-8: Breadboarding and Prototyping
870
871
873
874
878
879
881
"Deadbug" Prototyping
Solder-Mount Prototyping
Milled PCB Prototyping
Beware of Sockets
Some Additional Prototyping Points
Evaluation Boards
General-Purpose Op Amp Evaluation Board from the Mid-1990s
Dedicated Op Amp Evaluation Boards
Data Converter Evaluation Boards
Index
xv
882
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885
886
887
887
888
888
890
895