Common Combinational Logic Circuits
• Adders
– Subtraction typically via 2s complement addition
• Multiplexers
– N control signals select 1 of up to 2N inputs as output
• Demultiplexers
– N control signals select input to go to 1 of up to 2N outputs
• Decoders
– N inputs produce M outputs (typically M > N)
• Encoders
– N inputs produce M outputs (typically N > M)
• Converter (same as decoder or encoder)
– N inputs produce M outputs (typically N = M)
C. E. Stroud
Combinational Logic Circuits (10/12)
1
More Common Circuits
• Comparators
– Compare two N-bit binary values
• Equal-to or Not-equal-to
– Easiest to design
• Greater-than, Less-than, Greater-than-or-equal-to, etc.
– Require adders
• Parity check/generate circuit
– Calculates even or odd parity over N bits of data
– Checks for good/bad parity (parity errors) on
incoming data
C. E. Stroud
Combinational Logic Circuits (10/12)
2
Adders
• Consider ith column
addition of 2 binary
numbers (A and B)
– Ai + Bi + Cini = Couti
+ Sumi
– Derive truth table
– Populate K-maps
– Obtain minimized
SOPs
– Draw logic diagram
– Optimize with P&Ts
C. E. Stroud
Truth Table
A B C Co S
0 0 0
0
0
0 0 1
0
1
0 1 0
0
1
0 1 1
1
0
1 0 0
0
1
1 0 1
1
0
1 1 0
1
0
1 1 1
1
1
Combinational Logic Circuits (10/12)
BC
A 00 01 11 10
0 0 1 0 1
1 1 0 1 0
S=A’B’C+A’BC’
+AB’C’+ABC
=A’(BC)+A(BC)
=ABC
BC
A 00 01 11 10
0 0 0 1 0
1 0 1 1 1
Co=BC+AC+AB
3
Adders
A
B
C
BC
A 00 01 11 10
0 0 0 1 0
1 0 1 1 1
S=ABC
Co=BC+
AC+AB
Taking advantage of common
product terms between S and Co
we see that we can use the XOR
gate for AB to reduce the gate
count
C. E. Stroud
Co=A’BC+AB’C+AB
=C(A’B+AB’)+AB
=C(AB)+AB
A
B
C
Combinational Logic Circuits (10/12)
S=ABC
Co=BC+
AC+AB
4
Adders
referred to as a full adder
A
B
C
S=ABC
Co=BC+
AC+AB
we can let a block
represent the full adder
now we can build an N-bit
adder from N full adders
Cin
A0
B0
A1
B1
A
B
C
A
B
C
S
FA
S0
Co
S
S1
FA
Co
A
B
Cin
C. E. Stroud
full S
adder
AN-1
BN-1
Cout
Combinational Logic Circuits (10/12)
A
B
C
S
FA
Co
SN-1
Cout
5
Subtractors
Build an N-bit subtractor from an
N-bit adder using 2’s complement
•Recall the 2’s complement
transformation for a
negative number:
1) invert
2) then add 1
here we use Cin
to add a 1
•Therefore, S=A-B
•Note that this includes
a sign bit (SN-1)
C. E. Stroud
Cin=1
A0
B0
A1
B1
AN-1
BN-1
Combinational Logic Circuits (10/12)
A
B
C
A
B
C
A
B
C
S
FA
S0
Co
S
S1
FA
Co
S
FA
Co
SN-1
Cout
6
Multiplexers
• N control signals select 1 of up to 2N inputs
as output
– Sometimes called selectors
– We looked at a 2-to-1 MUX
A
A
Z
S
B
G=4
GIO=11
Gdel=3
C. E. Stroud
B
0
1
Z = AS’ + BS
S
if S=0, then Z=A
else if S=1, then Z=B
Combinational Logic Circuits (10/12)
In0
Out
Z
In2N-1
N
Select
Control
7
Short-hand Truth Table
Multiplexers
• 4-to-1 MUX
– 4 inputs
• In0-3
– 2 controls
• S1, S0 (LSB)
– 1 output
• Z
In0
In1
In2
In3
0
1
2
3
In0
S1
S0
S1 S0
• Can generated any size MUX
Z = In0 S1’ S0’ + In1 S1’ S0
+ In2 S1 S0’ + In3 S1 S0 S0
SOP obtained directly from S1
short-hand Truth Table
C. E. Stroud
Z
S1 S0 Z
0 0 In0
0 1 In1
1 0 In2
1 1 In3
In1
S1
S0
In2
S1
S0 S0
S1
In3
S1
S0
Combinational Logic Circuits (10/12)
Z
G=7
GIO=25
Gdel=3
8
Multiplexers
In0
In1
In2
In3
0
Z
1
2
3
• 4-to-1 MUX
S1 S0
– Built from 2-to-1 MUXs
• Can generate any size MUX
Z =X S1’ + Y S1
=(In0 S0’+In1 S0)S1’
+(In2 S0’+In3 S0)S1
=In0 S1’ S0’ + In1 S1’ S0
+ In2 S1 S0’ + In3 S1 S0
In0
A
In1
Z
B S
In2
A
In3
Z
B S
Combinational Logic Circuits (10/12)
A
Z
B S
S0
C. E. Stroud
X
G=12
GIO=33
Gdel=5
S0-S0’-Z
Z
Y
S1
9
Multiplexers
• Recall Shannon’s Expansion Theorem
– T10a: f(X1,X2,…,Xn-1,Xn)=
(X1’•f(0,X2,…,Xn-1,Xn))+(X1•f(1,X2,…,Xn-1,Xn))
– A 2-to-1 MUX is X1 as select input
• Can be taken further:
– f(X1,X2,…,Xn-1,Xn)= (X1’•X2’•f(0,0,…,Xn-1,Xn))
+ (X1•X2’•f(1,0,…,Xn-1,Xn)) + (X1’•X2•f(0,1,…,Xn-1,Xn))
+(X1•X2•f(1,1,…,Xn-1,Xn))
– A 4-to-1 MUX with X1X2 and X1 as select inputs
• This says a MUX is functionally complete
C. E. Stroud
Combinational Logic Circuits (10/12)
10
Multiplexers Are Functionally
Complete
0
0
• AND operation
– f(A,B) = AB = A’f(0,B) + Af(1,B)
= A’(0B) + A(1B) = A’0 + AB
• OR operation
B
B
1
– f(A) = A’ = A’f(0) + Af(1) 0
= A’(1) + A(0)
C. E. Stroud
Combinational Logic Circuits (10/12)
0
1
A
– f(A,B) = A+B = A’f(0,B) + Af(1,B) 1
= A’(0+B) + A(1+B) = A’B + A1
• NOT operation
AB
0
A+B
1
A
A
1
A
11
Demultiplexers
• N control signals select input
to go to 1 of up to 2N outputs
• Opposite of MUXs
Out0
In
– Sometimes called de-selectors
• Alternate view is a decoder
Out2N-1
N
Select
Control
– N inputs produce a logic 1 on
1 of up to 2N outputs
• An enable input can be added to Select
Control N
“enable” the logic 1 on the
output
Out0
Out2N-1
– Otherwise all outputs are 0
• Now it’s same as the DMUX
C. E. Stroud
Combinational Logic Circuits (10/12)
Enable
12
Demultiplexers/Decoders
S1 S0 O0 O1 O2 O3
• Truth table, logic
equations & design
of 2-to-4
O0=InS1’S0’
demultiplexer
O1=InS1’S0
• Same as 2-bit
O2=InS1S0’
address decoder O3=InS1S0
with active high
S0
G=6
enable (En)
– En same as In in
demux design
C. E. Stroud
GIO=20
Gdel=2
S1
0
0
In
0
0
0
0 1
0
In 0 0
1 0
0
0
In 0
1 1
0
0
0
In
(En) S1’
S0’
S0’
S1’
Combinational Logic Circuits (10/12)
S1’
S0
S1
S0’
S1
S0
In
O0
O1
O2
O3
13
Decoders/Encoders
• Decoders
– N inputs produce M outputs (typically M > N)
– BCD to 7-segment decoder is a good example
• Encoders
– N inputs produce M outputs (typically N > M)
– We could just as easily have taken the 7-segment values
(A-G) and encode to BCD or HEX
• That would be a 7-variable K-map
• Converters
– N inputs produce M outputs (typically N = M)
– Excess-3 code to BCD converter is a good example
C. E. Stroud
Combinational Logic Circuits (10/12)
14
Comparators
G=N+1
GIO=3N+N+1
Gdel=2
• Equal-to comparators use XOR A0
function
B0
NEQ
– XOR produces 1 when inputs
differ
AN-1
• Do bit-wise compare of N pairs of B
N-1
bits
– N XOR gates
A0-AN-1
B0-BN-1
N
– OR the XOR outputs to produce a
1 when the input values differ
• An N-input OR gate
• Invert the output (NOR) to produce a
1 when the input values are the same
• Greater/Less-than use 2s-comp
subtraction
C. E. Stroud
Combinational Logic Circuits (10/12)
1
A
Cin
B
Adder
Sum
Cout
N
A=B
AB
15
Parity Circuits
• Parity makes use of the XOR function
– XOR produces a 1 for an odd # of 1s on input
• This produces even parity over data + parity bit
• For odd parity, we can invert the output (an XNOR)
– Check for correct parity by comparing Pgen with incoming
G=3
parity bit Pin
GIO=9
Gdel=2
• Another XOR gate for comparison
•
D0
For N data bits
D1
– Generate circuit = N-1 XOR gates D2
• With parity control = N XOR gates
D3
– Check circuit = N XOR gates
• With parity control = N+1 XOR gates
• Parity control allows inversion for
even or odd parity generation and
requires additional XOR gate
C. E. Stroud
Combinational Logic Circuits (10/12)
Pin
G=4
GIO=12
Gdel=3
Pgen
Perror
16