Vol. 33, No. 4
Journal of Semiconductors
April 2012
An analytical model for the drain–source breakdown voltage of RF LDMOS power
transistors with a Faraday shield
Zhang Wenmin(张文敏)1; Ž , Zhang Wei(张为)1 , Fu Jun(付军)2 , and Wang Yudong(王玉东)2
1 School
of Electronic Information Engineering, Tianjin University, Tianjin 300072, China
of Microelectronics, Tsinghua University, Beijing 100084, China
2 Institute
Abstract: An analytical model for the drain–source breakdown voltage of an RF LDMOS power transistor with
a Faraday shield is derived on the basis of the solution of the 2D Poisson equation in a p-type epitaxial layer, as
well as an n-type drift region by means of parabolic approximation of electrostatic potential. The model captures
the influence of the p-type epitaxial layer doping concentration on the breakdown voltage, compared with the
previously reported model, as well as the effect of the other device parameters. The analytical model is validated
by comparing with a numerical device simulation and the measured characteristics of LDMOS transistors. Based on
the model, optimization of LDMOS device parameters to achieve proper trade-off between the breakdown voltage
and other characteristic parameters such as on-resistance and feedback capacitance is analyzed.
Key words: RF LDMOSFET; Faraday shield; breakdown voltage; surface electrical field; drift region
DOI: 10.1088/1674-4926/33/4/044001
EEACC: 2530F; 2560B; 2560P
1. Introduction
Currently, radio frequency laterally diffused metal oxide semiconductor (RF LDMOS) power transistors are widely
used in power amplifiers (PAs) for wireless base-stations, television/broadcast and radar applications. High output power
and good linearity are very important for power transistors to
achieve high efficiency operation. As the drain–source breakdown voltage (BVDS / will limit the maximum voltage swing
and greatly affect the linearity of RF LDMOS power transistors, the linearity and output power requirements for PA applications make it necessary to maintain a sufficiently high breakdown voltage.
In the practical design, there have been many methods used
for increasing breakdown voltage. Apples and Vaes suggested
the reduced surface field (RESURF) conceptŒ1 . The RESURF
concept can be used to realize a uniformly distributed electrical
field across the silicon surface in the drift region and achieve
a high breakdown voltage for RF LDMOS power transistors.
Furthermore, double RESURF implements an extra p-doped
layer in the surface of the drift regionŒ2 . The Faraday shield
is another widely used technique in RF LDMOS power transistors. Adding a separate electrode (Faraday shield) above the
drift region may improve the breakdown voltage and decrease
the gate-drain capacitanceŒ3 . Other methods, such as the multiresistivity drift region techniqueŒ4 and p-topŒ5 , have also been
proposed to increase the breakdown voltage.
Many works have discussed and studied the analytical
breakdown voltage modelŒ6 8 , but they have been either too
simple or based on the approximate 1D Poisson equation solution. He et al. reported an analytical model of surface field
distribution and breakdown voltage for an RESURF LDMOS
transistor based on an approximate solution of the 2D Poisson
equation in the drift regionŒ9 . Chen et al. extended the model
to an LDMOS with a Faraday shieldŒ10 . However, both works
ignored the influence of the doping concentration of the p substrate or p epitaxial layer on breakdown voltage.
In this paper, we have derived a closed form analytical
model of the source–drain breakdown voltage for RF LDMOS
power transistors with a Faraday shield by solving the Poisson
equation in the p-epitaxial layer as well as in the n-drift region
based on a parabolic approximation of electrostatic potential.
The breakdown voltages calculated by the presented analytical model show a good agreement with the numerical simulation results given by the Sentaurus TCAD simulator and the
experimental data. The dependence of the breakdown voltage
on the device and process parameters, such as the drift region
length, the Faraday shield length, the doping concentration of
the drift region and the p-epitaxial layer has been discussed and
analyzed in detail. Based on the model, optimization of breakdown voltage and other characteristic parameters, such as onresistance and feedback capacitance for the RF LDMOS power
transistors, is analyzed.
2. Model derivation
Figure 1 shows the cross section of the n-channel RF LDMOS power transistor with a Faraday shield investigated during this work. It includes a pC sink to connect the source to the
substrate contact. A part of the nC poly gate and the n drift
region is covered with the Faraday shield metal layer with an
isolating oxide layer in-between. The device is biased in the
off-state configuration, with substrate and gate grounded and
drain biased at a positive voltage VDS . Normally, the Faraday
shield is connected to the source, which is grounded in common
source configuration, to reduce feedback capacitance CGD and
thus improve the device linearity by screening the poly gate
electrode from the drain metalŒ11 . So in this work the shield is
biased at 0 V for the following modeling derivation and numerical device simulation. Breakdown is thought to occur when
Ž Corresponding author. Email: tjumin@126.com
Received 30 August 2011, revised manuscript received 25 October 2011
044001-1
c 2012 Chinese Institute of Electronics
J. Semicond. 2012, 33(4)
Zhang Wenmin et al.
It is possible to convert the 2D Poisson equation into a
1D equation describing the surface potential in the lateral coordinate x through potential parabolic approximation. In this
work, we approximate the y dependence of .x; y/ by a simple parabolic function asŒ12
1 .x; y/ D c0 .x/ C c1 .x/y C c2 .x/y 2 ;
2 .x; y/ D d0 .x/ C d1 .x/ .y
t1 / C d2 .x/ .y
(3)
2
t1 / ; (4)
where the coefficients ci .x/ .i D 0; 1; 2/ and di .x/
.i D 0; 1; 2/ are functions of x only.
The boundary conditions for the potential functions are
the maximum surface electrical field reaches the silicon critical field (2.5 105 V/cm), and at this moment the applied
drain bias VDS is defined as the breakdown voltage BVDS . At
the breakdown point, it would be reasonable to assume that
both the n drift region and the p-epitaxial region under the
drift region are fully depleted.
The drift region length L is defined as the lightly doped
n region length between the heavily doped nC drain region
and the channel region. LS is the overlap length of the Faraday shield above the drift region. t1 and t2 are the thickness
of the n drift region and p-epitaxial layer, respectively. tf is
the thickness of oxide layer between the Faraday shield and
the drift region. The drift region and the epitaxial layer are assumed to be uniformly doped with impurity concentration of
ND and NA , respectively.
Since both the drift region and the epitaxial layer under
the drift region can be reasonably assumed to be fully depleted
under the breakdown bias condition, according to the Poisson
equation, the electrostatic potential distribution in the drift region and epitaxial layer can be given by
(5)
b .x/ D 2 .x; t1 C t2 / D 0;
(6)
8
" C VFB
ˆ
< ox f
; 0 6 x 6 LS ;
tf
D "si
:̂
0; LS < x 6 L;
(7)
1 .x; t1 / D 2 .x; t1 /;
(8)
ˇ
ˇ
d1 .x; y/ ˇˇ
d2 .x; y/ ˇˇ
D
;
ˇ
ˇ
dy
dy
y D t1
y D t1
(9)
ˇ
d1 .x; y/ ˇˇ
ˇ
dy
Fig. 1. Cross section of the n-channel RF LDMOS power transistor
with Faraday shield.
f .x/ D 1 .x; 0/;
y D0
QOX
QOX
D WM WS
;
(10)
COX
COX
"ox
COX D
;
(11)
tf
where f .x/ is the drift region surface potential, "ox is the dielectric constant of oxide, VFB is the flatband voltage dependent on the oxide charge and the workfunction difference between the Faraday shield metal and silicon, WM and WS are the
workfunctions of the Faraday shield metal and the n-type drift
region, respectively. QOX is areal density of the fixed oxide
charge. Equation (7) is obtained from the continuity of the electric field at the Si/SiO2 interface, Equations (8) and (9) stem
from the continuity of the potential and electrical field at the
n-/p- interface, respectively.
As for VFB , firstly, QOX is here assumed to be in the order
of 1 1010 cm 2 . Secondly, it should be noted that titanium,
whose workfunction is 4.33 eV, is used as the Faraday metal
in this work for the device fabrication. Thirdly, about 4.25 eV
can be taken for the workfunction of the n-type silicon drift
2
2
@ 1 .x; y/ @ 1 .x; y/
qND
C
D
;
0
6
x
6
L;
0
6
y
6
t
;
region. Lastly, tf is at most a few tenths of micron. Therefore,
1
@x 2
@y 2
"si
according to Eq. (10), when the device is near breakdown, over
(1)
the most part of the drift region surface the VFB value can be
estimated to be much smaller than f which is greatly elevated
by the high drain bias voltage. This will be confirmed later by
2
2
@ 2 .x; y/
qNA
@ 2 .x; y/
the simulated surface potential distribution shown in Fig. 2.
C
D
;
@x 2
@y 2
"si
As a result,VFB can be reasonably neglected compared with
0 6 x 6 L; t1 6 y 6 t1 C t2 ; (2)
f , just as done in Refs. [9, 10], Equation (7) can be simplified
into
8
where 1 .x; y/ is the potential function in the drift region,
ˇ
ˆ
< "ox f ; 0 6 x 6 LS
2 .x; y/ is the potential function in the p-epitaxial layer, and
d1 .x; y/ ˇˇ
(12)
"si tf
q, "si are elementary electronic charge and dielectric constant
ˇ
dy
:̂0; L < x 6 L:
y D0
of silicon, respectively.
S
044001-2
VFB D WMS
J. Semicond. 2012, 33(4)
Zhang Wenmin et al.
According to the continuity of Ef .x/ at x D LS , VLS can
be expressed as
Combining Eqs. (1)–(12), the following 1D ordinary differential equation can be derived from the two 2D partial differential Poisson equations.
d2 f .x/
dx 2
˛f .x/ D ˇ;
VLS D 1 .VDS
(13)
where
˛D
2 / csc h
C 2 1 coth
8
2
2"ox .t1 C t2 /
ˆ
ˆ
;
˛1 D 2
C
ˆ
ˆ
<
t1 C 2t1 t2
"si tf t12 C 2t1 t2
ˆ
ˆ
ˆ˛ D
:̂ 2
2
;
2
t1 C 2t1 t2
ˇD
LS < x 6 L;
(14)
qNA t22
qND
:
C
"si
"si t12 C 2t1 t2
df .x/
dx
8
LS x
x
ˆ
C 1 cosh
.VLS 1 / cosh
ˆ
ˆ
ˆ
1
1
ˆ
ˆ
;
ˆ
ˆ
L
S
ˆ
ˆ
1 sinh
ˆ
ˆ
1
ˆ
ˆ
ˆ
<
0 6 x 6 LS ;
2 / cosh
x
LS
.VLS
2
2 sinh
L
2
LS
1
csc h
L
LS
2
1
:
As confirmed by the following calculation and simulation
results, the drift region surface electrical field peaks are always
located at the Faraday shield edge or drain edge as Ef .LS / and
Ef .L/, respectively, which can be derived as below by substituting x D LS and x D L into Eq. (17), respectively.
(15)
.VDS
2 / cosh
2 /
Ef .LS / D
.VLS
2 sinh
2 / cosh
L
L
2 / cosh
Ef .L/ D
LS
2
;
(19)
:
(20)
LS
2
LS
.VLS
2
L LS
2 sinh
2
.VDS
L
2 /
When breakdown occurs at the shield end (x D LS /, by
equating Eq. (19) with the critical electrical field EC , the VDS
can be solved for as BVLS .
L LS
LS
L LS
BVLS D EC 2 sinh
C 1 tanh
cosh
2
1
2
LS
L LS
1 sec h
C 1 cosh
2
1
L LS
C 2 1 cosh
:
2
(21)
Equation (16) indicates that the surface potential is closely
related to the doping concentrations of the drift region and epitaxial layer, i.e. ND and NA , as well as to the drift region length
L and the Faraday shield overlap length LS .
The magnitude of the drift region surface field is obtained
by differentiating Eq. (16) with respect x as
ˆ
ˆ
ˆ
.VDS
ˆ
ˆ
ˆ
ˆ
ˆ
ˆ
ˆ
ˆ
ˆ
ˆ
ˆ
:̂
C 1 2 coth
(18)
8
LS x
x
ˆ
ˆ
.VLS 1 / sinh
1 sinh
ˆ
ˆ
1
1
ˆ
ˆ
;
1 C
ˆ
ˆ
L
ˆ
S
ˆ
sinh
ˆ
ˆ
ˆ
1
ˆ
ˆ
ˆ
ˆ
0
6
x
6
L
;
S
<
f .x/ D 2 C
ˆ
ˆ
L x
x LS
ˆ
ˆ
C .VLS 2 / sinh
.VDS 2 / sinh
ˆ
ˆ
ˆ
2
2
ˆ
ˆ
;
ˆ
ˆ
L LS
ˆ
ˆ
sinh
ˆ
ˆ
2
ˆ
:̂
LS < x 6 L;
(16)
1=2
ˇ
1
where i D ˛i and i D ˛i
are introduced .i D 1; 2/.
D
LS
LS
L LS
C 1 coth
2 coth
1
2
0 6 x 6 LS ;
Solving Eq. (13) with the boundary conditions of f .0/ D
0, f .LS / D VLS and f .L/ D VDS , the surface potential is
given as
Ef .x/ D
LS
1
L
When breakdown occurs at drift region end (x D L), and
vice versa, by equating Eq. (20) with EC , the VDS can be solved
for as BVL.
BVL D
1
1 sinh
L
LS
2
L
Ec 2 sinh
C 2 cosh
L
LS
2
coth
LS
1
LS
L
LS
2 coth
C 1 coth
2
1
2
LS
L
LS
LS
csc h
2 1 csc h
C 1 2 coth
1
1
2
L
x
2
LS
;
C 2 coth
2 cosh
2
LS < x 6 L;
(17)
044001-3
LS
LS
1
1 cosh
L
LS
2
coth
L
LS
1
LS
2
coth
L
LS
2
:
(22)
J. Semicond. 2012, 33(4)
Zhang Wenmin et al.
Fig. 3. Dependence of breakdown voltage on ND . NA D 1 1015 cm 3 , L D 5 m, LS D 1 m, tf D 0.08 m, t1 D 0.6 m,
t2 D 4.2 m.
3. Results and discussions
Fig. 2. (a) Surface potential distribution along the lateral distance and
(b) surface electrical field distribution along the lateral distance for
the RF LDMOS power transistor. ND D 1 1016 cm 3 , NA D 1 1015 cm 3 , L D 4.5 m, LS D 1 m, tf D 0.08 m, t1 D 0.6 m,
t2 D 4.2 m, VDS D 65 V.
Being defined as the drain–source voltage at which either
of the two peak fields reaches EC , BVDS can be taken as the
smaller one of BVLS and BVL.
BVDS D min .BVLS ; BVL/ :
(23)
Finally, Equations (21) and (22) constitute the analytical
model of the drain–source breakdown voltage for the RF LDMOS power transistors. Compared with the previous models
presented by HeŒ9 and ChenŒ10 , the model proposed in this
work is an improvement in at least two aspects. Firstly, the
dependence of BVDS on NA is explicitly described (see Eq.
(15)) owing to a consideration of the Poisson equation in the
p-epitaxial layer in addition to the n drift region. Secondly,
through an appropriate mathematical derivation, the analytical BVDS model is finally given in an explicit closed from.
Of course, as no charge carriers are included in Poisson equations (1) and (2), on which our model is based, full depletion
in both the n-drift region and the p-epitaxial layer is a prerequisite for the model. Fortunately, when the RF LDMOS is at
the onset of drain–source breakdown, on the one hand, usually VDS is high enough to fully deplete the p-epitaxial layer as
well as the n drift region, and, on the other hand, the densities
of the charge carriers caused by the initial breakdown current
are still negligibly low compared to the ionized impurity concentrations. So as verified by the device simulation results, the
above-mentioned full depletion condition is always satisfied
for the device under investigation in this work.
The proposed model is validated by numerical device simulation performed with the Sentaurus TCAD simulator. The
electrostatic potential and charge carrier density are computed
by solving both the Poisson equation and the two carrier continuity equation during simulation.
Figures 2(a) and 2(b) compare modeled and simulated surface potential and surface field along the drift region at the onset of breakdown with VGS D VS D 0 V and VDS D 65 V. The
analytical and simulation results are obtained with ND D 1 1016 cm 3 , NA D 1 1015 cm 3 , L D 4.5 m, LS D 1 m, tf
D 0.08 m, t1 D 0.6 m, t2 D 4.2 m. From Fig. 2(a) one can
see that the analytically modeled potential curve is in very good
accordance with the Sentaurus simulation results. In addition,
as demonstrated by the simulation, the maximum electric field
along the drift region surface is either located at the drain end
(x D L) or at the Faraday edge (x D LS /. The simulated surface field distribution is reproduced on the whole by the model
in Fig. 2(b).
As in the practical design of an LDMOS transistor, it is a
fundamental requirement to minimize the on-resistance while
still maintaining a high breakdown voltage. The on-resistance
is closely related to the drift region doping concentration. The
charge of the n-layer will determine the sheet resistance of that
layer and it is the most critical parameter for the high voltage
device. So first we consider the effect of ND on the breakdown
voltage. Figure 3 shows the modeled and simulated effect of
drift region doping concentration on breakdown voltage. It can
be seen that the modeled BVL curve increases while BVLS
curve decreases with ND and the two curves intersect at a certain point. As the smaller one of BVL and BVLS , the modeled
BVDS experiences an initial rise followed by a subsequent fall
with a peak occurring at the intersection point. When ND is
lower than the critical concentration corresponding to the peak
BVDS , breakdown occurs at the drain end, i.e. BVDS D BVL.
When ND gets larger than the critical value, breakdown occurs
at the shield end, i.e. BVDS D BVLS . As shown in Fig. 3, the
simulated BVDS also initially increases and then decreases with
ND . The modeled BVDS are found to agree quite well with the
simulated BVDS over the range of low ND , but begin to deviate from the simulation data with increasing ND approaching
044001-4
J. Semicond. 2012, 33(4)
Zhang Wenmin et al.
Fig. 4. Dependence of breakdown voltage on Faraday shield length.
ND D 1.4 1016 cm 3 , NA D 1 1015 cm 3 , L D 5 m, tf D
0.08 m, t1 D 0.6 m, t2 D 4.2 m.
the critical concentration. Physically, the drift region cannot be
fully depleted any more as ND increases above a certain value,
then Poisson Eq. (1) is not valid for the whole drift region. This
may be the reason for the discrepancies between the modeled
and simulated BVDS when ND is very high. So the model is
valid for devices whose ND is smaller than the critical value
to fully deplete the drift region. In practice, the critical value
of ND would help mark a local optimum concentration in device and process design for the RF LDMOS power transistors
in terms of the trade-off between breakdown voltage and onresistance.
Figure 4 shows the modeled and simulated effect of Faraday shield length on breakdown voltage. It can be seen that,
on the whole, the breakdown voltage decreases with increasing LS . A closer look at the figure indicates that the modeled
BVDS curve as a function of LS is divided into two segments by
the intersection point of the modeled curves of BVLS and BVL.
To the left of the point, BVDS decreases gradually with increasing LS , tracing BVL versus LS , while to the right of the point,
BVDS drops sharply down the BVLS locus with respect to LS .
As also shown in Fig. 4, the modeled BVDS results are found to
be in good agreement with the corresponding simulation data,
justifying the two-segment LS dependence of BVDS . As reported by Ref. [13], longer LS can result in lower feedback
capacitance CGD , which may help improve the linearity of the
RF LDMOS power transistor. In this sense, at least in the operation region of interest in this work, prolonging LS for the purpose of reducing feedback capacitance may incur a breakdown
penalty. So in practical design such a trade-off may need to be
considered, for example, the LS at the intersection point in Fig.
4 might be a fairly good choice to ensure greatly reduced feedback capacitance at the modest cost of breakdown voltage loss.
The breakdown voltage dependence on the epitaxial layer
doping concentration NA shown in Fig. 5 is similar to ND dependence shown in Fig. 3. When NA is very low, the electrical field peak is located at the shield edge, and breakdown
occurs when the peak field reaches Ec . So BVDS is equal to
BVLS , which is determined by Eq. (21) and increases with NA
as shown in Fig. 5. Electrical field peak moves to the drain end
when NA is very high and breakdown occurs at the drain end.
Now, BVDS becomes BVL, which is determined by Eq. (22)
Fig. 5. Dependence of breakdown voltage on epitaxial layer doping
concentration. ND D 1.4 1016 cm 3 , L D 5 m, LS D 0.4 m, tf
D 0.08 m, t1 D 0.6 m, t2 D 4.2 m.
Fig. 6. Breakdown voltage versus drift region length. ND D 1.4 1016 cm 3 , NA D 1 1015 cm 3 , LS D 0.4 m, tf D 0.08 m, t1
D 0.6 m, t2 D 4.2 m.
and decreases with NA . So there exits an optimal doping concentration, where the electrical field at the shield edge is equal
to that at the drain edge, and breakdown voltage reaches the
largest value. As can be seen also in Fig. 5, the modeled NA
dependence of BVDS is verified by the simulation data which
coincide well with the calculation curve. This demonstrates
that the doping concentration in the p-epitaxial layer can indeed affect the source–drain breakdown voltage by modulating the surface potential and field in the n drift region. As a
result, the NA influence cannot be ignored, as in Refs. [9, 10],
in order to accurately model the breakdown voltage.
Figure 6 shows the dependence of the breakdown voltage
on drift region length L. Again, good agreement is obtained between modeling curve and simulation data points. On the contrary to LS in Fig. 4, the breakdown voltage increases as L. Obviously longer drift region can reduce the lateral electrical field
under a given drain bias voltage, thus increasing BVDS . A more
careful investigation shows that the modeled curves of BVLS
and BVL go up with increasing L at an accelerating and decelerating rate, respectively, intersecting at a critical L whose
value is about 5 m for the device under study in Fig. 6. When
L < 5 m, electrical field peak is located at the shield edge, and
breakdown occurs in this region, BVLS D min .BVLS ; BVL/
as shown in the figure, BVDS is determined by Eq. (21) increas-
044001-5
J. Semicond. 2012, 33(4)
Zhang Wenmin et al.
4. Conclusion
Fig. 7. Breakdown voltage versus drift length. ND D 1 1016 cm 3 ,
NA D 1 1015 cm 3 , LS D 0.75 m, tf D 0.32 m, t1 D 0.6 m,
t2 D 5 m.
In this paper, an analytical model of the drain–source
breakdown voltage of an RF LDMOS power transistor with a
Faraday shield is presented on the basis of an approximate solution to the 2D Poisson equation in the p-epitaxial layer as well
as the n drift region. The modeling calculation results show
a good agreement with the corresponding device simulation
and measurement data over a wide range of device parameters.
With the help of analysis by using the proposed model, the dependence of BVDS on different device parameters is revealed
to be closely associated with the transition of breakdown position along the drift region surface. The device parameters corresponding to these modeled transition points may be chosen in
practical RF LDMOS device design for optimizing trade-offs
between the breakdown voltage and other characteristic parameters such as on-resistance and feedback capacitance.
Acknowledgements
The authors would like to thank Shanghai Beiling Corp.,
Ltd for manufacturing the RF LDMOS power transistors, from
which the experimental results used in this work are measured.
References
Fig. 8. Breakdown voltage versus Faraday shield length. ND D 1 1016 cm 3 , NA D 1 1015 cm 3 , L D 4 m, tf D 0.32 m, t1 D
0.6 m, t2 D 5 m.
ing rapidly with L. When L > 5 m, the electrical field peak
moves to the drain edge, BVL D min .BVLS ; BVL/ as shown
in the figure, and BVDS is determined by Eq. (22) going on increasing but rather slowly with L. Finally BVDS saturates with
L. In practical design, the above-mentioned critical L may be
taken as a limit for drift region length since a further increase
in L will lead to a little BVDS benefit but a considerable onresistance penalty.
The proposed LDMOS model is also validated on the measured breakdown characteristics of LDMOS transistors in different configurations. Figures 7 and 8 show the measured and
modeled dependence of breakdown voltage on the drift region length and Faraday shield length, respectively. The device
parameters necessary for the modeling calculation are listed
under the figures. The values for these parameters are determined in the following way. Firstly, L, LS , NA and tf are
known directly from the device layout and fabrication process
information. Secondly, t1 , t2 and ND are estimated with the
help of the Sentaurus process simulation.
As a consequence, fairly good agreements between modeling calculation results and the corresponding measurement
data shown in the two figures further confirm the validity of
the proposed model.
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044001-6