Signal integrity of TSV
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IEEE EMC Society Distinguished Lecturer Seminar: Signal Integrity of TSV-Based 3D IC July 21, 21 2010 Joungho Kim at KAIST joungho@ee.kaist.ac.kr joungho@ee kaist ac kr http://tera.kaist.ac.kr TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 1 Contents 1) Driving Forces of 3D Package and IC 2) Signal Integrity Design 3) N i C Noise Coupling li Issues I 4) Noise Isolations 5) Summary TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 2 3D Movie TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 3 3D Housings Sk L Sky Lounge Apartment Medical care center Restaurant Fitness & Spa Parking TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 4 16GB Samsung NAND Flash, 8Gbx16 TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package 5 Sharp, Laboratory Morihiro Kada 3D Hamburger SDRAM Di it l Core Digital C RF TERA Terahertz Interconnection and Package Laboratory Analog 6 Terahertz Interconnection and Package Laboratory 6 Expected Market of 3D IC Market Driving Forces of 3D IC “More than Moore” Heterogeneous integration Æ Co-integration of RF + logic + Performance driven memory + sensors in a reduced space Electrical performance Æ”Mid term” t ” driver: > 2010 Logic Æ Interconnect speed and reduced parasitic power consumption DRAM MEMS 3D vs. “More Moore” Æ Can 3D be cheaper than going to the next lithography node? 3D IC Optimum Market Access Conditions Flash Cost Æ “Long Long term term” driven (NAND & NOR) driver: > 2012 CIS RFSiP Form factor driven Density Æ Achieving the highest capacity / volume ratio Æ “Short term” driver: > 2008 Source: “3D 3D IC & TSV Report” Report , Yole Development TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 7 Relatiive wiring p pitch, I/O pitch, and I/O in nterconnecttion density ranges (I/O O per cm2) Technology Trend of 3D IC * ref: f IBM JJ. RES RES. & DEV. DEV VOL. VOL 52 NO.6 NO 6 NOVEMBER 2008, 2008 p555 3D-IC integration I/O: 0.4 - 10.0μm pitch 105 – 108 I/O per cm2 Wiring pitch: 45nm Si-on-Si package p stacking g and chip I/O: 10-50μm pitch 103 - 106 I/O per cm2 Wiring pitch: 0.5μm Organic and ceramic package (SCM and MCM) I/O: 200 200-μm μm pitch 102 - 103 I/O per cm2 Wiring pitch: 25 - 200μm 2000 Time 2010 Relative comparison of I/O densities for 3D silicon, 3D die stacking, and silicon packaging, for both ceramic and organic packaging TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 8 Core Technologies of 3D IC Substrate Via Ball Attachment TSV Unified Design/CAD Environment and Test PCB 3D Thermal & Reliability Analysis And Design Methodologies Chip & SoC Architecture and Design Methodologies 3D IC Low Cost Interposer p Process and Design Technology TERA Terahertz Interconnection and Package Laboratory Chip Chipp-to to--Wafer Stacking & Bonding, TSV Technology Terahertz Interconnection and Package Laboratory 99 Signal Integrity Design Issues in 3D IC Signal Integrity I: Loading Effect & Reflection Port 1 Signal via Cox SiO2 Cvia_ox Ground via Csil Cvia_ox Cvia_ox Cvia_ox Lvia Gsil Rvia Gsil Si Cvia_ox 0 Cox Csil Lvia Gsil Lvia Rvia Gsil Rvia Cvia_ox Cvia_ox Csil Cox 3D IC using g TSV (Through Silicon Via) () S21(Phase) [Degree] Ground via Signal Integrity II: Crosstalk & Jitter -10 -20 -30 -40 Cvia_ox Csil Solid line = model Symbol line = measurement 0.1 Cox 1 Frequency [GHz] 10 CIS 20 Port 2 Logic - Limitation of High Speed Signaling by Capacitive Loading - Impedance Mismatching, Reflection RF Analog - Crosstalk Between TSVs - Die-to-Die Vertical Coupling - Jitter by Inter-Symbol-Interference DRAM EMI Si-Interposer p Power Integrity DSP Chip 7 Chip 6 Chip 5 Chi 4 Chip Chip 3 Chip 2 Chip 1 Through Throughwafer via - Vertical Die-to-Die Die to Die EMI Coupling - RF Sensitivity Reduction by EMI - EM Radiation Increase TERA Terahertz Interconnection and Package Laboratory VSSN Power Ground - Simultaneous Switching Noise caused by Insufficient Power - High freq Noise Coupling & Transfer Terahertz Interconnection and Package Laboratory 10 10 Disadvantages of Wire Bonding Stacked Chip Package • Long Interconnection Æ Long RC Delays Æ High Impedance for Power Distribution Network Æ High Hi h Power P Consumption C ti Æ Poor Heat Dissipation (Thick Substrate) • Bonding Wire located in Chip Perimeter Æ Low Density Chip Wiring Æ Limited Number of I/O Æ Limited I/O Pitch Æ Large Area Package 3D Stacked Chip Package with Wire Bonding • Complex Interposer Æ Long Redistribution Interconnection Æ Bonding Wire located in Interposer Periphery TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 11 11 Key Technology : TSV (Through Silicon Via) • Short Interconnection Æ Reduced RC Delays Æ Low Impedance for Power Distribution Network Æ Low Power Consumption Æ Heat Dissipation Through Via 3rd Chip (Thinned Substrate) Under fill Dielectric 2nd Chip (Thinned Substrate) • No Space p Limitation for Interconnection Dielectric Under fill Multi-level On-chip On chip Interconnect Æ High Density Chip Wiring Æ No Limitation of I/O Number Æ No Limitation of I/O Pitch ÆS Small a Area ea Package ac age SiO2 1st Chip Si-Substrate 3D TSV Stacked IC TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 12 ★ Why does TSV Family happy ^^ ? Elevator !! Happy TSV Family~! So fast! ♬ It’s awesome!! Sad Wire-bonding Family~! 4th Floor So tired T^T ! It takes too much energy !! • Shorter distance ! • Lower loss of energy ! 3rd Floor T^T Stairs !! T0T 2nd Floor ^^ ^^ TERA Terahertz Interconnection and Package Laboratory 1st Floor Terahertz Interconnection and Package Laboratory 13 10 chip stacked Package by KAIST 10 9 8 7 6 5 4 3 2 1 55 μm TSV diameter 150 μm Pitch TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 14 Background(1): High-frequency Channel Loss in TSV Gsil -Significant Significant high high-frequency frequency signal loss occur at Signal Transmission Cvia_ox Through TSV -The signal loss through TSV is caused by substrate leakage and coupling S21(mag gnitude) [ddB] 0.1μm Frequency [GHz] Si SiO2 Ta Cu Close up of through wafer via TERA Terahertz Interconnection and Package Laboratory Magnitude of S21 Terahertz Interconnection and Package Laboratory 15 Background(2): Increased Channel Loss in Multi-Stack TSV -Signal loss increases substantially with number of stacks/TSVs -The Th signal i l lloss through h h TSV iis caused db by substrate b lleakage k and d coupling li Increased Total Resistance Increased Total Capacitance (Slopes) 10 9 8 2-Stack TSVs 7 6 5 4 3 5-Stack TSVs 10-Stacked TSVs 2 1 TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 16 A Through Silicon Via Structure on Double-sided Silicon Substrate Underfill Bump Metal (M1,M2) Inter-metal Dielectric Insulation layer y Double-sided Double sided Silicon Substrate TSV 1111111111111 Cinsulator GSi sub Inter-metal Dielectric Underfill TERA Terahertz Interconnection and Package Laboratory Bump Cu SiO2 Si Terahertz Interconnection and Package Laboratory 17 17 Frequency-dependent Loss of Through Silicon Via Frequency dependent term 0 Cinsulator GSi subb i l t Leakage current Cu SiO2 Si Loss term I Insertion loss (dB B) -1 -2 -3 -4 Capacitive region Resistive region -5 -6 6 0.1 1 10 20 Frequency (GHz) TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 18 18 Scalable Equivalent Circuit Model of a TSV Signal TSV CBump Cinsulator Cinsulator LTSV RTSV TERA Cinsulator Cinsulator LTSV CSi sub GSi subb Cinsulator Cinsulator Cinsulator Cinsulator B Bump Terahertz Interconnection and Package Laboratory Ground TSV CBump RTSV B Bump Structural Parameters TSV diameter :d TSV-to-TSV pitch : p SiO2 thickness : t Height :h Bump diameter : D Equations Cinsulator (d,h,t) (d h t) CSi sub (d,h,p,t) CBump (p,D) GSi sub (d,h,p,D) (d h p D) RTSV (d,h) LTSV (d,h,p) Terahertz Interconnection and Package Laboratory 19 19 Analysis of a TSV Channel with Insulator Thickness of TSV Insulator thickness of TSV (t) 0 Signal Ground Top -0.5 S21 magnitude e (dB) Top CInsulator/2 CInsulator/2 CInsulator/2 -1.5 -2 Bottom Bottom Leakage current CInsulator=7.8 =7 8 pF Insulator thickness of TSV ↓ -2.5 -3.5 3.5 0.1 Ground Signal CInsulator=2.6 pF -1 -3 CInsulator/2 CInsulator=1.6 pF [A] 1 10 20 Frequency (GHz) Equivalent circuit model ( t = 0.5um ) E i l t circuit Equivalent i it model d l(t=0 0.3um 3 ) Equivalent circuit model ( t = 0.1um ) Î Leakage through silicon substrate dominantly increases due to lowered impedance with increased Cinsulator in region [A]. Î Insulator thickness dominantly affects frequency dependent loss of a TSV channel in region [A]. TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 2020 Analysis of a TSV Channel with Pitch between TSVs Pitch between Signal & Ground TSV (p) Top LTSV 0 Ground Top CSi sub LTSV GSi sub CSi sub=3.14 fF -0.5 05 S21 magnitu ude (dB) Signal CUnderfill, IMD LTSV ↓ CSi sub=3.48 fF -1 -1.5 CSi sub=4.26 fF -2 -2.5 Pitch between TSVs ↓ -3 -3.5 0.1 Signal Bottom CUnderfill, Bottom Ground Bottom [B] 1 10 [C ] 20 Frequency (GHz) Equivalent circuit model ( p = 190um ) Equivalent circuit model ( p = 150um ) Equivalent circuit model ( p = 100um ) ÎDue to relative small capacitance, pitch affects frequency dependent loss of a TSV channel from region [B]. Î From region [C], inductance effect becomes dominant. Î Pitch dominantly affects frequency dependent loss of a TSV channel in region [B]. TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 2121 Analysis of a TSV Channel with TSV Diameter Via diameter of TSV (d) CInsulator ↑ CUnderfill, IMD Signal Ground Top CSi sub ↑ LTSV ↓ 0 Top CInsulator I l t CSi sub LTSV LTSV GSi sub RTSV RTSV S21 magn nitude (dB) CInsulator I l t -0.5 -1 -1.5 -2 -2.5 -3 CInsulator Signal CInsulator CUnderfill, IMD Bottom Ground B tt Bottom -3.5 0.1 Via diameter ↑ Î The effect of decrease of pitch between TSVs [A] [B] 1 10 [C ] 20 Frequency (GHz) Equivalent circuit model ( d = 32um ) Equivalent circuit model ( d = 20um ) Signal TSV CSi sub ↑ Ground TSV Equivalent circuit model ( d = 10um ) CInsulator ↑ Î Via diameter affects frequency dependent loss of a TSV channel, dominantly Terahertz Interconnection and Package Laboratory 2222 TERA in region [A] and [B]. Terahertz Interconnection and Package Laboratory Analysis of a TSV Channel with Via Height of TSV Via height of TSV (h) CInsulator ↑ Signal Ground Top CSi sub ↑ LTSV ↑ [B] [C ] 0 Top CInsulator CSi sub LTSV LTSV GSi sub RTSV RTSV CInsulator Ground Bottom Bottom CSi sub ↑ -1 -1.5 -2 LTSV ↑ Via Height ↑ -2.5 -3 CInsulator Signal S21 magnitude e (dB) CInsulator -0.5 -3.5 -3 5 0.1 [A] 1 10 20 Frequency (GHz) Equivalent circuit model ( h = 110um ) Equivalent circuit model ( h = 80um ) Equivalent circuit model ( h = 50um ) Signal TSV CInsulator ↑ Ground TSV Î Via height affects frequency dependent loss of a TSV channel in all frequency ranges. TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 2323 Inter-symbol Interference (ISI) by Channel Loss InterInter-symbol Interference is the interference between adjacent pulses of a data - The channel BW Limit degrades the signal quality It depends on line line--length length,, data rate and sub. materials on PCB Long Channel 600 600 500 500 Voltage [mV] Voltage [mV] Short Channel 400 300 200 400 300 200 100 100 0 0 -100 0110110 0000 40 % reduction -100 0 5 10 15 0 5 Time [ns] 10 15 Time [ns] – Channel Length = 10 cm – 3 Gbps – FR4 (Loss Tangent = 0.03) – Channel Length = 40 cm – 3 Gbps – FR4 (Loss Tangent = 0.03) [ ISI effect due to line-length ] TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 24 24 Inter-Symbol Interference at the TSV Equalizer S21(ma agnitude) [[dB] Voltage (V) 0 25 0.25 0 -0.25 Frequency [GHz] 0 20 40 60 80 100 Ti Time ((ps)) Magnitude of S21 TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 25 25 The Proposed TSV Equalizer using an Ohmic Contact Ohmic contact ((Al/n+ type) yp ) Signal TSV n+ high doped Silicon Ground TSV n-type Silicon Substrate Bump Bump We intentionally made leakage by using an Ohmic contact resulting in DC attenuation between signal and ground TSV TSV. TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 26 26 Frequency Domain Simulation-based Verification of the TSV Equalizer Performance 0 Inse ertion losss (dB) Insertion loss of 8 TSVs without TSV equalizer -2 -4.8 dB -3.8 dB -4 - 4.5 -6 1 dB 0 7dB 0.7dB Flattened from DC to 10GHz (Nyquist frequency of 20Gbps) Insertion loss of 8 TSVs with TSV equalizer -8 0.1 1 10 20 F Frequency(GHz) (GH ) • We successfully flattened frequency dependent loss by 3.8 dB by using TSV Equalizer Equalizer. TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 27 27 Time Domain Simulation-based Verification of the TSV Equalizer Performance 0 25 0.25 Voltage (V) Voltage (V) 0 25 0.25 0 -0.25 0 20 40 60 Ti Time (ps) ( ) 80 100 Pk-pk jitter : 16 ps 0 -0.25 0 Eye opening: 100mV 20 40 60 80 100 Ti Time ( ) (ps) • We successfully achieved normalized pk pk-pk pk jitter and eye eye-opening, opening 32% and 20%, meanwhile the unequalized eye is completely closed. TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 28 28 Time-Domain Measurement Results Eye-opening : 904 mV = 90.4% Vin (1V) 0.5 Pk-pk jitter : 50 ps = 0.5% 0 5% UI 0 2 4 6 8 0.5 Pk-pk jitter : 12.5 ps = 1.25% 1 25% UI Data rate : 100 Mb/s Data Pattern : PRBS 211-1, Source amplitude : 1 V TERA Terahertz Interconnection and Package Laboratory 0.2 0.4 0.6 0.8 0 1 Time (nsec) Time (nsec) 0.5 Pk-pk jitter : 27.8 ps = 18.9% 18 9% UI 0 0 10 Eye-opening : 685 mV = 68.5% Vin (1V) 1 0 0 Eye-opening : 720 mV = 72% Vin (1V) 1 Voltage (V) 1 Voltage (V) Measured Eye-diagrams of a TSV channel Voltage (V) Data rate : 1 Gb/s Data Pattern : PRBS 211-1, Source amplitude : 1 V 40 80 120 160 200 Time (psec) Data rate : 5 Gb/s Data Pattern : PRBS 211-1, Source amplitude : 1 V Terahertz Interconnection and Package Laboratory 2929 Coupling Issues in Stacked Dies using TSV Bonding Adhesive Bonding Adhesive P-Substrate 3rd Chip Inductor TSV TSV TSV N+ P+ P+ N+ N-Well N Well 2 N+ P+ N+ P+ N+ N-Well N Well P-Substrate TSV to Active Circuit Coupling N+ P+ N+ Metal to Metal N-Well Coupling 3 TSV N+ P+ P+ N+ N W ll N-Well 2nd Chip Inductor 1 TSV to TSV Coupling TSV N+ P+ N+ P+ N+ N W ll N-Well P-Substrate N+ P+ TSV N+ N W ll N-Well 1st Chip < CROSSSECTIONAL VIEW > TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 30 Measurement Result of Coupling between TSVs S G S G < Top p view> Coupling coefficient [dB] -10 -20 20 Csi -30 Gsi + Cparasitics -40 Cox Measurement -50 Model -60 Cm Cox R L Cp1 0.1 1 10 20 Freq [GHz] Csi Gsi M • Analytic model of coupling between TSVs shows good g agreement with measurement result < Equivalent circuit model of coupled TSV> TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory -31- 31 Shielding Methods for TSV Coupling 1) Re-design of TSV materials and dimensions 2) Separation 3) G d Ri Guard Ring 4) GND Shield TSV 5) Metal Ring TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 32 Shielding Effect Measurement – (1) Metal Ring -10 G S < Top view> Cm Coupling coeffficient [dB] C G -20 -30 -40 Cox R L Csi Gsi M w/ metal ring -60 01 0.1 Cp1 w/o metal ring -50 1 10 20 Freq [GHz] • Metal ring has shielding effect only in high frequency because it blocks coupling in IMD layer < Equivalent circuit model of coupled TSV> TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory -33- 33 Shielding Effect Measurement– (2) Guard Ring -10 G S < Top view> Cm Coupling coeffficient [dB] C G -20 -30 -40 Cox R L Csi Gsi M w/ guard ring -60 01 0.1 Cp1 w/o guard ring -50 1 10 20 Freq [GHz] • Guard ring has good shielding effect in every frequency range because guard ring structure can partly block substrate coupling between TSVs < Equivalent circuit model of coupled TSV> • Main factor of coupling between TSVs is silicon substrate TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory -34- 34 Shielding Effect Measurement– (3) Guard Ring + Metal Ring -10 G S < Top view> Coupling coeffficient [dB] C G -20 -30 -40 w/o guard ring -50 w/ guard ring w/ guard ring + metal ring Cm -60 01 0.1 Cox R L Cp1 1 Csi Gsi M 10 2x10 Freq [GHz] • Metal ring structure with guard ring can further decrease coupling between TSVs < Equivalent circuit model of coupled TSV> TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory -35- 35 Measurement Environments for Model Verification Vector Network Analyzer (VNA) Measurement instrument g Technology gy PNA-L N5230A : Agilent Frequency range : 10MHz ~ 20GHz Frequency sweep : log scale, 1601 point microprobe : GGB industries inc. 40A-GS250-P microprobe microprobe Port1 Port2 RDL RDL ILD/IMD FOX P+ substrate contact FOX P+ FOX P+ TSV Open silicon substrate [ Cross C sectional ti l view i off test t t sample l ] TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 36 36 Designed Test Sample Images RDL(Redistribution layer) G G Contact IMD / ILD Silicon substrate S RDL(Redistribution layer) Dummy skip layer coupling TSV S Contact [ Top view of test sample ] TSV [ Cross sectional view ie of test sample ] TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 37 37 Analysis of Noise Coupling based on the 3D TLM Model Csub Rsub CTSV TSV silicon substrate Distance Di t b between t contact t t and d TSV : 100 μm Substrate height : 100 μm TSV diameter : 30 μm TSV SiO2 thickness : 0.5 μm Coup pling coefficient [dB] conta ct -30 ILD/IM D A B -35 35 Silicon resistance dominant -40 -50 TSV SiO2 capacitance d i dominant t -55 -60 10M 100M 1G Frequency [GHz] Coupling can be divided into 3-regions 3 regions In region A, B, and C TSV SiO2 capacitance , silicon resistance, silicon capacitance is the dominant factor to the coupling TERA Silicon capacitance dominant -45 Terahertz Interconnection and Package Laboratory C 10G Terahertz Interconnection and Package Laboratory 38 38 Substrate contact to TSV Coupling 3D TLM Model Verification by Measurement – with Distance Variation Coup pling coeffiicient [dB]] -10 50 um Distance Increases 100 um -20 200 um -30 -40 Measurement The p proposed p model -50 10M 100M 1G Frequency [Hz] 10G Proposed model’s coupling coefficient estimation is less than measurement over 1GHz But model follows same tendency as the distance increases TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 39 39 Analysis of Noise Coupling based on the 3D TLM Model – with TSV SiO2 Thickness Variation Csub Rsub CTSV TSV silicon substrate TSV SiO2 thickness (tox TSV) Di t Distance b between t contact t t and d TSV : 100 μm Substrate height : 100 μm TSV diameter : 30 μm TSV SiO2 thickness : 0.3, 0.5, 0.7 μm Substrate conductivity : 10S/m Coup pling coefficient [dB] conta ct -20 ILD/IM D -30 A tox_TS V C B CTS V Coupli ng -40 -50 -60 10M Coupling coefficient d decreases tox_TSV = 0.3um tox_TSV = 0.5um tox_TSV = 0.7um 100M 1G Frequency [GHz] TSV SiO2 thickness determine the coupling coefficient in the region A If we increases TSV SiO2 thickness, coupling coefficient decreases in the region A TERA Terahertz Interconnection and Package Laboratory 10G Terahertz Interconnection and Package Laboratory 40 40 Analysis of Noise Coupling based on the 3D TLM Model – with Silicon substrate Height Variation (1) Csub Rsub CTSV height (h) TSV silicon substrate Distance Di t b between t contact t t and d TSV : 100 μm Substrate height : 30, 70, 100 μm TSV diameter : 30 μm TSV SiO2 thickness : 0.3 μm Substrate conductivity : 10S/m Coup pling coefficient [dB] conta ct -20 ILD/IM D A h -30 -40 -50 -60 10M C B CTS V Coupli ng , , Rsub Csub Coupling coefficient increases h = 30um h = 70um h = 100um 100M 1G Frequency [GHz] 10G If silicon substrate height decreases decreases, all component value is changed At the whole frequency, the coupling coefficient increases as silicon substrate height increases TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 41 41 Analysis of Guard-ring based on the 3D TLM Model – with Guard-ring Location Variation guardring conta ct TSV silicon substrate Distance between contact and TSV : 100 μm Substrate height : 100 μm TSV diameter : 30 μm μm TSV SiO2 thickness : 0.5 μ Guard-ring distance from contact : 10 μm Guard-ring width : 10 μm Coup pling coefficient [dB] -30 A C B A’ C’ B’ -40 -50 w/o guard-ring with guard-ring around TSV with guard-ring around contac -60 0 -70 10M 100M 1G Frequency [Hz] 10G Guard-ring Guard ring around contact shows more isolation effect compared to guard-ring guard ring around TSV Guard ring around contact does not have frequency dependent isolation effect Guard-ring TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 42 42 PLL Coupling Simulation Environment ½ noise source Is assumed as square wave (500mV , 305MHz ) [ Active circuit noise ] PFD LPF CP ½ ½ ½ ½ VCO Output ½ [ PLL ] ILD / IMD metal S contact G S TSV TSV ili b silicon substrate [ Active circuit to TSV coupling model ] [ PLL external clock ] Contact to TSV coupling model was proposed and verified in the previous chapter HSPICE simulation was performed using the contact to TSV coupling model and PLL schematic TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 43 43 Substrate Noise Coupling to TSV 0 305 MHz 305*3 MHz 305*5 305 5 MHz -30 20 -20 305*7 MHz 305*9 MHz ... -40 -60 -50 -60 10M -80 100M 1G Frequency [Hz] 10G 305MHz square wave noise is coupled to TSV by the coupling coefficient Up to 9th harmonic frequency, coupling coefficient is almost constant TERA -40 Terahertz Interconnection and Package Laboratory No oise voltag ge (dBV) Co oupling coefficient betwee en contact a and TSV [d dB] -20 -100 Terahertz Interconnection and Package Laboratory 44 44 PLL Phase Noise Degradation due to Active Circuit to TSV Coupling -50 Pha ase Noise (dBc/Hz) 60 -60 -70 No noise 305MHz, 500mV coupled noise Phase noise spur generated due to TSV coupled noise Externa l Clock PLL Output 3rd harmonic of 2.4GHz output 2nd harmonic of 2.4GHz output -80 -90 -100 1M 10M 100M Frequency [Hz] 1G 5G PLL phase noise shows spurs at 5MHz due to coupled 305MHz noise PLL phase noise spur at 75MHz, 2.4GHz, 4.8GHz is due to circuit design TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 45 45 Substrate Noise Coupling to TSV Co oupling coefficient betwee en contact a and TSV [d dB] w/o guard-ring 0 305 MHz Guard-ring around TSV 305*3 MHz 305*5 305 5 MHz -30 20 -20 305*7 MHz 305*9 MHz ... -40 Guard-ring around TSV -60 -50 -60 10M -80 100M 1G Frequency [Hz] 10G Guard ring around TSV decreased coupling coefficient Guard-ring PLL coupled noise also decreased by the guard-ring around TSV TERA Terahertz Interconnection and Package Laboratory -40 No oise voltag ge (dBV) -20 -100 Terahertz Interconnection and Package Laboratory 46 46 PLL Phase Noise Degradation due to Active Circuit to TSV Coupling -50 w/o guard-ring Pha ase Noise (dBc/Hz) 60 -60 -70 Guard-ring around TSV Externa l Clock Phase noise decreased ~4dBc/Hz PLL Output 3rd harmonic of 2.4GHz output 2nd harmonic of 2.4GHz output -80 -90 -100 1M 10M 100M Frequency [Hz] 1G 5G PLL phase noise spur at 5 MHz decreased by the guard guard-ring ring Guard-ring around TSV can improve coupling degraded circuit performance TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 47 47 BER Calculation in Mixed-Signal System Model Spec ctrum [dBm] tr T -20dB/dec f = 1 Coupling coefficient π tr -40dB/dec data from RX raw data from TX BER teste r data from RX raw data bit error occurs 3 5 7 9 Harmonic number frequency Generated noise from digital clock Transmitte r of RF Signal Digital noise Coupling coefficien t Receiver RF signal RF signal g Baseband (BER tester) Raw Data Delay TERA Terahertz Interconnection and Package Laboratory Amp Terahertz Interconnection and Package Laboratory 48 48 Dimension Region with Coupled TSV Parameters Constant BER curve BER 50 um 1 d = 1 ~ 50um p = 200um 30 um TSV V diameterr tox = 0.5um hTSV = 30um ~ 200um 3x10-1 20 um 2x10-1 10 um 10-1 5 um 1 um Dimension region for acceptable BER 30 um 50 um 70 um 100 um 150 um 200 um 0 Silicon thickness • In certain digital application, dimension region of TSV design parameters for p BER can be obtained from the modeling g of coupled p TSVs acceptable TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 49 49 Dimension Region with Coupled RDL Parameters Constant BER curve BER 200 um 1 Dimension region for acceptable BER Edge-tto-edge sp pace 150 um 3x10-1 100 um 2x10-1 60 um s = 20 ~100 um 40 um w = 20um 20 um 50 um 70 um 100 um 150 um t = 1um l = 100 ~500 um 200 um 300 um 10-1 0 Coupled length • In certain digital application, dimension region of RDL interconnects design parameters for acceptable p p BER can be obtained from the modeling g of coupled p RDL interconnects TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 50 50 Dimension Region with Coupled TSV Parameters with Guard Ring Constant BER curve BER 50 um 1 d = 1 ~ 50um p = 200um 30 um TSV V diameterr tox = 0.5um hTSV = 30um ~ 200um 3x10-1 20 um 2x10-1 10 um I Increased d di dimension i region for acceptable BER 5 um 1 um 30 um 50 um 70 um 10-1 100 um 150 um 200 um 0 Silicon thickness • By applying guard ring structure, dimension region for acceptable BER is significantly increased Æ Target BER can be satisfied within realizable dimensions TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 51 51 Vertical Coupling of DDR3 to ZigBee Transceiver Zigbee Tranceiver VDD N+ P+ P+ Guardring VCO of ZigBee Transceiver Differential Spiral Inductor 2nd Chip Die-to-Die Die to Die Vertical Coupling N+ P+ N-Well TSV N+ N+ P+ N+ N Well N-Well 20dB/decade TERA DDR3 T 40dB/decad e 1 ㅡ T Terahertz Interconnection and Package Laboratory Tr 1st Chip Amplittude DDR 3 1 ㅡ Pi*Tr www.micron.co F Frequenc m 3 5 79 y Terahertz Interconnection and Package Laboratory 52 52 Experimental Verification of Proposed Model (Line Type Clock Tree to Two Turn Spiral Inductor) C Clock 40 L 20 0 -20 Inductor L -80 -100 -120 0.1G 40 20 0 Inductor -40 -60 60 L Clock C Clock L Inductor LM C epoxy 1G -20 L -40 Clock L Inductor LM -60 R,C csub -80 -100 10G -120 20G Voltage Trransfer Ratio [dB] Impedance e [dBΩ] 60 2 Turn Z11=Clock Tree Impedance Z21=Transfer Impedance Z21/Z11=V2/V1 Measurement Frequency[Hz] • Before clock tree resonance, voltage transfer ratio is determined by Cclock and Linductor. • After clock tree resonance, voltage transfer ratio is determined by Lclock and Linductor. TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 5353 53 Investigation of Vertical Coupling Effect on VCO Spur 0 2.4 GHz -40 -20 20 High-frequency Multiplicative Noise -60 -80 -100 -120 0 1G 0.1G VCO Outpu ut Spectrum [dBm] 20 1G 10G Frequency(Hz) Voltage Transfer R Ratio [dB] Clock Spectrum [d dBV] Clock spectrum p (before ( vertical coupling) Voltage Transfer Ratio 1 Z 21 V2 /I1 V2 = = = A Z11 V1/I1 V1 1 )dB = 20log(V2 )dB A 1 20log(V1 )dB + 20log( )dB A = 20log(V2 )dB 20log(V1 * 20G 20 • Main mechanism of spur 0 generation ti is i high-frequency hi h f -20 2.4 GHz multiplicative noise -40 • To reduce the spur at 10MHz offset -60 from center frequency, design guide has to be proposed. VCO Output Spectrum (before vertical coupling) -80 VCO Output Spectrum (after vertical coupling) -100 100 2.38 TERA Terahertz Interconnection and Package Laboratory 2.4 2.42 2.44 Frequency(GHz) Terahertz Interconnection and Package Laboratory 54 54 Investigation of Design Guide for Spur Reduction (Epoxy Thickness) 0 -20 20 -40 -60 -80 -100 -120 0 1G 0.1G VCO Outpu ut Spectrum [dBm] 20 1G 10G Frequency(Hz) Voltage Transfer R Ratio [dB] Clock Spectrum [d dBV] Clock spectrum p (before ( vertical coupling) Voltage Transfer Ratio Port 2 Port 1 Spiral Inductor Chip 90um 80um 20um Clock Tree Chip 20G 20 • Spurs at 5MHz and 10MHz offset 0 f from center t frequency f satisfy ti f the th -20 spur spec of ZigBee system. -40 • Increasing epoxy thickness is -60 highly effective for spur reduction. VCO Output Spectrum (before vertical coupling) -80 VCO Output Spectrum (after vertical coupling) -100 100 2.38 TERA Terahertz Interconnection and Package Laboratory 2.4 2.42 2.44 Frequency(GHz) Terahertz Interconnection and Package Laboratory 55 55 Summary -TSV is the most critical interconnection structure in 3D IC. - TSV can cause significant channel loss for high-speed signaling. - Equalizer E li or specific ifi I/O schemes h are needed d d to t supportt low l power and high-speed data transmissions. - Crosstalk and coupling between TSV and active circuit need to be considered when designing the TSV arrangement configurations. - Shielding structures are needed to reduce the TSV crosstalks and noise couplings. TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 56
