Power Integrity of SiP (System In Package)
advertisement
IEEE EMC Society Distinguished Lecturer Seminar: Power Integrity of SiP (System In Package) July 21, 21 2010 Joungho Kim at KAIST joungho@ee.kaist.ac.kr joungho@ee kaist ac kr http://tera.kaist.ac.kr TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 1 Contents I. Needs of SiP II. Power Integrity of SiP III III. PDN Design D i Ch Challenges ll iin SiP IV. Embedded decoupling capacitor and EBG structures V. PDN Isolation in SiP design VI VI. PDN noise i coupling li effects ff t on Mixer, Mi LNA LNA, and d OpAmp O A VI. SSN Free 3D Clock Distribution Network VII. Power Integrity of TSV based 3D SiP VIII. Conclusion TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 2 Ubiquitous Mobile Life Physical World Player Mobile Platform Wired Computing Communication Brain Wireless Entertainment Medical/Welfare service Product Internet Robot Sensing/Cognition/ Identification T l h Telephony network Auto-mobile Auto mobile TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 3 3D Convergence System In Package 3D Memory Stack Multi-core Processor RF Transmitter/ Receiver Filter Antenna SRAM DRAM Flash Embedded de-cap TERA Terahertz Interconnection and Package Laboratory Termination Resistor EBG Structure Terahertz Interconnection and Package Laboratory 4 Advantages of SiP approach □ֺSmall form factor □ֺ Fast time to market □ֺ Inhomogeneous □ g device integration g □ֺ Integration of passive devices, filters, and antenna □ֺ Suitable for RF mobile communication systems □ֺ Low cost TERA Terahertz Interconnection and Package Laboratory 5 Terahertz Interconnection and Package Laboratory 5 Power Supply Current Path Discrete Decoupling Capacitor on PCB Low Inductance Capacitor on Package Ball Grid Array Package Chip Bulk Capacitor Ball Bonding VRM Ground Power Chip ΔI Decoupling Capacitor On Chip Wi Wire Bonding P k Package B ll Ball P/G Network Bonding Decoupling Capacitor On Package PCB P/G Network Decoupling Capacitor On PCB VRM Bulk Capacitor Near VRM Low impedance path of current-flow at high frequency. Screen out large inductance. TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 6 Simultaneous Switching Noise (SSN) V=VCC+ΔV ΔI=ΔI1+ ΔΙ2+ …ΔIn Common Power Supply ΔI1 H L 1 ΔI2 H L 2 ΔIn H Parasitic Inductance (due to Pins, Bond-wire, etc.) n L L L Common Ground Chip ΔI Simultaneous Switching Noise (SSN) : ΔV = L Δt Increase of Maximum Power (Current) Increase of Clock Frequency SSN caused by simultaneous switching output buffers TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 7 Problems caused by SSN - Voltage margin reduction - Logic failure - Noise N i coupling li tto sensitive iti circuits i it (RF and d analog l circuits) i it ) - Circuit reliability degradation (S/N, sensitivity) - Signal integrity degradation ( eye, jitter) - Electromagnetic El t ti radiation di ti TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 8 Inductive Impedance of PDN in SiP LPKG,wire LPKG,trace LPKG,via LPKG,ball LPCB,decap S G LPCB,via LP/G plane P S Ltotlal = LPKG,wire+ LPKG,trace+ LPKG,via+ LPKG,ball+ LPCB,via+ LP/G plane+ LPCB,decap TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 9 Reduction of PDN Inductance - Locate as close as possible - g of interconnect Reduce length - Wider, planar interconnect - Ground/return current path as close as possible, minimal loop size - Choose low ESL decoupling capacitors - On chip decap > on-package decap > on-PCB decap - Thinner PCB and package substrate - Provide multiple paths (via (via, pin pin, wire wire, decoupling capacitors) - Choose advanced package - Cost balance needed TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 10 Power/Ground Network Impedance P/G Imp pedance Actual Impedance Ideal Impedance kHz TERA Terahertz Interconnection and Package Laboratory MHz GHz THz Frequency [log] Terahertz Interconnection and Package Laboratory 11 Frequency Dependent Functions of Discrete Decoupling Capacitor Decoupling Capacitor Powerr/Ground N Network Impedancee Chip VRM jωLVRM − Ground j j < jωLDECAP − ωCVRM ωC DECAP Power Capacitance given by Discrete Decoupling Capacitors Inductance given by • ESL of Discrete Capacitor • Mount Pad • Power/Ground Traces • Power/Ground Via Inductance by VRM or ESL of Bulk Capacitor KH KHz TERA Terahertz Interconnection and Package Laboratory Capacitance by Power/Ground Plane MH MHz Inductance by Power/Ground Plane GHz Frequency Terahertz Interconnection and Package Laboratory 12 Frequency Dependent Functions of Discrete Decoupling Capacitor Decoupling Capacitor Powerr/Ground N Network Impedancee Chip VRM Ground jωLDECAP − Power Capacitance given by Discrete Decoupling Capacitors TERA Terahertz Interconnection and Package Laboratory j ωC DECAP C j ωC DECAP < jωLVRM − MH MHz j ωCVVRM < jωLPLANE − j ωC PLANE Capacitance by Power/Ground Plane Inductance given by • ESL of Discrete Capacitor • Mount Pad • Power/Ground Traces • Power/Ground Via Inductance by VRM or ESL of Bulk Capacitor KH KHz jωLDECAP − Inductance by Power/Ground Plane GHz Frequency Terahertz Interconnection and Package Laboratory 13 Good Power Distribution Network Battery Decoupling Capacitor p Voltage regulator Power plane on PCB Package Device Wirebond TERA Terahertz Interconnection and Package Laboratory Power trace on PCB Terahertz Interconnection and Package Laboratory 14 Low Impedance Water Pipe Resistive Pipe Inductive Pipe TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 15 What happens if power distribution network is bad? TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 16 What happens if power distribution network is Good? TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 17 Impedan nce (Logarithm) Impedance Property of Chip-Package-PCB Hierarchical PDN Interaction 10MHz 100MHz Interaction 1GHz Frequency (Logarithm) 10GHz Advantage and application of PDN analysis in frequency domain - Intuitive analysis - Easy to control impedance property Need for hierarchical PDN simulation - Interactions between different level PDNs generate high impedance peak. TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 18 Case Study : Design of P/G Ring and Bonding Wire for 40Gbps PKG The bonding wire length is minimized (1,800 µm Æ 630 µm), by cutting power/ground rings. [ Previous Design ] 1,800µm TERA Terahertz Interconnection and Package Laboratory [ Proposed Design ] 630µm Terahertz Interconnection and Package Laboratory 19 High P/G Plane Impedance made by P/G Plane Resonance Low Impedance (1,0)/(0,1) : 518MHz 0 0 0.02 0.02 Mode Suppression 0.04 0.1 (1,1) : 743MHz 0.04 0.1 0.06 0.08 0.05 01 0.1 0 0 0.02 0.04 0.08 0.1 0.12 0.14 01 0.1 0 0 0.12 0.06 0.06 0.08 0.05 0.02 P/G Plane 0.14 0.04 0.12 0.06 0.08 0.1 0.12 0.14 0.14 Center Located (2,0)/(0,2) : 1043MHz (2,2) : 1493MHz 0 0.02 0.04 0.1 0.06 0.08 0.05 ( f r )mn = 1 2π μ0ε r ε 0 ⎛ mπ ⎞ ⎛ nπ ⎞ ⎜ ⎟ +⎜ ⎟ ⎝ a ⎠ ⎝ b ⎠ 2 0 0.02 0.04 a = b = 14cm TERA Terahertz Interconnection and Package Laboratory 0.08 0.1 0.12 0.14 0.14 0.02 0.04 0.06 0.08 0.05 0.1 0 0 0.12 0.06 0 0.1 0.1 0 2 High Impedance 0.02 0.04 0.12 0.06 0.08 0.1 0.12 0.14 0.14 Terahertz Interconnection and Package Laboratory 20 Spectrum Analyzer Measurement of P/G Plane Edge Radiation TV2 SA Measurement TV2 P/G Plane Impedance -10 10 500 MHz CLK 100 10 1478 Æ 3rd - 30 1 0.1 0.01 - 50 TV2 (7cm 7cm) (7cm,7cm) 14cm - 70 0 0.5 1 1.5 2 Frequency Frequency q y [[GHz] [[GHz]]] TERA P/G Pla ane Impedance [Ω] Edge R Radiation (SA-P PPG) [dB Bm] 0 Terahertz Interconnection and Package Laboratory 2.5 Short Via3 14cm Terahertz Interconnection and Package Laboratory 21 Power/Ground Network Impedance plane cavity resonance modes 20l |ZPDN| 20log|Z (1,1) (1,0) Parallel circuit resonance ωLTotal_Loop2 ωLTotal_Loop3 20dB/dec lines TERA Terahertz Interconnection and Package Laboratory PKG-level PDN (1/4,0) -20dB/dec lines ωL LTotal_Loop1 (2,0) Chip-level PDN Cdecap2 Cdecap1 plane cavity resonance modes Series circuit resonance log f Terahertz Interconnection and Package Laboratory 22 Effect of On-chip PDN Design plane cavity resonance modes 20l |ZPDN| 20log|Z (1,1) (1,0) (2,0) On-chip Inductance (1/4,0) Chip-level PDN On-chip decap On-chip ESR TERA Terahertz Interconnection and Package Laboratory log f Terahertz Interconnection and Package Laboratory 23 On-chip PDN - Decoupling capacitors using oxide capacitance and MIM capacitance - Cost sensitive, die size - ESR considerations id ti needed d d - On-chip inductance dominant > 10GHz - On-chip PDN resonance > 10GHz - O hi PDN: On-chip PDN di directt radiated di t d coupling li source TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 24 Motivation –Cross-sectional View of Embedded Film Capacitor 1. Removal of SMD Passive Componen 1 (Enhanced Routibility) GND to Chip VDD to Chip Embedded Film Capacitor 3. Small Thickness (Low Inductance) High g Dielectric Material (High Capacitance) TERA Terahertz Interconnection and Package Laboratory 2. Short Via Length (Low Via Inductance) Terahertz Interconnection and Package Laboratory 25 25 Fabricated Test Vehicles (with Thin Film Embedded Capacitor) Vehicle Code Dielectric Thickness Dielectric Constant (DK) Capacitance/cm2 Total Capacitance (5cm x 5cm with 2 pairs) A 50 μm 4.6 81.46 pF 4.07 nF B 25 μm 4.6 162.91 pF 8.15 nF C 12 μm 4.6 339.40 pF 16.97 nF D 10 μm 16 1416.64 pF 70.83 nF E 10 μm 25 2213.50 pF 110.68 nF 50μm “A” with x50 TERA Terahertz Interconnection and Package Laboratory “A” with x100 “A” with x500 25μm “B” with x500 12μm “C” with x500 Terahertz Interconnection and Package Laboratory 26 Measured Impedance Curves (Discrete, Low DK “C” , High DK “E”) P Power/Gro ound Impedance [dB B ohm] 30 16 x 100nF Discrete Capacitors 20 With Thin Film Embedded Capacitor (Thickness : 12μm, DK : 4.6) – “C” 10 TM02/20 Mode Resonance (5cm x 5cm) With Thin Film Embedded Capacitor (Thickness : 10μm, DK : 25) – “E” 0 Significant Improvement over GHz With Thin Film Embedded Capacitor -10 -20 -30 -40 -50 Improvement at low frequency range with High-DK High DK Embedded Material 1 10 100 1000 3000 Frequency [MHz] Significant improvement over GHz with Thin Film Embedded Capacitor (Very low ESL of Embedded Capacitor) More improvement at low frequency range with high-DK embedded capacitor (More Capacitance) TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 27 Measured S M SSN [V] Measured SSN (No De-Cap. Vs. Discrete De-Cap.) No Decoupling Capacitor 3.5 Vp-p : 370.2 mV 3.3 3.1 Measureed SSN [V]] 0 4 8 12 Time [nsec] 16 x 100nF Discrete Capacitors 3.5 Vp-p : 123.8 mV 16 20 High-frequency harmonic was amplified with discrete capacitors 33 3.3 3.1 0 4 8 12 Time [nsec] 16 20 High frequency harmonic was amplified with discrete decoupling capacitors (as expected with impedance curve) TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 28 Measured S M SSN [V] Measured SSN (Discrete, Low DK “C” , High DK “E”) With Thin Film Embedded Capacitor (Thickness : 12μm, DK : 4.6) – “C” 3.5 3.3 Vp-p : 49.4 mV 3.1 0 Measureed SSN [V]] Low-Frequency Harmonic was appeared with Low DK Embedded Capacitor 4 8 12 Time [nsec] 16 20 With Thin Film Embedded Capacitor (Thickness : 10μm, DK : 25) – “E” 3.5 33 3.3 Vp-p : 10.6 mV 3.1 0 4 8 12 Time [nsec] 16 20 SSN was almost suppressed with High-DK thin film embedded capacitor TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 29 PDN Design Methods - Frequency dependent capacitance and inductance control - Increase of decoupling Capacitance depending frequency range (on-chip, on-package, on-PCB, lumped, embedded) - Decrease of Inductance (line, plane, via, wire, bonds, decoupling capacitors ) - Control resonances (lumped, planar cavity, on-chip, inter-level): avoid overlap with clock and harmonic frequencies - Control ESR to reduce peak resonance impedance - Evaluate dc ESR for dc voltage drop estimation TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 30 Proposed Modeling Method for Chip-Package-PCB Hierarchical PDN x f 4 Bond-wire y 1 Chip-level PDN 1 Chip-level PDN Bond-wire 4 8 2 Package-level Package le el PDN 7 Inter-level Coupling Ball 5 Fringing Field Fringing Field 8 2 9 Via 6 Power Ground Ball 9 3 PCB-level PDN Package-level P k l l PDN 7 Fringing Inter-level Field Coupling Segmentation S t ti Method 5 Vi Via 6 3 PCB-level PDN 9 Considering all parts in hierarchical PDN and merging them into one using segmentation method TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 31 Analysis of Impedance of Test Vehicle at Package Side PCB Mode (1 0)&(0 1) (1,0)&(0,1) Adjacent PKG&Chip Effect PKG Mode (1 0)&(0 1) (1,0)&(0,1) PCB Mode PCB Mode (2,0)&(0,2) (2,1)&(1,2) PKG Mode (2 1)&(1 2) (2,1)&(1,2) PKG Mode (1,1)&(1,1) Impeedance (ohhm) 100 PKG Mode (2,0)&(0,2) CPkg+CInt+CChip 10 Ck CPkg+CInt Pkg CPCB+CPkg+CInt+CChip 1 LChip+Bondwire LPkg+Via LPkg+Via+LInt//Ball LPCB+Via+L LPkg+Via+L LInt//Ball 0.1 0.1 1 10 20 Frequency (GHz) 9 A qu quite te complicated co p cated impedance peda ce characteristic c a acte st c composed co posed of o chip-package-PCB c p pac age C hierarchical PDN is fully analyzed. TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 32 Verification of Proposed Modeling Method (Corner on Chip) 1000 Chip (1,0)&(0,1) Measurement Proposed Model Chip Package PCB Impedanc ce (ohm) 100 CPkg+CInt+CChip CPkg+CChip LPkg+Via+Bondwire+LChip CChip 10 LChip LPkg+Via+Bondwire+LInt//Ball+LChip LPCB+Via+LPkg+Via+Bondwire+LInt//Ball+LChip 1 CPCB+C CPkg+C CInt+C CChip 0.1 0.1 1 10 20 Frequency (GHz) The impedances at corner probe pad on chip Frequency : 100MHz to 20GHz 5 high impedance peaks 4p peaks Æ interactions TERA Terahertz Interconnection and Package Laboratory 1 peak Æ mode resonance of chip Terahertz Interconnection and Package Laboratory 33 Need for Estimation of High Impedance Peak in Hierarchical PDN High Hi h impedances i d in i hi hierarchical hi l PDN ffrom iinteractions i generate problems bl off system performance f d degradation. d i Power/Ground Noise EMI current Impedan nce VSSN=ZPDN × ICircuit Signal Degradation Frequency RF Sensitivity RF /Analog Digital A precise simulation and analysis of hierarchical PDN is needed. TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 34 PDN Noise Coupling Paths in chip and package - Adjacent interconnections: line, pin, wire - p Via and planes - Conductive substrates - Common power line, plane - Common decoupling capacitors - Common return current paths - Isolation techniques needed: Cost, size increase TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 35 Frequency Spectrum of Digital Clock Waveforms f(x) Time TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 36 Waveform and Spectrum of Clock Signal 20 150 Fundamental : 200MHz 100MHz Odd harmonics Even harmonics 100 50 5ns10ns Powe er [dBm] Magnitude (mV) 0 0 -50 200MHz 100MHz -20 -40 -100 -60 -150 -200 200MHz 100MHz 0 5 10 Time (ns) TERA Terahertz Interconnection and Package Laboratory 15 20 -80 0 500 1000 1500 2000 2500 3000 Frequency [MHz] Terahertz Interconnection and Package Laboratory 37 Spectrum of Wireless Mobile Communication Systems WI-FI Bluetooth T-DMB TPMS GPS RF-ID AM FM 174~216MHz 1227.60MHz 1575.42MHz 535~1,705kHz S-DMB WiBro 2.3GHz 2.6GHz UWB UWB 3.1~4.8GHz 7.2~10.2GHz 주파수 2.4GHz 433.92MHz 88~108MHz 88 108MHz TERA Terahertz Interconnection and Package Laboratory 900MHz Terahertz Interconnection and Package Laboratory 38 Setup for Analysis Pulse Pattern Generator (PPG) Observation Factors : 1. Transfer Impedance ( 1 , 2 ) 2. Noise Coupling Ratio ( 1 , 3 ) 3 Output Waveform ( 3 ) 3. LO Signal • LO Frequency : 915.5MHz • LO Voltage : 400mV Pulse 이미지를 표시할 수 없습니다 . 컴퓨터 메모리가 부족하여 이미지를 열 수 없거나 이미지가 손상되었습니다 . 컴퓨터를 다시 시작한 후 파 일을 다시 여십시오 . 여전히 빨간색 x가 나타나면 이미지를 삭제한 다음 다시 삽입해야 합니다 . Port3 Port2 Output p Signal g Port1 • Frequency : 500kHz • Power : -2dBm • Voltage : 250mV • Voltage Gain : 12dB Signal Generator (SG) RF Signal • Frequency : 915MHz • Power : -14dBm 14 • Voltage : 60mV Sine Wave Balun DC 2.5V Combine r P/G Noise • Frequency : 40kHz , 150MHz, 900MHz • Voltage : 80mV Pulse TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 39/41 39 Basic Performance of Designed Mixer VDD Double Balanced Mixer Out- Out+ TSMC 0.25um Process Target Frequency : 860 ~ 960 MHz Gain : 10 ~ 12 dB LO + LO + P1dB : - 5dBm RF Isolation : -30dB LO - LO Isolation : -25dB RF+ Direct Conversion Frequency : 500kHz RF- TERA Terahertz Interconnection and Package Laboratory bias Terahertz Interconnection and Package Laboratory 40 On-chip Decap. Effect : Transfer Impedance ( Simulation ) Traansfer Imp pedance ( d dB ) Without On-Chip Decap. VS With On-Chip 30 (1,0) Decap. (λ/4) 900MHz (0,1) 20 10 0 -10 -20 -30 -40 10M ((1,1) , ) Wirebond+ On-chip Decap. Capacitance On-chip Decap Effect (112pF). Without On-chip decap. With On-chip decap. 100M 1G Frequency ( Hz ) • When on-chip decoupling capacitor is designed , transfer impedance decreases more than the case without on-chip decoupling capacitor over 600MHz s e impedance ped ce decreases dec e ses when w e design des g on-chip o c p decoup decouplingg capacitor c p c o in 900MHz. 900 . - > Transfer TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 41 On-chip Decap. Effect : Output Spectrum (Measurement) Spectrum Spectrum ( Scaled Up ) -40 Without Decap. With Decap. Power ( dB P Bm ) Power ( dB P Bm ) 0 -20 -40 -60 60 -80 0 0.5 1 1.5 Frequency ( GHz ) 2 Without Decap. With Decap. -60 ( 900MHz, -51dBm) 13 5B 13.5B ( 900MHz, -64.5dBm) -80 -100 890 895 900 905 Frequency ( MHz ) 910 • Switching noise of output waveform with on-chip decoupling capacitor decreases in 13.5dB a frequency of 900MHz compared to the case without on on-chip chip decoupling capacitor . -> Verified effect of design on-chip decoupling capacitor in RF or LO frequency band. TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 42 Off-chip Decap. Effect : Transfer Impedance (Simulation) Traansfer Imp pedance ( d dB ) Without Off-Chip Decap. VS With Off-Chip Decap. 30 Off-chip p Decap. p Effect 20 10 0 150MHz Off-Chip Capacitor : L1= 540pH , C1=101nF , R1 =17mΩ -10 -20 -30 10k Inductance Capacitance Without Off-chip decap. With Off-chip decap. 100k 1M 10M 100M 1G Frequency ( Hz ) • When additional off-chip decoupling capacitor is designed , transfer impedance decreases more than the case without additional off-chip decoupling capacitor from 2MHz to 200MHz - > Transfer impedance decreases when design on-chip decoupling capacitor in 150MHz. TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 43 Off-chip Decap. Effect : Output Spectrum ( Measurement ) Spectrum p Spectrum p ( Scaled Up p) ( 150MHz, -44.5dBm) -50-50 Without Decap. Without Decap. With Decap. With Decap. ( 150MHz, -56.7dBm) -60 -60 -70 70 -70 -80 -80 00 100 100M 200200M 300 300M 400 400M Frequency eque cy ( MHz ) 500 500M -40 Without Decap. With Decap. ( 150MHz, -44.5dBm) Power ( dB P Bm ) Po ower ( dBm m) -40-40 -50 12.2dB ( 150MHz, -56.7dBm) -60 -70 -80 100 120 140 160 180 Frequency q y ( MHz ) 200 • Switching noise of output waveform with off-chip decoupling capacitor decreases in 12.2dB a frequency of 150MHz compared to the case without off off-chip chip decoupling capacitor . -> Verified effect of design off-chip decoupling capacitor in IF frequency band. TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 44 Problem by Power and Ground Noise DAC Digital RF & Analog BPF PA PLL ADC LNA LNA Key circuit Unwanted DC Offset OPamp TERA Terahertz Interconnection and Package Laboratory System Failure!! Terahertz Interconnection and Package Laboratory 45 45 DC Output Offset with Proposed and Conventional Analysis DC Output Offset with Proposed Analysis Digital P 100mV Bonding Wire Package PDN _ Chip PDN DC Output Offset with Conventional Analysis 100mV 100mV Digital P OP amp P _ + + G G OP amp P G G 60 DC Output Offset (mV) Conventional analysis Proposed analysis 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Frequency (GHz) TERA Terahertz Interconnection and Package Laboratory Considerable C id bl Di Distinction i i b between DC O Output Off Offset with and without Consideration of PDN Terahertz Interconnection and Package Laboratory 46 SSN Sensitive Circuits in IC - VCO: Voltage Controlled Oscillator - LNA: Low Noise Amplifier - PLL Ph PLL: Phase L Locked k dL Loop - ADC: Analog to Digital Converter - DAC: Digital to Analog Converter TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 47 SSN Isolation Methods - Decoupling - Filtering - Slot - Split - Shielding - EBG strictures - Separated power supply/decoupling/return current path - Separated interconnections: lines, pins, pads, vias - Separated planes, layers - Increased separation distance TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 48 PDN Noise Isolation Methods Digital PDN Analog/RF PDN ip Ch ge ka c Pa A B PC B A - Chip p Level Split On-chip Metal PDN Bus Guard Ring (P+/ N+/ Deep-Nwell type) On-chip Decoupling Capacitor Internal Voltage Regulator Package/PCB g Level - Split Power/Ground Planes - On-Package/PCB Decoupling Capacitor (Discrete type, Embedded type) - Electromagnetic Band Gap (EBG) B Æ Frequency dependency of noise isolation Æ Z21 analysis l i in i the th frequency f domain d i TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 49 104 Merged PCB PDN/Merged Package PDN Split PCB PDN/Split Package PDN Split PCB PDN/Split Package PDN+off-chip PDN+off chip decap. decap Split PCB PDN/Split Package PDN+off-chip decap.+on-chip decap. 102 o on-chip decap. d 1 By Split Transfer IImpedance [Ω] The isolation methods of each hierarchical PDN off-chip p decap. 10-2 10-41M 10M 100M 1G 3G Frequency [Hz] TERA • By split of PCB and package level PDN, the PDN transfer impedance can be suppressed except around 10MHz. • By adding on-/off-chip decoupling capacitor, capacitor the PDN transfer impedance can be suppressed in both low and high frequency region. Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 50 Stack-up for Transceiver SiP [ 7 layer] • Thickness = 1.3 mm, Size: 20mmx20mm, • Ceramic: Dupont (Dielectric Constant = 7.4, Loss Tangent = 0.001) • Die: 7, Decap: 5 개, Ball: 287, Wire-bonding: 53 개 • 7 Layers Heat Sink 600 um Short-wire 500 um Die 200 um Signal/Filter Lines 100 um Chip Pads Ground Plane 100 um EBG1 100 um EBG2 100 um Power Plane 200 um BGA TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 51 Transceiver without DS-EBG -12.17 12 17 dB dBm at 9 GHz -12.33 12 33 dB dBm at 9GHz -43 dBm at 8.999997 8 999997 GH GHz < Without Power/Ground Noise > < With Power/Ground Noise > Power/Ground Po er/Gro nd noise generates a -43 43 dBm of unwanted n anted signal near the output signal. TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 52 Transceiver with DS-EBG -12.33 12 33 dB dBm at 9GHz -12.17 12 17 dB dBm at 9 GHz 21 dB Suppression < Without Power/Ground Noise > -64 dBm at 8.999997 GHz < With Power/Ground Noise > DS-EBG DS EBG successfully s ccessf ll suppresses s ppresses the unwanted n anted signal by b 21 dB. TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 53 Proposed On-Interposer EBG Structure Capacitive P/G mesh Width: 80um S W Space: 120um Inductive P/G mesh W Width: 40um Space: 360um S TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 54 Measurement Results (1/2) 0 Coupling Coeffficients, S21 (dB) -10 TV A (Mesh) TV B (EBG) Mesh PDN -20 -30 30 Stopband -40 -50 -60 -70 Interposer EBG -80 -90 TERA Terahertz Interconnection and Package Laboratory 0 2 4 6 8 10 12 14 Frequency (GHz) 16 18 20 Terahertz Interconnection and Package Laboratory 55 Measurement Results (2/2) - Switching noise input at port 1 using 500mVpp clock signal - Coupled C l d noise i spectrum t probed b d att portt 2 -10 -20 500MHz TV A (M (Mesh) h) TV B (EBG) Coupleed Noise Spectru um (dBm) Coupleed Noise Spectru um (dBm) -10 -30 -40 -50 -60 -70 0 2 TERA Terahertz Interconnection and Package Laboratory 4 6 8 10 12 14 Frequency (GHz) 16 18 20 -20 1GHz TV A (M (Mesh) h) TV B (EBG) -30 -40 -50 -60 -70 0 2 4 6 8 10 12 14 Frequency (GHz) 16 18 Terahertz Interconnection and Package Laboratory 20 56 Proposed 3D Clock Distribution Scheme 3-D Stacked Chip Star-wiring I/O Clock Distribution for Low Jitter, Skew, and Delay Î lossless of bonding-wire & pad Î free from on both on chip and package power supply noise Clock Distribution Path using Bonding Wire DLL Output Driver DLL Replica Path Star-wiring DLL Stacked Chip I/O Buffer DLL Chip Ball Grid Array Package TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 57 Enhanced Clock Jitter Performance of the Proposed Scheme Conventional On-chip I/O Clock Distribution Scheme • Peak-to-Peak Jitter : 146ps p RMS Jitter : 22ps 500MHz Clock Voltage [3 300mV/div] Voltage [3 300mV/div] 500MHz Clock 3D Stacked Chip Star-wiring I/O Clock Distribution Scheme • Peak-to-Peak Jitter : 34ps RMS Jitter : 5ps Time[100ps/div] Time[100ps/div] 9 3D-stacked chip star-wiring clock scheme provides low clock jitter compared with on-chip clock scheme (77% jitter reduction) 9 It is devised to enable the clock signal delivery to be free from on on-chip chip digital switching noise and package power/ground cavity noise coupling. TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 58 Advantages of Proposed PCR CDN for 3D Stacked Chip Package Clock path Clock F/F DLL Wire-bond as an inductive termination HRM Synchronous digital chip Data I/O Jitter is filtered Quarterwavelength resonator LTCC interposer Package sub. Package-level implementation planar cavity y resonator ((not g grid connected)) One p • • Package ball Jitter is filtered by high-Q bandpass filter utilizing a package level quarter-wavelength planar cavity resonator Reduction of the number of cascaded repeaters TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 59 59 Originalities of Proposed PCR CDN for 3D Stacked Chip Package Standing wave Planar cavity voltage amplitudes (V) Wire-bond as an inductive termination I/O buffer I/O buffer Min. Max. • Uniform phase and uniform amplitude standing wave is used for clock distribution TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 60 60 Quarter-wavelength Resonator with Inductive Termination open open Inductive termination open Incident wave Voltage Voltage l λ/2 open λ/4 short Voltage λ/4 TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 61 61 Measure Eyd-diagram of PCR CDN with Noise Distrbuted clock at planar cavity resonator output Clock source before distribution 12 1.2 12 1.2 Voltage (V) Voltage (V) Pk-to-pk jitter = 98 ps Eye-opening = 920mV 0 -1.2 Pk-to-pk jitter = 28 ps Eye-opening = 1720mV 0 -1.2 0 100 200 Time (p (psec)) 300 400 Source clock Distrbuted clock Pk-to-pk jitter 98 ps 28 ps Eye-opening 920 mV 1720 mV TERA Terahertz Interconnection and Package Laboratory 0 100 200 Time (p (psec)) 300 400 Clock frequnecy : 1.55 GHz • Clock magnitude : 1 Vp-p • Switching noise : 300 mV • Terahertz Interconnection and Package Laboratory 62 62 Unique Research Focus High-performance Mixed Mode System System on Chip (On Chip Level) (On-Chip System y in Package g (On-Package Level) Module, PCB, Cabling (System Level) Signal Integrity Co-Design Low Noise and High-Integration Design P Power Integrity I t it Electromagnetic I t f Interference Improvement of Reliability, Reliability Performance, Performance Design Cycle, Cycle Cost TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 63 Conclusion - - - Significant noise coupling occurs from digital PDN to noise sensitive RF and analog circuits on a same SiP. The clock frequencies and harmonic frequencies should be placed away from the RF carrier frequencies. Low PDN impedance should be maintained. PDN resonance frequencies should be placed away not only from the clock frequencies, and their harmonic frequencies, but also from RF carrier frequencies. q Via and wire are a major noise coupling path from digital PDN to noise sensitive circuits. Noise coupling reduction methods including using PDN design design, frequency control, filtering, separation/isolation, decoupling, shielding, and grounding techniques. Case studies: LNA, Clock distribution network Chip-package co-design can provide optimal and cost-effective solutions solutions. TERA Terahertz Interconnection and Package Laboratory Terahertz Interconnection and Package Laboratory 64
