Viking Marketing March 2012
Viking Technology’s
BGA Stacking Technology
Review
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Abstract
The design of memory subsystems has become more complex as the need for higher
speeds & DRAM densities continue to increase with an on-going requirement for smaller
memory module form factors. Small memory module form factors such as SO-DIMMs, MiniDIMMs, and Very Low Profile (VLP) DIMM’s generally use specialized DRAM packaging
technologies to achieve high density solutions.
This technology review document has been prepared to provide OEM system designers with
information of Viking Technology’s approach to high density DRAM modules by using an inhouse developed BGA stacking technology. This data will be useful for system designers;
providing a technical comparison between BGA Stacking & DDP (Dual-Die Packaged DRAM)
in order to maximize the performance/cost benefits of using high density, BGA stacked Viking
DRAM modules.
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Table of Contents
1
INTRODUCTION
6
1.1
BGA Stacking Features and Benefits
6
1.2
Why DDP’s are expensive
6
1.3
Why monolithic / single die 4Gb DRAM is expensive
7
BGA STACKING DESIGN AND FABRICATION
8
2
2.1
3
3.1
Mechanical Description of BGA Stack
BGA STACKING QUALIFICATION PLAN
Simulation
8
10
10
3.2
BGA Stacking Signal Integrity
3.2.1 Signal Integrity Analysis
3.2.2 Post Register Timings
3.2.3 Clock Timings
3.2.4 Write Timings
11
11
12
20
21
3.3
BGA Stack Mechanical Reliability and Structural Integrity
3.3.1 Extended Thermal Cycle
3.3.2 Shock and Vibration
30
31
34
3.4
BGA Stack Electrical Reliability and Thermal Analysis
3.4.1 Temperature Testing the BGA Stack while under power
3.4.2 Temperature rise of DDP’s compared to BGA Stacking
35
35
38
4
MEMORY MODULE ENHANCEMENTS
39
5
SYSTEM DESIGN RECOMMENDATIONS
39
5.1
Air Flow Recommendations
5.1.1 Air Flow for Commercial Temperature Operation (0 to 70ºC)
5.1.2 Air Flow for Industrial Temperature Operation (-40 to 85ºC)
40
40
40
5.2
Ideas on Cooling By Airflow
5.2.1 Memory Module Placement in the System
5.2.2 DIMM Socket Selection and Orientation
5.2.3 Air gaps for DIMM Sockets
5.2.4 Increase Air Flow Pressure
41
41
41
41
42
6
CONCLUSION
42
7
REFERENCE AND ADDITIONAL INFORMATION
42
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Table of Tables
Table 3-1: CS0/GND: Single-ended Signals and Timing__________________________________________
Table 3-2: #RAS/GND: Single-ended Signals and Timing ________________________________________
Table 3-3: A3: Single-ended Signals and Timing _______________________________________________
Table 3-4: CLK/#CLK@ U19 DDR3 SDRAM Stacked BGA Frame _________________________________
Table 3-5: CLK3/GND and #CLK3/GND @ U19 Stacked BGA Frame _______________________________
Table 3-6: Write Cycle: DQS0/GND & #DQS0/GND @ U19 Stacked BGA Frame ______________________
Table 3-7: Write Cycle: DQS0/#DQS0 and DQ2 @ U19 Stacked BGA Frame _________________________
Table 3-8: Shock and Vibration Specifications _________________________________________________
Table 3-9: Samsung 2Gbit x4 devices (PN K4B2G0446B HCH9) DDR3-1333 DRAM ___________________
Table 3-10: Micron DDR3 DDP Thermal Chart _________________________________________________
Table 5-1: Maximum DRAM Case Temperature ________________________________________________
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12
13
13
20
21
21
22
34
37
38
39
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Table of Figures
Figure 1-1: Cost of High Density Single Die Monolithic DRAM vs BGA Stacked solution__________________ 7
Figure 2-1: Cross-Section View and Dimensions of BGA Stacked Module_____________________________ 8
Figure 2-2: Top View and Dimensions of BGA Stack Cell__________________________________________ 8
Figure 2-3: Side View of BGA Stacked DDR3 VLP RDIMM ________________________________________ 9
Figure 2-4: Top view of BGA Stacked DDR3 VLP RDIMM _________________________________________ 9
Figure 3-1: 8G VLP RDIMM, DDR3-1333, Viking PN: VR7VA1G7254GHDSBT1 ______________________ 11
Figure 3-2: CH1=CLK3_CH2=#CS0_CH3=#RAS_CH4=A3_AC timing ______________________________ 14
Figure 3-3: CH1=CLK3_CH2=#CS0_AC timing ________________________________________________ 14
Figure 3-4: CH1=CLK3_CH2=#CS0_#CS0_Vmax=1.576V_Vmin=53mV ____________________________ 15
Figure 3-5: CH1=CLK3_CH2=#CS0_#CS0_setup=655ps ________________________________________ 15
Figure 3-6: CH1=CLK3_CH2=#CS0_#CS0_hold=711ps _________________________________________ 16
Figure 3-7: CH1=CLK3_CH2=#CS0_CH3=#RAS_setup=1.044ns __________________________________ 16
Figure 3-8: CH1=CLK3_CH2=#CS0_CH3=#RAS_hold=1.556ns ___________________________________ 17
Figure 3-9: CH1=CLK3_CH2=#CS0_CH3=#RAS_AC limit________________________________________ 17
Figure 3-10: CH1=CLK3_CH2=#CS0_CH4=A3_AC limit _________________________________________ 18
Figure 3-11: CH1=CLK3_CH2=#CS0_CH4=A3_setup=1.156ns ___________________________________ 18
Figure 3-12: CH1=CLK3_CH2=#CS0_CH4=A3_hold=1.578ns ____________________________________ 19
Figure 3-13: CH1=CLK3_CH2=DQS0_CH3=DQ2_AC limit _______________________________________ 23
Figure 3-14: CH1=CLK3_CH2=DQS0_CH3=DQ2_DQ2 Vmax=1.124V_Vmin=365mV __________________ 23
Figure 3-15: CH1=CLK3_CH2=DQS0_CH3=DQ2_tDQSS=-44ps __________________________________ 24
Figure 3-16: CH1=CLK3_CH2=DQS0_CH3=DQ2_tDSH=678ps ___________________________________ 24
Figure 3-17: CH1=CLK3_CH2=DQS0_CH3=DQ2_tDQSS=-44ps __________________________________ 25
Figure 3-18: CH1=CLK3_CH2=DQS0_CH3=DQ2_tDSH=678ps ___________________________________ 25
Figure 3-19: CH1=CLK3_CH2=DQS0_CH3=DQ2_tWPRE=1.767ns ________________________________ 26
Figure 3-20: CH1=CLK3_CH2=DQS0_CH3=DQ2_tDQSH=722ps __________________________________ 26
Figure 3-21: CH1=CLK3_CH2=DQS0_CH3=DQ2_tDQSL=778ps __________________________________ 27
Figure 3-22: CH1=CLK3_CH2=DQS0_CH3=DQ2_tDS=244ps ____________________________________ 27
Figure 3-23: CH1=CLK3_CH2=DQS0_CH3=DQ2_tDH=356ps ____________________________________ 28
Figure 3-24: CH1=CLK3_CH2=DQS0_CH3=DQ2_tDS=200ps ____________________________________ 28
Figure 3-25: CH1=CLK3_CH2=DQS0_CH3=DQ2_tDH=722ps ____________________________________ 29
Figure 3-26: CH1=CLK3_CH2=DQS0_CH3=DQ2_tWPST=622ps __________________________________ 29
Figure 3-27: CH1=CLK3_CH2=DQS0_CH3=DQ2_AC limit _______________________________________ 30
Figure 3-28: Dye and Pry on an 8GB VLP RDIMM ______________________________________________ 32
Figure 3-29: Dye and Pry on an 8GB VLP RDIMM ______________________________________________ 32
Figure 3-30: Removal of top BGA from BGA Stack______________________________________________ 33
Figure 3-31: Removal of top BGA from BGA Stack______________________________________________ 33
Figure 3-32: Thermocouple locations on an 8GB VLP RDIMM, DDR3-1333 __________________________ 35
Figure 3-33: Temperature rise for Samsung DDR3-1333 DRAM inside BGA Stack _____________________ 36
Figure 5-1: Air Flow for Commercial Temperature Operation (0 to 70ºC) _____________________________ 40
Figure 5-2: Air Flow for Industrial Temperature Operation (-40 to 85ºC)______________________________ 40
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1 Introduction
1.1 BGA Stacking Features and Benefits
High density small form factor DRAM memory modules using BGA stacking technology
provide the following features and benefits:
 Lower cost modules compared to those assembled using costly DDP’s or
high density single die monolithic (i.e. 4Gb DDR3) DRAM. BGA stacked memory
modules use mainstream, readily available DRAM with an inherent lower cost per bit.
 Shorter lead times. The process and equipment for soldering a BGA stack is the same
as soldering a single BGA device.
 No stacking compound yield loss. Viking’s BGA stacking solution does not result in
compound yield manufacturing problems.
 Reliable and consistent quality. All solder joints are accessible for inspection and
meet IPC-A-610C under Viking & Sanmina-SCI quality control
 BGA stacking offers flexibility in the DRAM supply chain, with multiple DRAM vendor
choices
 BGA stacked modules are also available as Industrial Temperature: -40 to +85ºC
 BGA stacks on a VLP DIMM will fit into standard 10mm DIMM socket spacing (JEDEC
Max 7.55mm Module thickness)
 Low voltage options are available: 1.5V and 1.35 V (1.25V when JEDEC approved)
 Robust design attributes that provide guardband margin for environmental operating
conditions and timing variations on different motherboards/servers
 Electrical, thermal and reliability characteristics comparable to DDP solutions
1.2 Why DDP’s are expensive
DDP’s are costly due to fabrication problems. Current wire-bonded die stacking technology is
a process that has never been able to transition economically into high volume production.
The process of wire bonding die into stacks requires expensive equipment, is time
consuming and is prone to poor manufacturing yields. This has resulted in a limited
availability of DDP’s and at high prices. Additionally, wire-bonded DDP have less than
optimal signal integrity characteristics because the wire-bonds are not impedance controlled
and this causes packaging parasitic’s that can impact signal quality.
The newer “Through Silicon Via” (TSV) die stacking technologies will have similar fabrication
issues. There is a high capital equipment cost, a slow etch rate of silicon that curtails
throughput and a complexity of additional process steps to create conductive via’s that are
insulated from the silicon through which they pass.
DDP’s using TSV also have issues of reliability that have not yet been satisfactorily solved.
The points of weaknesses in the design include the dielectric and conductive coating of the
side walls of a high aspect ratio pipe and the 90 degree bends at the top and base of the
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pipe that the redistribution layer (RDL) must traverse and maintain connectivity during
thermal cycling. A further consideration is that because the TSV’s extend through the entire
thickness of the silicon it is impossible to place any semiconductor circuitry in the region of
the bond pads. A decrease in silicon utilization results in an increase in die size which is
unfavorable influence to the DDP component price.
Even if the problems of TSV formation are satisfactorily addressed, die stacking is not a
trivial problem. Large arrays of lands have to be reliably joined. Some of the techniques
recommended for this process include stud bumps in combination with conductive adhesives,
solid state diffusion bonding of metals and soldering. While all of these possibilities are
technically tractable, like TSV’s, making large numbers of high yielding and reliable joints
between die, in volume, at an affordable price, has yet to be satisfactorily addressed at both
the die and wafer level.
1.3 Why monolithic / single die 4Gb DRAM is expensive
There are several reasons why the price of a single die high-density monolithic DRAM chips
may cost more than an equivalent density using two DRAM memory chips. The more notable
reasons being:
1) The cost premiums associated with early introduction of any new DRAM density
2) DRAM die shrink efficiencies may not be available yet to lower cost
3) High density chips may not be in volume production as a “mainstream” DRAM
These reasons indicate a price/time relationship that may last for a certain period of time
which is illustrated in the figure below.
Figure 1-1: Cost of High Density Single Die Monolithic DRAM vs BGA Stacked solution
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BGA stacking is more economical than high density monolithic DRAM when the cost of the
two lower density DRAMs (plus stacking cost) is lower than the cost of the single die
monolithic chip. However, if a price cross-over point is reached, it would be time to upgrade
to the higher density DRAM (4Gb price cross-over not expected until late 2012 / 2013).
2 BGA Stacking Design and Fabrication
2.1 Mechanical Description of BGA Stack
Viking’s BGA stacking technique is a packaging method that mounts a BGA chip over
another BGA chip that has already been soldered to the memory DIMM PCB. The BGA
stacking technique does not require an interposer PCB to join the memory devices
electrically or mechanically together into a single standalone stacked component. The Viking
BGA stack comprises of an FR4 PCB (with cavity) that fits over the other BGA. The stacking
PCB creates a vertical riser that makes electrical connections from the BGA mounted on top
of the stacking PCB to the memory DIMM PCB as shown in the following figures.
Figure 2-1: Cross-Section View and Dimensions of BGA Stacked Module
4 Layer FR4 Stacking PCB
Solder Bump
BGA
3.19 mm
BGA
Figure 2-2: Top View and Dimensions of BGA Stack Cell
Current Stacking PCB dimensions established to support a wide variety of DRAM package dimensions
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Figure 2-3: Side View of BGA Stacked DDR3 VLP RDIMM
Figure 2-4: Top view of BGA Stacked DDR3 VLP RDIMM
Viking has developed a stacking method using a 4-layer FR4 controlled impedance stacking
PCB that has power and ground plane layers that have the added benefit of distributing heat.
This will maximize signal integrity characteristics and thermal response to produce a BGA
stack that is functional over the full range of signal clocking speeds (i.e. DDR3). The use of
FR4 was chosen as the PCB material to match the thermal coefficient of expansion to the
DIMM PCB and to provide dielectric properties that resemble the memory DIMM PCB.
The use of FR4 PCB material in the BGA stack also improves manufacturability by using the
same BGA soldering process and equipment as the other components on the memory
module in a high volume production environment. The design of the pad sizes and solder
contact areas were designed to meet IPC-A-600, IPC-6012 and IPC-A-610C requirements
and to withstand shock, vibration and thermal cycling. The stacking PCB’s are made in
panels containing differential impedance coupons that ensure the quality of the signal
integrity aspects of the stack.
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Viking memory modules with BGA stacking use only the highest-grade, fully tested memory
components from leading Tier 1 DRAM vendors. Viking can also support memory modules
with BGA stacking that are intended for high temperature and industrial temperature
environments
3 BGA Stacking Qualification Plan
The qualification plan for the Viking BGA stack encompasses the following areas:
SIMULATON
 Electrical
– .EBD simulation model
 Mechanical
– IGES 3D mechanical model
 Thermal
– Thermal characterization lab report
– Ambient temp vs. Airflow solution space graph
LAB TESTING and Design Validation Testing (DVT)
 Electrical
– Signal Integrity Testing
– DDR3 JEDEC Compliance Testing
 Mechanical Reliability and Structural Integrity Testing
– JESD22-A104-B
 Electrical Reliability and Thermal testing
– Accelerated thermal cycle report
The test vehicle for the Viking BGA Stack was a DDR3-1333, 8GB 2 Rank x4 VLP RDIMM.
Viking module P/N: VR7VA1G7254GHDSBT1 with a Vdd of 1.5v.
3.1 Simulation
IBIS models were used to model different types of stacks at various speeds. Analysis has
shown that cross-talk is minimal and that the frequency response is similar to that of a single
memory device on a 2 rank planar non-stacked PCB.
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3.2 BGA Stacking Signal Integrity
3.2.1 Signal Integrity Analysis
The primary test instrument used was an Agilent Technologies Infiniium (Model Number:
DSO91204A, SW Version, 02.10.0004, Application SW Version 1.40)
In summary, solid timing margins were observed at DDR3-1333 in a standard DDR3 Intel
server motherboard (Model # S5520HC) at 25ºC.
 Signal integrity equivalent to standard planar 2R DIMM
 +/-10% Vref and Vtt Margins In System Without Error (Vdd = 1.5v)
The BGA stacks passed DDR3 JEDEC Compliance Testing with significant guardband
margin to datasheet specifications for the control, address and data lines.
 Guardband margin was measured to the following JEDEC specifications:
JEDEC Std. # 79-3C: Table 24, 25, 29, 37, 38, 63, 65
The figure below is the layout of the 8GB VLP RDIMM, 2 Rank (x4) DDR3-1333, (Viking
module P/N VR7VA1G7254GHDSBT1 showing the location of the 18 BGA stacks. There are
36 Samsung 2Gbit, 512Mx4 DRAM devices (PN K4B2G0446B-HCH9). Note that DRAM U#
reference designators shown on the module in the following drawing are attached directly to
the DIMM PCB. The U-numbers shown above the module are the DRAM BGA’s mounted on
top of the BGA stack.
Figure 3-1: 8G VLP RDIMM, DDR3-1333, Viking PN: VR7VA1G7254GHDSBT1
U19
U20
U21
U22
U27
U1
U2
U3
U4
U9
U37
U23
U24
U25
U26
U5
U6
U7
U8
Note: U#’s shown above the image are the BGA’s on top of the BGA stack.
U35
U34
U33
U32
U36
U31
U30
U29
U28
U17
U16
U15
U14
U18
U13
U12
U11
U10
Note: U#’s shown above the image are the BGA’s on top of the BGA stack.
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3.2.2 Post Register Timings
This section summarizes the JEDEC compliance testing on Single-ended Signals and Timing
for CS0, #RAS and A3. Scope shots are shown in the figures following the tables.
3.2.2.1 CS0/GND: Single-ended Signals and Timing
Chip Select 0 (CS0) passed JEDEC compliance testing with the guardband margin results
shown in the following table.
Table 3-1: CS0/GND: Single-ended Signals and Timing
Test
1
2
3
4
5
6
7
8
9
10
Notes:
1)
2)
3)
4)
5)
6)
Test Name
VIH.CA(AC)
VIH.CA(DC)
VIL.CA(AC)
VIL.CA(DC)
Overshoot amplitude (Address, Control)
Overshoot area (Address, Control)
Undershoot amplitude (Address, Control)
Undershoot area (Address, Control)
tIS(base)
tIH(base)
Actual Value
1.260000V
1.260000V
375.0000mV
41.00000mV
-26.00000mV
0.000000V-ns
78.00000mV
0.000000V-ns
640.1ps
687.3ps
Guardband
Margin
36.20%
36.90%
34.80%
6.30%
106.50%
100.00%
119.50%
100.00%
884.80%
390.90%
Spec Range
VALUE >= 925.0000mV
850.0000mV <= VALUE <= 1.500000V
VALUE <= 575.0000mV
0.000000V <= VALUE <= 650.0000mV
VALUE <= 400.0000mV
VALUE <= 400.0000mV-ns
VALUE >= -400.0000mV
VALUE <= 400.0000mV-ns
VALUE >= 65.0ps
VALUE >= 140.0ps
JEDEC Std. # 79-3C, Table 24 (Vref=0.75)
JEDEC Std. # 79-3C, Table 24 (Vref=0.75; VDD=1.50)
JEDEC Std. # 79-3C, Table 24 (Vref=0.75)
JEDEC Std. # 79-3C, Table 24 (Vref=0.75; VSS=0.00)
JEDEC Std. # 79-3C, Table 37
JEDEC Std. # 79-3C, Table 65
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Note
1
2
3
4
5
5
5
5
6
6
Viking Marketing March 2012
3.2.2.2 #RAS/GND: Single-ended Signals and Timing
#RAS passed JEDEC compliance testing with the guardband margin results shown in the
following table.
Table 3-2: #RAS/GND: Single-ended Signals and Timing
Guardband
Margin
Test
Test Name
Actual Value
Spec Range
1
VIH.CA(AC)
1.108000V
19.80%
VALUE >= 925.0000mV
1
2
VIH.CA(DC)
1.111000V
40.20%
850.0000mV <= VALUE <= 1.500000V
2
3
VIL.CA(AC)
365.0000mV
36.50%
VALUE <= 575.0000mV
3
4
VIL.CA(DC)
357.0000mV
45.10%
0.000000V <= VALUE <= 650.0000mV
4
5
Overshoot amplitude (Address, Control)
-350.0000mV
187.50%
VALUE <= 400.0000mV
5
6
Overshoot area (Address, Control)
0.000000V-ns
100.00%
VALUE <= 400.0000mV-ns
5
7
Undershoot amplitude (Address, Control)
318.0000mV
179.50%
VALUE >= -400.0000mV
5
8
Undershoot area (Address, Control)
0.000000V-ns
100.00%
VALUE <= 400.0000mV-ns
5
9
tIS(base)
783.2ps
VALUE >= 65.0ps
6
VALUE >= 140.0ps
6
1100.00%
10
tIH(base)
221.1ps
Notes:
1)
JEDEC Std. # 79-3C, Table 24 (Vref=0.75)
2)
JEDEC Std. # 79-3C, Table 24 (Vref=0.75; VDD=1.50)
3)
JEDEC Std. # 79-3C, Table 24 (Vref=0.75)
4)
JEDEC Std. # 79-3C, Table 24 (Vref=0.75; VSS=0.00)
5)
JEDEC Std. # 79-3C, Table 37
6)
JEDEC Std. # 79-3C, Table 65
57.90%
Note
3.2.2.3 A3/GND: Single-ended Signals and Timing
Address Line 3 (A3) passed JEDEC compliance testing with the guardband margin results
shown in the following table.
Table 3-3: A3: Single-ended Signals and Timing
Test
Test Name
Actual Value
1
VIH.CA(AC)
1.139000V
23.10%
VALUE >= 925.0000mV
2
VIH.CA(DC)
1.139000V
44.50%
850.0000mV <= VALUE <= 1.500000V
3
VIL.CA(AC)
392.0000mV
31.80%
VALUE <= 575.0000mV
4
VIL.CA(DC)
386.0000mV
40.60%
0.000000V <= VALUE <= 650.0000mV
5
tIS(base)
721.0ps
1010.00%
261.0ps
86.40%
6
tIH(base)
Notes:
1)
JEDEC Std. # 79-3C, Table 24 (Vref=0.75)
Margin
Spec Range
VALUE >= 65.0ps
VALUE >= 140.0ps
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Figure 3-2: CH1=CLK3_CH2=#CS0_CH3=#RAS_CH4=A3_AC timing
Figure 3-3: CH1=CLK3_CH2=#CS0_AC timing
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Figure 3-4: CH1=CLK3_CH2=#CS0_#CS0_Vmax=1.576V_Vmin=53mV
Figure 3-5: CH1=CLK3_CH2=#CS0_#CS0_setup=655ps
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Figure 3-6: CH1=CLK3_CH2=#CS0_#CS0_hold=711ps
Figure 3-7: CH1=CLK3_CH2=#CS0_CH3=#RAS_setup=1.044ns
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Figure 3-8: CH1=CLK3_CH2=#CS0_CH3=#RAS_hold=1.556ns
Figure 3-9: CH1=CLK3_CH2=#CS0_CH3=#RAS_AC limit
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Figure 3-10: CH1=CLK3_CH2=#CS0_CH4=A3_AC limit
Figure 3-11: CH1=CLK3_CH2=#CS0_CH4=A3_setup=1.156ns
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Figure 3-12: CH1=CLK3_CH2=#CS0_CH4=A3_hold=1.578ns
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3.2.3
Clock Timings
This section summarizes the JEDEC compliance testing on Clock.
3.2.3.1 Clock: CLK3/#CLK3 @ U19 DDR3 SDRAM Stacked BGA Frame
Table 3-4: CLK/#CLK@ U19 DDR3 SDRAM Stacked BGA Frame
Test
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Test Name
tjit(CC) Rising Edge
Measurements
tCK(avg) Rising Edge
Measurements
tjit(per) Rising Edge
Measurements
terr(2per) Rising Edge
Measurements
terr(3per) Rising Edge
Measurements
terr(4per) Rising Edge
Measurements
terr(5per) Rising Edge
Measurements
terr(6per) Rising Edge
Measurements
terr(7per) Rising Edge
Measurements
terr(8per) Rising Edge
Measurements
terr(9per) Rising Edge
Measurements
terr(10per) Rising Edge
Measurements
terr(11per) Rising Edge
Measurements
terr(12per) Rising Edge
Measurements
terr(nper) Rising Edge
Measurements
Actual Value
85ps
1.500ns
Guardband
Margin
23.40%
0.00%
Spec Range
Note
-160ps <= VALUE <= 160ps
1
1.500ns <= VALUE <= 1.875ns
2
52ps
17.50%
-80ps <= VALUE <= 80ps
1
-58ps
25.40%
-118ps <= VALUE <= 118ps
1
-58ps
29.30%
-140ps <= VALUE <= 140ps
1
-57ps
31.60%
-155ps <= VALUE <= 155ps
1
57ps
33.00%
-168ps <= VALUE <= 168ps
1
-67ps
31.10%
-177ps <= VALUE <= 177ps
1
63ps
33.10%
-186ps <= VALUE <= 186ps
1
67ps
32.60%
-193ps <= VALUE <= 193ps
1
-64ps
34.00%
-200ps <= VALUE <= 200ps
1
-76ps
31.50%
-205ps <= VALUE <= 205ps
1
-77ps
31.70%
-210ps <= VALUE <= 210ps
1
75ps
32.60%
-215ps <= VALUE <= 215ps
1
101ps
50.00%
-99.00000E36s <= VALUE <=
99.00000E36s
1
16
tCH Average High
Measurements
503.4682mtCK(avg)
44.20%
470.0000mtCK(avg) <= VALUE
<= 530.0000mtCK(avg)
1
17
tCL Average Low
Measurements
496.4921mtCK(avg)
44.20%
470.0000mtCK(avg) <= VALUE
<= 530.0000mtCK(avg)
1
18
tjit(duty-high) Jitter Average
High Measurements
31ps
50.00%
-99.00000E36s <= VALUE <=
99.00000E36s
1
19
tjit(duty-low) Jitter Average Low
Measurements
34ps
50.00%
-99.00000E36s <= VALUE <=
99.00000E36s
1
Notes:
1)
2)
JEDEC Std. # 79-3C, Table 65
JEDEC Std. # 79-3C, Table 63 (CL=10, CWL=7)
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3.2.3.2 CLK3/GND and #CLK3/GND @ U19 Stacked BGA Frame
Table 3-5: CLK3/GND and #CLK3/GND @ U19 Stacked BGA Frame
Test
1
Notes:
1)
Test Name
Actual
Value
Guardband
Margin
VIX
63.00000mV
29.00%
Spec Range
-150.0000mV <= VALUE <=
150.0000mV
Note
1
JEDEC Std # 79-3C, Table 29
3.2.4
Write Timings
This section summarizes the JEDEC compliance testing on a write cycle. Scope shots are
shown in the figures following the tables.
3.2.4.1 Write Cycle: DQS0/GND and #DQS0/GND @ U19 Stacked BGA Frame
Table 3-6: Write Cycle: DQS0/GND & #DQS0/GND @ U19 Stacked BGA Frame
Test
1
2
3
Test Name
Overshoot amplitude (Clock, Data, Strobe,
Mask)
Overshoot area (Clock, Data, Strobe,
Mask)
Undershoot amplitude (Clock, Data,
Strobe, Mask)
Worst Actual
Worst Margin
Spec Range
Note
-227.0000mV
156.80%
VALUE <= 400.0000mV
1
0.000000V-ns
100.00%
VALUE <= 150.0000mVns
1
243.0000mV
160.80%
VALUE >= -400.0000mV
1
4
Undershoot area (Clock, Data, Strobe,
Mask)
0.000000V-ns
100.00%
VALUE <= 150.0000mVns
1
5
VIX
-11.00000mV
46.30%
-150.0000mV <= VALUE
<= 150.0000mV
2
Notes:
1)
2)
JEDEC Standard No. 79-3C, Table 38
JEDEC Standard No. 79-3C, Table 29
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3.2.4.2 Write Cycle: DQS0/#DQS0 and DQ2 @ U19 Stacked BGA Frame
Table 3-7: Write Cycle: DQS0/#DQS0 and DQ2 @ U19 Stacked BGA Frame
Guardband
Margin
19.70%
Test
1
Test Name
VIH.DQ(AC)
Actual Value
1.077000V
Spec Range
VALUE >= 900.0000mV
850.0000mV <= VALUE <=
1.500000V
VALUE <= 600.0000mV
0.000000V <= VALUE <=
650.0000mV
Note
1
2
VIH.DQ(DC)
1.019000V
26.00%
3
VIL.DQ(AC)
475.0000mV
20.80%
4
VIL.DQ(DC)
451.0000mV
30.60%
5
Overshoot amplitude (Clock, Data,
Strobe, Mask)
-100.0000mV
125.00%
VALUE <= 400.0000mV
5
6
Overshoot area (Clock, Data,
Strobe, Mask)
0.000000V-ns
100.00%
VALUE <= 150.0000mV-ns
5
7
Undershoot amplitude (Clock,
Data, Strobe, Mask)
360.0000mV
190.00%
VALUE >= -400.0000mV
5
8
Undershoot area (Clock, Data,
Strobe, Mask)
0.000000V-ns
100.00%
VALUE <= 150.0000mV-ns
5
2
3
4
9
tDS(base)
215ps
616.70%
VALUE >= 30ps
6
10
tDH(base)
311ps
378.50%
VALUE >= 65ps
6
11
tWPRE
1.184913tCK(avg)
31.70%
VALUE >= 900.0000mtCK(avg)
6
12
tWPST
413.8622mtCK(avg)
38.00%
VALUE >= 300.0000mtCK(avg)
6
13
tDQSS
12.30673mtCK(avg)
47.50%
-250.0000mtCK(avg) <= VALUE <=
250.0000mtCK(avg)
6
14
tDSS
503.1627mtCK(avg)
151.60%
VALUE >= 200.0000mtCK(avg)
6
15
tDSH
476.0625mtCK(avg)
138.00%
VALUE >= 200.0000mtCK(avg)
6
16
tDQSL
490.0626mtCK(avg)
40.10%
450.0000mtCK(avg) <= VALUE <=
550.0000mtCK(avg)
6
17
tDQSH
489.9159mtCK(avg)
39.90%
450.0000mtCK(avg) <= VALUE <=
550.0000mtCK(avg)
6
Notes:
3)
4)
5)
6)
7)
8)
JEDEC Standard No. 79-3C, Table 25 (Vref=0.75)
JEDEC Standard No. 79-3C, Table 25 (Vref=0.75; VDD=1.50)
JEDEC Standard No. 79-3C, Table 25 (Vref=0.75)
JEDEC Standard No. 79-3C, Table 25 (Vref=0.75; VSS=0.00)
JEDEC Standard No. 79-3C, Table 38
JEDEC Standard No. 79-3C, Table 65
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Figure 3-13: CH1=CLK3_CH2=DQS0_CH3=DQ2_AC limit
Figure 3-14: CH1=CLK3_CH2=DQS0_CH3=DQ2_DQ2 Vmax=1.124V_Vmin=365mV
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Figure 3-15: CH1=CLK3_CH2=DQS0_CH3=DQ2_tDQSS=-44ps
Figure 3-16: CH1=CLK3_CH2=DQS0_CH3=DQ2_tDSH=678ps
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Figure 3-17: CH1=CLK3_CH2=DQS0_CH3=DQ2_tDQSS=-44ps
Figure 3-18: CH1=CLK3_CH2=DQS0_CH3=DQ2_tDSH=678ps
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Figure 3-19: CH1=CLK3_CH2=DQS0_CH3=DQ2_tWPRE=1.767ns
Figure 3-20: CH1=CLK3_CH2=DQS0_CH3=DQ2_tDQSH=722ps
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Figure 3-21: CH1=CLK3_CH2=DQS0_CH3=DQ2_tDQSL=778ps
Figure 3-22: CH1=CLK3_CH2=DQS0_CH3=DQ2_tDS=244ps
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Figure 3-23: CH1=CLK3_CH2=DQS0_CH3=DQ2_tDH=356ps
Figure 3-24: CH1=CLK3_CH2=DQS0_CH3=DQ2_tDS=200ps
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Figure 3-25: CH1=CLK3_CH2=DQS0_CH3=DQ2_tDH=722ps
Figure 3-26: CH1=CLK3_CH2=DQS0_CH3=DQ2_tWPST=622ps
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Figure 3-27: CH1=CLK3_CH2=DQS0_CH3=DQ2_AC limit
3.3 BGA Stack Mechanical Reliability and Structural Integrity
The BGA Stack Structural Integrity Test validation thoroughly proved the mechanical
reliability of the DIMM module solder joints by environmental and accelerated life testing. The
specific areas of the validation of BGA stacking were the solder joints on the stacked PCB
and the processes that create the joints to ensure that the joints have good bond strength.
At the completion of the testing, no structural failures or solder crack initiation was observed
on the BGA connections. All of the structural tests passed without issue, confirming that the
design, materials, and processes used to apply the BGA stack to a DIMM module are proven
to be reliable and repeatable. All the necessary validations and tests were performed that
would expose any problems or weaknesses in the design, and none were found.
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3.3.1 Extended Thermal Cycle
Thermal cycling is a highly accepted method of placing mechanical stresses on a structure
that closely mimics the stresses that are experienced in real life operational conditions.
Stress can be accelerated to enable the simulation of years of normal operation. This
simulation only takes several months in a thermal cycle chamber. The thermal cycle test and
sample size that was run on the BGA stacking was as follows:
According to JESD22-A104-B (approximately equivalent to IPC 9701)
•
0° C, to 100° C, to 0° C profile
•
2 cycles per hour
•
10 min ramps
•
5 min dwells
•
14 x DDR3 8GB VLP DIMM’s (Viking P/N VR7VA1G7254GHDSBT1)
•
Thermotron Model 7800 thermal cycle chamber (current calibration)
Although JESD22-A104-B requires 1000 cycles, this procedure ran for 14,330 cycles. All
modules were thoroughly tested before starting the procedure and were found to be 100%
functional with no errors or physical defects. Modules were placed in the chamber and the
profile program was executed. The modules were removed from the chamber twice per week
check and were given a full functional test and visual inspection, with an average time
between check points of 168 cycles. The results were logged and the modules were returned
to the thermal cycle chamber to continue the procedure. At the completion of 11,330 cycles,
the procedure ended. All modules were thoroughly tested after the procedure and were found
to be 100% functional with no errors or defects. Periodically, one module was pulled from the
test population and processed with a dye-and-pry procedure. This procedure was performed
by coating the module in a dye penetrant, baking for 2 hours, and then mechanically prying
the module layers apart. The BGA’s were also pried off the FR4 substrate. Afterwards, both
sides of every solder joint was inspected under a microscope to determine if any solder joint
cracks had begun to propagate. The intervals for the dye-and-pry procedure were 3300
cycles. There are approximately 1152 BGA stacking solder joints per module (18 x 64 solder
joints) for a total of about 16128 total joints in the test (1152 x 14). The solder joints were
inspected under magnification for evidence of crack propagation.
Test results: The BGA solder joints showed no cracks and no functional failures occurred.
During the pry procedure, as substantial amount of force was needed to separate the stacks
from the FR4 substrate, indicating that the solder joints in the assembly are strong and well
formed. The predominant solder joint failure mode was the pulling away of the solder pad
from the PCB surface, indicating that the solder joint is strong and is not the primary weak
point. The failure modes are not highly skewed toward one type, indicating that there is a
good distribution of the weak points in the assembly. The following figure shows an image of
the dye and pry module.
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Figure 3-28: Dye and Pry on an 8GB VLP RDIMM
Figure 3-29: Dye and Pry on an 8GB VLP RDIMM
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Figure 3-30: Removal of top BGA from BGA Stack
Figure 3-31: Removal of top BGA from BGA Stack
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3.3.2 Shock and Vibration
Table 3-8: Shock and Vibration Specifications
Mode
Shock1 Operating and nonOperating
Vibration1 Operating and nonOperating
MIL STD-810F, section 516.6
MIL STD-810F, section 514.5
50g 11ms, 3 Axis, Half Sine,
Positive and Negative
20~1000Hz: 0.04g2/Hz 3 Axis
1000~2000Hz: 6db/oct 3 Axis
Notes:
1. Shock and vibration specifications assume that the DIMM is latched securely in the DIMM socket. Stimulus may be
applied in the X, Y, or Z axis.
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3.4 BGA Stack Electrical Reliability and Thermal Analysis
3.4.1 Temperature Testing the BGA Stack while under power
The figure below shows the test vehicle for testing the thermal effects of the BGA stack. The
U# reference designators shown in yellow (U2, U9, U8, U18 and U11) were the locations for
thermocouples that were placed inside the BGA Stack on the DRAM devices directly
attached to the DIMM PCB. The 1st BGA stack receiving airflow was U8.
Figure 3-32: Thermocouple locations on an 8GB VLP RDIMM, DDR3-1333
Air Flow
Air Flow
Thermocouples placed inside the BGA stack at U2, U9, U8, U18 and U11
The 8GB VLP DIMM, DDR3-1333, (Viking module P/N VR7VA1G7254GHDSBT1 with a Vdd
of 1.5v was tested in a DDR3-1333 Intel server motherboard (S5520HC) with 10mm DIMM
socket spacing. The entire system was placed into a thermal chamber for 24 hours at an
ambient air temperature of 45ºC running Memtest86 memory stress test. The graph below
shows the results of the testing and how temperature rise within the BGA stack can vary
depending on placement in the air flow.
 5ºC rise inside the BGA stack for the 1st BGA stack upstream in the airflow (U8)
 15ºC average temperature rise inside the BGA stack downstream in the airflow
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Figure 3-33: Temperature rise for Samsung DDR3-1333 DRAM inside BGA Stack
Temperature
(ºC )
8G VLP RDIMM, DDR3-1333, Viking PN VR7VA1G7254GHDSBT1
DDR3 U2, U9, U11, U18 (inside BGA Stack)
DDR3 U8
Ave. Ambient Temperature = 45 ºC
Test Conditions:
Running Memtest86 in an Intel Thurley
Time (over 24 hour period)
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Most DDR3 DRAM today are specified with a maximum DRAM operating case temperature
of 85°C, (or 95°C, if the DRAM is refreshed externally at 2X refresh, which is a 3.9μs interval
refresh rate. The use of self refresh temperature (SRT) or automatic self refresh (ASR), if
available, must be enabled.)
The maximum ambient air for the BGA stack can be calculated using the worse case 15ºC
rise inside the BGA stack. The maximum temperature for the last BGA stack downstream in
ambient air at approximately 1 meter/sec airflow would be:
Tcase –Trise = Tambient or
85 – 15 = 70
The maximum 70ºC ambient for the BGA stack also coincides with the maximum
temperature rated for a non-stacked DIMM rated for commercial temperature operation.
The thermal resistance of the stack can be calculated as:
Tcase - Tambient = CA x DRAM Power
Where CA is the thermal resistance of the stack, (DRAM Case temperature inside stack to
Ambient air)
DRAM Power can be approximated using the datasheet for DRAM in the test module,
Samsung 2Gb 512Mx4 devices (PN K4B2G0446B HCH9) DDR3-1333 DRAM
 Active Die = 1.5V x 90mA = 135mW (using IDD1 per spec, See note 1)
 De-Selected Die = 1.5V x 60mA = 90mW (using IDD3N per spec, See note 1)
 Power (Total for 2 die in the stack)= 135mW + 90mW = 225mw (~ 0.25 watts)
Table 3-9: Samsung 2Gbit x4 devices (PN K4B2G0446B HCH9) DDR3-1333 DRAM
Note1: Datasheet at http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=691&partnum=K4B2G0446B
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The thermal resistance of the stack from DRAM case to ambient air at approximately
1 meter/sec airflow is estimated using the 5ºC rise since this based on the 1st BGA stack
upstream in the airflow (U8) without preheated air from other DRAM.
CA = Tcase - Tambient / power
or
5ºC rise / 0.25watts = 20ºC/W.
The maximum ambient air for cooling the DIMM can now be calculated as:
Tambient max at the DIMM= 85 - 20 x power (where T is in ºC; power in watts)
This equation can be used for other DRAM components or for DRAMs operated at other
speed or power levels.
3.4.2 Temperature rise of DDP’s compared to BGA Stacking
According the table below, DDP temperature rise over ambient can be approximately 10ºC at
1 meter/second airflow. One possible reason why DDP’s may run hotter than BGA stacking is
that DDP’s have only 1 set of DRAM solder balls to transfer the heat from 2 die into the PCB
via conduction. As a result DDP’s would rely more heavily on convection cooling via airflow.
On the other hand, a Viking BGA stacked module has two sets of solder balls to conduct heat
from the 2 DRAMs into the PCB via conduction cooling removing heat more effectively than
convection cooling using airflow. This is due to the fact that the thermal resistance of the
PCB is lower than air. However, heat from the PCB’s must eventually be removed at some
location within the system using a combination of conduction and convection.
Table 3-10: Micron DDR3 DDP Thermal Chart
DRAM
Airflow
Thermal
Impedance
(Junction to
ambient)
DDR3
1333
(M/s)
JA (ºC/W)
JC (ºC/W)
= Idd x Vdd
(mw)
= JA *
power
ºC
0
61
2.8
238.5
14.5485
1
44
2.8
238.5
10.494
Micron
D die
(DDP)
Micron
D die
(DDP)
Thermal
Impedance
(Junction
to case)
Power
Temperature
rise from
ambient
Temperature
rise from
case
Ambient
Junction
temperature
case temp
ºC
= ambient +
(JA * power)
= Junction (JC * power)
0.6678
45
59.5485
58.8807
0.6678
45
55.494
54.8262
Note1: Thermal Impedance based on Micron MT41J1G4_64M_32M_twin die DDP at 1.5v
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4 Memory Module Enhancements
Beyond the standard features for a JEDEC standard memory module, there are optional and
additional enhancements that can be made to memory modules that would increase
performance and reliability in demanding environmental conditions. Some of these options
are:






Modules rated for or screened to an Industrial temperature range: -40 to +85ºC
Thermal sensor and SPD defined to increase DRAM refresh rate or fan speed
Full DIMM heat spreaders
Conformal coating, Type 1B31 Acrylic, MIL-I-46058 Rev. C. Type AR
Low voltage DRAM (i.e. DDR3 at 1.35V and 1.25V when available)
Modules screened for extended Vref guardband margining for system reliability
5 System Design Recommendations
The recommendations listed below are not to be interpreted as design rules for using BGA
stacked DIMMs, but only as suggested ideas for gaining the maximum performance/cost
benefits of using BGA stacked modules.
Small form factor memory modules such as SO-DIMMs, Mini-DIMMs and VLP DIMMs may
have a higher power density (watts/area) and generally may need some extra consideration
for thermal cooling.
The specification for the maximum DRAM case temperature shown in the table below
indicates that a thermal solution must be designed to ensure the DRAM TCase does not
exceed the maximum rating.
Table 5-1: Maximum DRAM Case Temperature
Parameter/Condition
Symbol
Value
Units
Notes
0
to
85
°C
1, 2
Maximum DRAM operating
TCase
case temperature
0 to 95
°C
1, 2, 3
Notes:
1. TCase is measured in the center of the package
2. Device functionality is not guaranteed if the DRAM device exceeds the maximum TCase during operation.
3. If TCase exceeds 85°C, the DRAM must be refreshed externally at 2X refresh, which is a 3.9μs interval
refresh rate. The use of self refresh temperature (SRT) or automatic self refresh (ASR), if available,
must be enabled.
If the system designer is using airflow to cool the memory, the following sections will help:
1) Determine the airflow requirements for cooling BGA stacked memory modules
2) Prevent heat from degrading memory reliability
3) Prevent heat generated ECC memory errors from slowing down the computer
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5.1 Air Flow Recommendations
5.1.1 Air Flow for Commercial Temperature Operation (0 to 70ºC)
The figure below graphs the recommended airflow vs. air temperature for an 8GB VLP
RDIMM rated for the commercial temperature range of 0-70ºC.
Figure 5-1: Air Flow for Commercial Temperature Operation (0 to 70ºC)
Air temperature vs. air velocity for safe operation
Commercial Temp BGA Stack DIMM - 70C max
60
Air temperature (C)
55
50
Region for reliable operation for a
Commercial Temperature
8GB VLP RDIMM
with BGA Stacking
45
40
35
30
0
1
2
3
4
5
6
Air v elocity (m/s)
5.1.2 Air Flow for Industrial Temperature Operation (-40 to 85ºC)
The figure below graphs the recommended airflow vs. air temperature for an 8GB VLP
RDIMM rated for the industrial temperature range of -40-85ºC.
Figure 5-2: Air Flow for Industrial Temperature Operation (-40 to 85ºC)
Air temperature vs. air velocity for safe operation
Industrial Temp BGA Stack DIMM - 85C max
75
70
Air temperature (C)
65
60
Region for reliable operation for an
Industrial Temperature
8GB VLP RDIMM
with BGA Stacking
55
50
45
40
0
1
2
3
4
5
Air ve locity (m/s)
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6
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5.2 Ideas on Cooling By Airflow
5.2.1 Memory Module Placement in the System
Whenever possible, it is recommended to design the memory subsystem in a way that avoids
blowing preheated air over the DRAM module. For example, place the memory subsystem to
the sides of processor(s) and outside the airflow of hot air generated by the heatsink on the
processor(s) or other hot components such as the power supply or chipset. The ambient
intake air should flow over the memory subsystem and other hot components like the
processor(s) at the same time. Placing the memory sockets closest to the inlet air would be
desirable. If this is not possible, the use of a shroud, duct or plenum to direct and contain the
airflow through the memory subsystem parallel to the longest sides of the DRAM modules
and on both sides of the module. These enclosures may also allow for slower fan speeds
with less acoustical noise without impacting airflow.
5.2.2 DIMM Socket Selection and Orientation
Select the best DRAM module socket and orientation to prevent trapped heat pockets. If the
motherboard/systemboard is mounted flat and perpendicular to the line of gravity, the best
orientation for the memory module would be a vertical mount, since heated air rises up along
the line of gravity. A vertical module orientation prevents heat from being trapped under the
lower bottom side of the memory modules.
A socket selection with a low seating plane could make this possible. As an example, using a
DDR3 DIMM socket that lowers the seating plane from 3.3mm to 2.4mm, will allow a JEDEC
standard DDR3 VLP at 18.75mm tall (per JEDEC MO-269) to fit into an ATCA chassis having
a maximum height restriction of just over 21mm.
If a vertical mount is not possible then an angled mount DIMM orientation would benefit from
1-sided DIMMs with the DRAM components only mounted on the top side. This would be true
for memory DIMMs placed flat and parallel over the systemboard.
5.2.3 Air gaps for DIMM Sockets
Maintain a 2.5mm minimum air gap around each memory module. The 2.5mm air gap
between each memory module should take into account any extra width from memory
stacking and heat spreaders. If the air gap spacing between memory modules is too small,
an airflow back pressure may result from the physical obstruction of the DIMM modules in the
path of the airflow. This could result in an airflow pressure drop along the side of the DIMMs
resulting in a decreased airflow or the airflow may be diverted away or around the entire
memory subsystem. Current JEDEC convention for DIMM socket spacing is 10mm, center to
center, but larger spacing may be desirable to improve memory subsystem reliability.
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5.2.4 Increase Air Flow Pressure
One way to increase airflow pressure to extract heat away from the memory subsystem
would be to use blowers or dual fans, if acoustical noise is not an issue. Airflow with a
minimum pressure drop is best achieved by pulling out the hot air at the exhaust location and
pushing air in at the intake location in the system.
6 Conclusion
Viking BGA stacking technology provides a reliable alternative to DDP or high density
monolithic DRAM with the following additional benefits:
 Lower cost
 Shorter lead times
 Flexible DRAM choices
 Available in industrial temperature range: -40 to +85ºC
 Low Voltage options: 1.5V, 1.35V (and 1.25V when available)
7 Reference and Additional Information
[1] Low Cost Through Silicon Via Solution Compatible with Existing Assembly
Infrastructure and Suitable for Single Die and Die Stacked Packages
http://www.tessera.com
About Viking Technology
Viking Technology develops and delivers innovative high-technology products that optimize
the value and performance of our customers’ applications. Founded in 1989, Viking
Technology has been providing Original Equipment Manufacturers (OEMs) with industry
leading designs, engineering, product support and customer service for 20 years. For more
information visit http://www.vikingtechnology.com.
Viking Technology20091 EllipseFoothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159Website: www.vikingtechnology.com
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