13606CP
13 GHz Latched Comparator
Data Sheet
Applications
•
•
•
•
•
•
•
•
Broadband test and measurement equipment
Oscilloscope and logic analyzer front ends
Window comparators
Mono-bit receivers
High speed line receivers and signal regeneration
Threshold and/or peak detectors
High speed triggers
Digital Phase and Frequency Detection
Features
•
•
•
•
•
•
•
•
•
•
•
•
Supports clock rates up to 13 GHz
propagation delay (Clk-to-Q): 65 ps typ.
Low power consumption: 550 mW typ.
Fast rise and fall times: 15 ps typ.
Deterministic Jitter: 2.0 ps p-p typ.
Random Jitter 60 fs RMS typ.
Hysteresis <5 mV
Output amplitude 1.2 Vpp differential
Supports single-ended and differential operation
Single –3.3 V power supply
Available in plastic QFN package
Evaluation board available
Description
The 13606CP is an exceptionally fast latched voltage
comparator with very low thermal hysteresis that
operates with clock rates from DC to 13 GHz. The
part is nominally positive-edge triggered; however,
by reversing the positive and negative clock
connections, a negative-edge triggered application
can be accommodated. All differential analog inputs
and differential clock inputs are DC coupled on-chip
and terminated with resistors to ground. The
differential data outputs should be terminated off
chip with 50 Ω resistors to ground.
The 13606CP operates from a single -3.3 V power
supply and is available in a 3 X 3 mm, plastic,
QFN package. The packaged part is also available
on an evaluation board with SMA connectors.
For customers requiring a comparator that
operates from a +3.3 V power supply, Inphi
offers the 13607CP.
Block Diagram
GND
IN+
In
OUTp
Out
IN-
OUTn
25706CP
13606CP
Latch
Clk In
CLKINp
CLKINn
VEE
2008-03-18
13606CP_DS_Ver1.1
Inphi Proprietary
Page 1 of 12
Absolute Maximum Ratings
•
•
•
Stresses beyond those listed here may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any other conditions beyond
those indicated in the “Operating Conditions” and “Electrical Specifications” of this datasheet is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameter
Symbol
Power Supply Voltage
Conditions
Min
Max
Unit
10 sec. stress time
–3.9
+0.5
V
IN+, IN-,
10 sec. stress time
CLKIN
–4.0
+1
V
–3.0
+1
V
VEE
Analog and Clock Input Signals
Output Signals
DOUT
10 sec. stress time
Junction Temperature – Die
TJ
---
+175
°C
Case Temperature– Package Paddle
TC
---
+125
°C
TSTORE
---
+125
°C
RH
0
100
%
VEE, GND
>500
---
V
Outputs
>200
---
V
Clock & analog inputs
>500
---
V
Shipping/Storage Temperature
Humidity
ESD protection
(HBM)1
VESD
Notes:
1 As
per JESD22-A114-B.
Operating Conditions
•
Important Note: Unused I/O should be terminated with 50 Ω to GND for all specifications to be met.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Power Supply Voltage
VEE
± 5% Tolerance
–3.465
–3.300
–3.135
V
Power Supply Current
IEE
---
167
255
mA
On-Chip Power Dissipation
PD
---
550
800
mW
Operating Temperature (Junction) – Die
TJ
+15
---
+125
°C
Operating Temperature (Case) – Package
TC
Bottom of Paddle
–5
---
+85
°C
Thermal Resistance – junction to paddle
RJC (θJC)
Bottom of paddle
---
51
---
°C/W
2008-03-18
13606CP_DS_Ver1.1
Inphi Proprietary
Page 2 of 12
DC Electrical Specifications
!
•
WARNING – To prevent damage to the part:
•
DC power must be turned off prior to connecting or disconnecting any cables.
Electrical specifications guaranteed when the part is operated within the specified operating conditions
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Analog Input Specification
Input High Level
VIH
GND referenced
-0.5
---
0.3
V
Input Low Level
VIL
GND referenced
-0.8
---
0
V
Input Amplitude1
VINpp
Differential peak-to-peak
---
---
1200
Single ended peak-to-peak
---
---
1000
VOS
---
±1.5
±6.0
mV
ΔVOS/ΔT
---
3.0
---
μV/°C
Input to GND
55
62.5
70
Ω
Measured with DC input and
100 MHz clock
---
5.0
6.0
mV
Input Offset Voltage2
VOS Temperature Coefficient
DC Input Resistance
RIN
Hysteresis (DC)
mVpp
Clock Input Specification
Input High Level
VIH
GND referenced
–0.5
---
0.5
V
Input Low Level
VIL
GND referenced
–0.8
---
0
V
Differential peak-to-peak
300
---
1200
Single ended peak-to-peak
200
---
1000
RCLKIN
Input to GND
45
50
55
Ω
Data Output Amplitude
DOUT
Differential peak-to-peak
1000
1250
1400
mVpp
Output High Voltage
VOH
DC coupled, GND referenced
-85
-55
0
mV
Output Common Mode
VOCM
DC coupled, GND referenced
-425
-360
-300
mV
Output Eye Cross
VOEC
Single-ended measurement
40
50
60
%
DC Output Resistance
ROUT
Output to GND
59
65
71
Ω
Input Amplitude1,3
(Important: See note #3)
VCLKpp
DC Input Resistance
mVpp
Data Output Specification4
Notes:
1 Analog and clock input amplitudes <300 mVpp may cause part to fail the following AC electrical specifications:
Clock Phase Margin, Deterministic Jitter, Random Jitter, Clock to Data Output Delay.
2 Typical refers to variance or “1-sigma” value. Expectation value is 0 mV.
3 For optimum performance in the clock frequency range of 10.5 GHz to 12.5 GHz, the clock input amplitude should be
reduced. Decision accuracy may be degraded and the output data eye may be distorted for clock amplitudes greater than
300 mVpp (single-ended) or 600 mVpp (differential). It is left to the customer to determine the best amplitude for
optimum system operation.
4 Outputs are CML and, when direct coupled, must be DC terminated with 50 Ω to GND. When AC-coupled, no external
DC termination is required and the output high and common mode levels are not applicable.
2008-03-18
13606CP_DS_Ver1.1
Inphi Proprietary
Page 3 of 12
AC Electrical Specifications
!
WARNING – To prevent damage to the part:
•
DC power must be turned off prior to connecting or disconnecting any cables.
Electrical specifications guaranteed when the part is operated within the specified operating conditions
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Analog Input Specification
Input Analog Bandwidth
BWIN
400 mVpp single-ended sine wave
---
23
---
GHz
Input Return Loss1
RLIN
0 to 13 GHz
14
---
---
dB
Soak time = 0.01 μs
---
2
---
Soak time = 1 μs
---
12
---
Soak time = 100 μs
---
16
---
13
---
---
GHz
At CLKIN zero crossing
---
---
1.0
V/ns
Thermal Hysteresis2
VTHYS
mV
Clock Input Specification
Maximum Clock Frequency
fMAX
Minimum Clock Slew Rate3
SMIN
Clock Input Return Loss4
RLCLK
0 to 13 GHz
14
---
---
dB
Clock Phase Margin
CPM
at 12.5 GHz
330
---
---
deg
tr/tf
20–80%
---
15
18
ps
0 to 11 GHz
13
---
---
dB
11 to 13 GHz
9
---
---
dB
Data Output Specification
Output Rise/Fall Time
Output Return Loss5
RLOUT
Added Deterministic Jitter6,7
JD
Peak-to-peak, FCLK = 12.5 GHz
---
2.0
4.0
ps
Random Jitter6,7
JR
RMS at 10 GHz
---
60
120
fs
Clock to Data Output Delay6
tQ
QFN Package
50
65
80
ps
Notes:
1 The Analog inputs are designed to be a broadband impedance match to 50 Ω and are DC terminated on chip with a
63 Ω resistor to GND.
2 See Hysteresis Specification section.
3 Minimum Clock Slew Rate specification ensures sufficiently fast clock edge rates on sine wave clock signals to maintain
given specifications. This device will operate with lower clock slew rates, though some performance specifications may be
degraded.
4 The Clock inputs are designed to be a broadband impedance match to 50 Ω and are DC terminated on chip with a 70 Ω
resistor to GND.
5 The data outputs are designed to be a broadband impedance match to 50 Ω and are DC back-terminated on chip with a
62 Ω resistor to GND.
6 Valid when clock to data phase is near center of CPM window. t specifications are not fully characterized.
Q
7 It should be noted that the random and deterministic jitter of Inphi's high-speed logic parts are "in the noise" of standard
oscilloscope measurement techniques. The deterministic jitter (JD) specified above is the measured peak-to-peak total
jitter, using a 27-1 PRBS data pattern, less the measured source peak-to-peak total jitter. The random jitter (JR) is based
on phase noise measurements.
2008-03-18
13606CP_DS_Ver1.1
Inphi Proprietary
Page 4 of 12
Timing Diagram
Input and Output Equivalent Circuits
2008-03-18
13606CP_DS_Ver1.1
Inphi Proprietary
Page 5 of 12
Typical DC Operating Characteristics
Output Amplitude (OutP, single-ended) vs. Supply with
Temperature as parameter
VOUTp Common Mode Voltage vs. Supply with
Temperature as parameter
-356
VOUTp Common Mode Voltage (mV)
OutP Amplitude (V)
0.69
T = -5 C
0.67
T = 25 C
T = 85 C
0.65
0.63
0.61
0.59
0.57
0.55
-358
-360
-362
-364
-366
T = -5 C
-368
T = 25 C
-370
T = 85 C
-372
-374
-376
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
Power supply (V)
3.3
3.4
3.5
3.6
Power supply (V)
Figure 1. Output amplitude (Vpp) vs. VEE and
temperature. Source is 12.5 Gbps 27-1 PRBS pattern.
Figure 3. Output common mode voltage (VDC) vs.
VEE and temperature, 12.5 Gbps 27-1 PRBS pattern.
Eye Crossing (OutP) vs. Supply with Temperature as
parameter
VOUTp VOH vs. Supply with Temperature as parameter
60.0
-52
VOUTp VOH (mV)
-54
Eye Crossing (OutP) (%)
T = -5 C
T = 25 C
T = 85 C
-56
-58
-60
-62
55.0
50.0
T = -5 C
45.0
T = 25 C
T = 85 C
40.0
-64
3.0
3.1
3.2
3.3
3.4
3.5
3.0
3.6
3.1
3.2
3.3
3.4
3.5
3.6
Power supply (V)
Power supply (V)
Figure 2. Output high voltage level (VDC) vs. VEE
and temperature. Source is 12.5 Gbps 27-1 PRBS
pattern.
Figure 4. Output data eye crossing vs. VEE and
temperature. Source is 12.5 Gbps 27-1 PRBS pattern.
Power Dissipation vs. Supply with Temperature as
parameter
0.75
Power Dissipation (W)
0.70
T = -5 C
0.65
T = 25 C
T = 85 C
0.60
0.55
0.50
0.45
0.40
3.0
3.1
3.2
3.3
3.4
3.5
3.6
Power supply (V)
Figure 5. Power dissipation (W) vs. VEE and
temperature.
2008-03-18
13606CP_DS_Ver1.1
Inphi Proprietary
Page 6 of 12
Typical AC Operating Characteristics
Gain vs. Frequency of CP in QFN
Gain (dB)
5.0
0.0
-5.0
Nominal Pin -4 dBm
-10.0
1
10
100
Freq (GHz)
Figure 6. Output data eye. Source is 12.5 Gbps
27–1 PRBS pattern.
Figure 7. –3 dB Bandwidth. Source is sine wave
with Pin = -4 dBm (~400 mVpp) single-ended.
Peak-to-Peak Jitter (OutP, 2^7-1 patt.) vs. Supply with
Temperature as parameter
Random Jitter (outp) vs. Supply with Temp. as
parameter
220
3.5
Random Jitter (RMS in fs)
Peak-to-Peak Jitter (ps)
T = -5 C
3.0
2.5
2.0
T = -5 C
1.5
T = 25 C
T = 85 C
215
T = 25 C
T = 85 C
210
205
200
195
190
185
1.0
3.0
3.1
3.2
3.3
3.4
3.5
3.0
3.6
3.1
Figure 8. Output peak-to-peak jitter vs. VEE and
temperature. Measurement includes total peak-topeak jitter of source and test equipment.
3.3
3.4
3.5
3.6
Figure 9. Output random jitter vs. VEE and
temperature. Measurement includes random jitter
of source and test equipment.
Rise Time (OutP) vs. Supply with Temperature as
parameter
Phase Margin vs. Supply with Temperature as parameter
330
17.0
T = -5 C
16.5
Phase Margin (degrees)
Rise Time (OutP) (ps)
3.2
Power supply (V)
Power supply (V)
T = 25 C
T = 85 C
16.0
15.5
15.0
14.5
328
T = -5 C
326
T = 25 C
324
T = 85 C
322
320
318
316
314
312
310
14.0
3.0
3.1
3.2
3.3
3.4
3.5
3.6
Power supply (V)
Figure 10. Output rise time (ps) vs. VEE and
temperature. Source is 12.5 Gbps 27-1 PRBS
pattern.
2008-03-18
13606CP_DS_Ver1.1
3.0
3.1
3.2
3.3
3.4
3.5
3.6
Power supply (V)
Figure 11. Analog input to clock input phase
margin (degrees) vs. VEE and temperature. Source is
12.5 Gbps 27-1 PRBS pattern.
Inphi Proprietary
Page 7 of 12
Typical Hysteresis Characteristics
Delta VOUT versus Delta VIN
0.8
-5 C
0.6
25 C
55 C
85 C
Delta Vout (V)
0.4
0.2
0.0
-0.2
-10
-5
0
5
10
-0.4
-0.6
-0.8
Delta Vin (mV)
Figure 12. Typical analog input (IN+) DC hysteresis on the 13606CP. For
this measurement, the offset voltage was calculated from the swept data by
taking the average of the threshold for the positive and negative sweep. The
difference between the thresholds is the hysteresis.
Hysteresis versus Soak Time
20.00
Data Hysteresis (mV)
18.00
16.00
14.00
12.00
10.00
8.00
6.00
4.00
2.00
0.00
(μs) 0.001
(Mbps) 1000
0.01
100
0.1
10
Data Soak
1
1
10
0.1
100
0.01
Figure 13. Analog input (IN+) thermal hysteresis on the 13606CP is shown as
a function of input soak time in μs (and equivalent data rate in Mb/s). Input
used was a 1010… square wave pattern at varying data rates. Clock frequency
set to 1 GHz.
2008-03-18
13606CP_DS_Ver1.1
Inphi Proprietary
Page 8 of 12
S-Parameter Characteristics
13606CP S11 of IN+ on Three Devices
0
-10
S11 (dB)
-20
-30
-40
SN1 IN+
SN3 IN+
-50
SN5 IN+
IN+/- Spec
-60
0
5
10
15
20
25
30
Frequency (GHz)
Figure 14. Input Return Loss under typical VEE and temperature conditions (see note below)
13606CP S11 of CLKINp on Three Devices
0
-10
S11 (dB)
-20
-30
-40
SN1 CLKINp
SN3 CLKINp
-50
SN5 CLKINp
CLKINp/n Spec
-60
0
5
10
15
20
25
30
Frequency (GHz)
Figure 15. CLKINp/n Input Return Loss under typical VEE and temperature conditions (see note)
13606CP S22 of Three Devices
0
-10
-20
SN1 DOUTn Low
SN3 DOUTn Low
SN5 DOUTn Low
SN1 DOUTp High
SN3 DOUTp High
SN5 DOUTp High
ORL Spec
dB
-30
-40
-50
0
5
10
15
20
25
30
GHz
Figure 16. Output Return Loss under typical VEE and temperature conditions (see note below)
Note: The periodic nulls are due to not calibrating out the PCB transmission lines.
2008-03-18
13606CP_DS_Ver1.1
Inphi Proprietary
Page 9 of 12
QFN Package Outline Drawing and Pin Assignment
Name
Pin
IN-
2
Inverting analog input. Internally terminated 65 Ω to GND.
Input
IN+
3
Non-inverting analog input. Internally terminated 65 Ω to GND.
Input
CLKINp
6
Non-inverting clock input. Analog input is latched on the rising
edge of this input signal. Internally terminated 50 Ω to GND.
Input
CLKINn
7
Inverting clock input. Analog input is latched on the falling edge of
this input signal. Internally terminated 50 Ω to GND.
Input
DOUTp
11
Non-inverting data output. Back terminated 60 Ω to GND. Always
terminate to 50 Ω to GND.
Output
DOUTn
10
Inverting data output. Back terminated 60 Ω to GND. Always
terminate to 50 Ω to GND.
Output
GND
1, 4, 5, 8, 9, 12,
14, Paddle
Ground
Supply
VEE
13, 15, 16
Power Supply: Connect to –3.3 V
Supply
2008-03-18
Description
13606CP_DS_Ver1.1
Inphi Proprietary
Function
Page 10 of 12
Order Information
Part No.
Description
13606CP-S01QFN
13 GHz Latched Comparator (–3.3 V Supply) in QFN Package
13606CP-S01QFN-EVB
13 GHz Latched Comparator (–3.3 V Supply) in QFN Package on an
Evaluation Board with SMA Connectors
Contact Information
Inphi Corporation
2393 Townsgate Road, Suite 101
Westlake Village, CA 91361
• Phone:
• Fax:
• E-mail:
(805) 446-5100
(805) 446-5189
products@inphi-corp.com
‚Visit us on the Internet at: http://www.inphi-corp.com
For each customer application, customer’s technical experts must validate all parameters. Inphi Corporation reserves the right to change
product specifications contained herein without prior notice. No liability is assumed as a result of the use or application of this product.
No circuit patent licenses are implied. Contact Inphi Corporation’s marketing department for the latest information regarding this product.
Qualification Notification
The 13606CP is fully qualified. Please contact Inphi for the qualification report.
Inphi Corporation will honor the full warranty as outlined in Section 5 of Inphi’s Standard Customer
Purchase Order Terms and Conditions.
Version Updates:
Version 1.0 (Released 2006-08-23):
Initial Release.
From Version 1.0 to Version 1.1 (dated 2008-03-18):
1. Added two entries to the Applications section (page 1).
2. Changes to the Features section (page 1).
a. Corrected the typical Propagation Delay (Clk-to-Q) to be 65 ps.
b. Changed the typical Deterministic Jitter value from 3.0 to 2.0 ps.
c. Changed the typical Random Jitter value from 0.2 ps to 60 fs.
3. Changes to the DC Electrical Specifications section (page 3):
a. Changed the Analog Input High level max. specification from +0.5 V to +0.3 V.
b. Changed the Clock Input Amplitude, Single-ended, min. spec from 300 to 200 mVpp.
c. Changed the Output Amplitude typical rating from 1200 mV to 1250 mV.
d. Added DC output resistance specifications in the Output Specification section.
e. Added Note #3, reduce clock amplitude when operating in the 10.5 to 12.5 GHz range.
f. Reworded Note #4 to clarify output DC termination requirements.
2008-03-18
13606CP_DS_Ver1.1
Inphi Proprietary
Page 11 of 12
Version Updates (cont’d.):
From Version 1.0 to Version 1.1 (dated 2008-03-18) (cont’d.):
2. Changes to the AC Electrical Specifications section (page 4):
a. Respecified the Analog input bandwidth (BWIN) to 23 GHz typical, removed 13 GHz min.
specification and added note (#1).
b. Changed Analog Input Return Loss RLIN minimum spec from TBD to 14 dB.
c. Corrected the first soak time test condition for the analog input, Thermal Hysteresis
specification. The soak time was changed from 0.1 μs to 0.01 μs.
d. Added Minimum Clock Slew Rate note (#3).
e. Changed Clock Input Return Loss RLCLK minimum spec from TBD to 14 dB.
f. Changed Clock Phase Margin minimum spec from TBD to 330 degrees.
g. Split Output Return Loss (RLOUT) into two rows and changed minimum spec from TBD to
13 dB for the frequency range of “0 to 11 GHz” and 9 dB for “11 to 13 GHz”.
h. Changed the Deterministic Jitter specs: the typical spec from 3.0 to 2.0 ps and the max spec
from 6.0 to 4.0 ps.
i. Changed the Random Jitter specs: the typical spec from 0.3 ps to 60 fs and the max spec
from 0.6 ps to 120 fs.
j. Removed the Clock to Data Output Delay specs (die form).
k. Corrected the Clock to Data Output Delay specs (QFN package): the minimum spec from
80 to 50 ps, the typical spec from 100 to 65 ps and the max spec from 120 to 80 ps.
l. Deleted the Clock to Data Output Delay Variation parameter; was TBD.
m. Added Note #1, 4 & 5 relating to the I/O impedances and Return Loss specs.
n. Deleted old Note #3 that explained the Clock to Data Output Delay Variation parameter.
o. Added new Note #3 explaining the slew rate and square wave clocks.
p. Removed reference to ΔtQ in footnote #6
q. Added Note #7 in reference to both the random and deterministic jitter measurement
techniques.
3. Added figure 7 and made several wording corrections to figure captions in Typical Operating
Characteristics sections (pages 6–7).
4. Added S-parameter Characteristics section with figures 14 through 16 (page 9).
5. Updated Qualification Notification by changing “limited” status to “fully qualified” (page 11).
2008-03-18
13606CP_DS_Ver1.1
Inphi Proprietary
Page 12 of 12