Sunday May 15th, 2016
Sunday, 5/15
Registration
Memory System Tutorial
RRAM Tutorial
Lunch Break (provided)
MRAM Tutorial
8th International Memory Workshop
May
15th
–
18th
2016
Paris Marriott Rive Gauche Hotel
Paris, France
General Chair
Jing Li
U. of Wisconsin
USA
Technical Chair
Randy Koval
Intel
USA
Finance Chair
Gabriel Molas
CEA LETI
France
Publicity Chair
Sung-Yong Chung
SK Hynix
Korea
Scientific Committee
Alessandro Baiano, NXP, Netherlands
Wen-Ting Chu, TSMC, Taiwan
Damien Deleruyelle, Aix-Marseille Univ., France
Bernard Dieny, CEA-Spintec, France
Pei-Ying Du, Macronix, Taiwan
Yoshiaki Fukuzumi, Toshiba, Japan
Akira Goda, Micron, USA
Micha Gutman, TowerJazz, Israel
Hyeong Soo Kim, SK Hynix, Korea
Klaus Knobloch, Infineon, Germany
Takashi Kobayashi, Hitachi, Japan
Gwan-Hyeob Koh, Samsung, Korea
Gill Lee, Applied Materials, USA
Alfonso Maurelli, ST Microelectronics, Italy
Scott Summerfelt, TI, USA
Zhiqiang Wei, Panasonic, Japan
Monday, 5/16
Registration
Opening remarks
Session #1
Committee Luncheon
Lunch Break (on your own)
Session #2
Panel discussion
Reception
Poster Session
Tuesday, 5/17
Registration
Session #3
Session #4
Lunch Break (on your own)
Session #5
Session #6
Banquet (provided)
Wednesday, 5/18
Registration
Session #7
Session #8
Closing Remarks
Lunch Break (provided)
Conference location:
Paris Marriott Rive Gauche Hotel
Advisory Committee
Jan Van Houdt, IMEC, Belgium
Agostino Pirovano, Micron, Italy
Paris Marriott Rive Gauche Hotel & Conference Center
17 Boulevard Saint Jacques Paris 75014 France
Tel: +33-1-4078 7980
Tutorial Registration on site: 7:00AM – 5:00PM
7:00AM – 5:00PM
8:00AM – 9:00 AM
9:00AM-12:00 PM
12:00PM – 2:00PM
2:00PM – 5:00PM
7:00AM – 6:00PM
8:00AM – 8:20AM
8:20AM – 11:50AM
12:00PM – 2:00PM
2:00PM – 3:40PM
4 :00PM – 5:30PM
5:30 PM
6:00PM – 8:30PM
7:00AM – 5:00PM
8:00AM – 9:40AM
10:05AM –12:10PM
12:10PM – 2:00PM
2:00PM – 3:40PM
4:10PM – 5:50PM
7:00PM – 9:00PM
7:00AM – 12:00PM
8:00AM – 10:05AM
10:30AM – 12:10PM
12:15 AM – 12:35PM
12:35 PM – 2:00PM
Tutorials
8:00AM-5:00 PM
Chairs: Zhiqiang Wei (Panasonic, Japan)
Thibaut Devolder (IEF, France)
Memory System
8:00AM – 9:00AM
Instructor: Will Akin (Micron)
The short course will provide an introduction to memory system architecture. This will
include an overview of fundamentals within mobile, compute and storage systems, relevant
benchmarks used for NVM solutions technologies (SSD's and Mobile eMMC/UFS) and key
metrics that benefit applications
RRAM
9:00AM – 12:00PM
Instructors: W. Chang (Winbond), S. Yoneda (Panasonic), Y. Chen (Sandisk)
Technology experts will review the fundamentals of RRAM, benchmark against the
incumbent NVM technologies, and review the application-dependent requirements of
RRAM technology for storage class memory and embedded applications.
MRAM
2:00PM – 5:00 PM
Instructors: V. Cros (CNRS/Thales), J. Slaughter (Everspin), M. Gaidis (Samsung)
Technology experts will cover STT-MRAM phenomena & materials, from in-plane to out-ofplane magnetized STT-MRAM, and STT-MRAM scaling status, challenges, and outlook.
Poster Session
Monday May 16th, 2016
6:00 PM – 8:30 PM
1) S Ngueya, J. Portal, Safran-Starchip/Aix-Marseille University, “Ultra Low Power Charge
Pump with Multi-Step Charging and Charge Sharing”
2) J. Yang-Scharlotta, JPL/Caltech/NASA, “Reliability Characterization of TaOX-based
Commercial ReRAM in Combination with Radiation”
3) V. Markov, SST, “SuperFlash® Scaling Aspects: Program Disturb”
4) Yu-Ming Chang, Yuan-Hao Chang, Macronix/ Academia Sinica Taipei, “An Efficient
Sudden-Power-off-Recovery Design with Guaranteed Booting Time for Solid State
Drives"
5) S. Gautam, A. Kumar, IIT Roorkee (India)/Applied Materials, “Reduction of GIDL using
Dual Work Function Metal Gate in DRAM”
6) A. Kumar, Indian Institute of Technology Delhi, “Hybrid CMOS-OxRAM Image Sensor
for Overexposure Control”
7) J. A. J. Rupp, Aachen University, “Threshold Switching in Amorphous Cr-doped
Vanadium Oxide for New Crossbar Selector”
8) B. Vaidyanathan, Micron Technology, “Hierarchical Full-Chip Fast-simulation Based
Design Mitigation of CHC in NAND Flash Memory”
9) C. Wang, D. Sekar, Tsinghua University/Rambus, “The statistical evaluation of
correlations between LRS and HRS relaxations in RRAM array”
10) L. Zuolo, R. Micheloni, Universita degli Studi di Ferrara/Microsemi, “Memory System
Architecture Optimization for Enterprise All-RRAM Solid State Drives”
11) A. Hardtdegen, C LaTorre, Julich/Aachen University, “Internal Cell Resistance as the
Origin of Abrupt Reset Behavior in HfO2-based Devices determined from Current
Compliance Series”
12) H. Koike, Tohoku University, “Demonstration of yield improvement for on-via MTJ
using a 2-Mbit 1T-1MTJ STT-MRAM test chip”
Monday May 16th, 2016
Tuesday May 17th, 2016
Wednesday May 18th, 2016
Registration 7:00 AM - 6:00 PM
Registration 7:00 AM - 5:00 PM
Registration 7:00 AM - 12:00 PM
Session #1 8:00 AM – 11:50 AM
Chairs:
Jing Li, UW-Madison, USA
Randy Koval, Intel, USA
8:00 AM
8:20 AM
8:50 AM
9:20 AM
Invited
Session #3 8:00 AM – 9:40 AM
Chairs:
Jan Van Houdt, IMEC, Belgium
Pei-Ying Du, Macronix, Taiwan
Jing Li, Opening Remarks
Seiichi Aritome, “NAND Flash Memory Revolution”
Annie Foong, Intel, “Wicked Fast Storage and Beyond”
Seung H. Kang, Qualcomm, “Embedded STT-MRAM: A Holistic
Approach to Device, Circuit, and System”
8:00 AM
9:50 AM
Break (Refreshments Provided)
9:15 AM
10:20 AM
10:50 AM
Luca Perniola, CEA-LETI, “Universal Signatures from Non-Universal
Memories: Clues for the Future…”
Nhan Do, SST (a subsidiary of Microchip Technology),
“eNVM Technologies Scaling Outlook and Emerging NVM
Technologies for Embedded Applications“
11:20 AM
Lunch Break (on your own)
12:00 PM
Committee Luncheon
8:25 AM
8:50 AM
9:40 AM
10:30 AM
2:00 PM
2:25 PM
2:50 PM
3:15 PM
3:40 PM
RRAM-1
C.Y. Chen, IMEC, “Doped Gd-O based RRAM for Embedded
Application”
M. Azzaz, STMicroelectronics/CEA, LETI, " Endurance/Retention
Trade Off in HfOx and TaOx Based RRAM"
G. Piccolboni, CEA, LETI “Vertical CBRAM (V-CBRAM): From
Experimental Data to Design Perspectives”
W.W. Koelmans, IBM Research Zurich, “Carbon-Based Resistive
Memories”
Break (Refreshments Provided)
10:55 AM
11:20 AM
11:45 AM
12:10 PM
2:25 PM
2:50 PM
Storage Class Memory: Technical and Commercial Challenges
Moderator: Amulya Athayde (Applied Materials)
Panelists: Seiichi Aritome
Zvonimir Bandic (Western Digital)
Annie Foong (Intel)
Michael Gaidis (Samsung)
Jonghoon Oh (SK Hynix)
Reception: 5:30 PM
Sponsor: Applied Materials, Inc., USA
3:15 PM
3:40 PM
6:00 PM
Poster Introduction
(See the front page for the list of poster papers)
4:35 PM
5:00 PM
5:25 PM
Banquet
NAND
P. Blomme, IMEC, “Junctionless Array with Ultrathin Poly\TiN Floating Gate and
HfAlO Based Intergate Dielectric for sub-15nm Planar NAND Flash”
N. Papandreou, IBM Research, “Effect of Read Disturb on Incomplete Blocks in
MLC NAND Flash Arrays”
B-J. Yang, National Chiao Tung Univ., “Analytical Model to Evaluate the Role of
Deep Trap State in the Reliability of NAND Flash Memory and its Process
Dependence”
H. Lue, Macronix, “Theoretical Analysis of Planar Flat Floating Gate NAND Flash
Device and Experimental Study of Floating-gate (FG) / Charge-trapping (CT)
Fusion Device for Comprehensive Understanding of Charge Storage and
Operation Principle”
Break (Refreshments Provided)
Session #6 4:10 PM – 5:50 PM
Chairs:
Sung-Yong Chung, SK Hynix, Korea
Randy Koval, Intel, USA
4:10 PM
Poster Session: 6:00 PM – 8:30 PM
Chair: Gill Lee, Applied Materials, USA
PCM
H. Lung, IBM/Macronix, “A Double-Data- Rate 2 (DDR2) Interface Phase-change
Memory with 533MB/s Read -Write Data Rate and 37.5ns Access Latency for
Memory-Type Storage Class Memory Applications”
M. Stanisavljevic, IBM Research, “Demonstration of Reliable Triple-Level-Cell
(TLC) Phase-Change Memory”
G. Navarro, CEA LETI, “N-doping Impact in Optimized Ge-rich Materials Based
Phase-Change Memory”
N. Castellani, CEA LETI, “Comparative Analysis of Program/Read Disturb
Robustness for GeSbTe-Based Phase-Change Memory Devices”
J. Kluge, STMicroelectronics/CEA LETI “High Operating Temperature Reliability
of Optimized Ge-rich GST Wall PCM Devices”
Lunch (On your own)
Session #5 2:00 PM – 3:40 PM
Chairs:
Sung-Yong Chung, SK Hynix, Korea
Klaus Knobloch, Infineon, Germany
2:00 PM
Panel discussion 4:00 PM – 5:30 PM
Chair: Gill Lee, Applied Materials, USA
C. Wu, Macronix, “Device Characteristics of Single-Gate Vertical Channel
(SGVC) 3D NAND Flash Architecture”
S. Lai, Macronix, “A Bottom-Source Single-Gate Vertical Channel (BS-SGVC) 3D
NAND Flash Architecture and Studies of Bottom Source Engineering”
A. Subirats, IMEC, “In Depth Analysis of Post-Program VT Instability After
Electrical Stress in 3D SONOS Memories”
L. Breuil, IMEC, “Improvement of Poly-Si Channel Vertical Charge Trapping
NAND Device Characteristics by High Pressure D2/H2 Annealing”
Break (Refreshments Provided)
Session #4 10:05 AM – 12:10 PM
Chairs:
Gwan-Hyeob Koh, Samsung, Korea
Alfonso Maurelli, ST Microelectronics, Italy
10:05 AM
Session #2 2:00 PM – 3:40 PM
Chairs:
Steve Heinrich-Barna, TI, USA
Takashi Kobayashi, Hitachi, Japan
3D NAND
SSD/Error Management
Y. Yamaga, Chuo University, “Application Optimized Adaptive ECC with
Advanced LDPCs to Resolve Trade-off among Reliability, Performance, and Cost
of Solid-State Drives”
T. Tokutomi, Chuo University, “17x Reliability Enhanced LDPC Code with BurstError Masking and High-Precision LLR for Highly Reliable Solid-State-Drives with
TLC NAND Flash Memory”
H. Yamazawa, Chuo University, “Privacy-Protection SSD with Precision ECC and
Crush Techniques for 15.5× Improved Data-Lifetime Control”
J. Spinner, University of Applied Sciences, Konstanz, Germany, “Construction of
High-Rate Generalized Concatenated Codes for Applications in Non-Volatile
Flash Memories”
7:00 PM - 9:00 PM (provided)
Session #7 8:00 AM – 10:05 AM
Embedded Memory & DRAM
Chairs:
Scott Summerfelt, TI, USA
Jan Van Houdt, IMEC, Belgium
8:00 AM
8:25AM
8:50 AM
9:15 AM
9:40 AM
10:05 AM
Y. Lee , Samsung, “Highly Scalable 2nd Generation 45-nm Split-gate
Embedded Flash with 10-ns Access Time and 1M-Cycling Endurance ”
L.Q. Luo, Global Foundries/Singapore University of Technology and Design,
“Functionality Demonstration of a High-Density 2.5V Self-Aligned Split-Gate
NVM Cell Embedded Into 40nm CMOS Logic Process for Automotive
Microcontrollers”
S. Han, Samsung, “In-depth Analysis of NBTI at 2X nm Node DRAM”
J. A. Rodriguez, Texas Instruments, “High Temperature Data Retention of
Ferroelectric Memory on 130nm and 180nm CMOS”
B. Lacoste, SPINTEC, “Control of Sub-Nanosecond Precessional Magnetic
Switching in STT-MRAM Cells for SRAM Applications”
Break (Refreshments Provided)
Session #8 10:30 AM – 12:10 PM
Chairs:
Hyeong Soo Kim, SK Hynix
Micha Gutman, TowerJazz, Israel
10:30 AM
10:55 AM
11:20 AM
11:45 AM
RRAM-2
K. Chiang, Macronix, “A Si-doped High-Performance WOx Resistance
Memory Using a Novel Field-Enhanced Structure”
N. Gonzales, Adesto, “An Ultra Low-Power Non-Volatile Memory Design
Enabled By Subquantum Conductive-Bridge RAM”
P.C Su, National Chiao-Tung University, “Investigation of Factors Affecting
SET-Disturb Failure Time in a Resistive Switching Memory”
S. Blonkowski, STMicroelectronics, “Fully Analytical Compact Model of
OxRAM based on Joule Heating and Electromigration for DC and Pulsed
Operation”
12:15 PM – 12:35 PM Closing Remarks & Adjourn
12:35 PM Lunch (Provided)