JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.2, APRIL, 2015
http://dx.doi.org/10.5573/JSTS.2015.15.2.312
ISSN(Print) 1598-1657
ISSN(Online) 2233-4866
Decrease of Parasitic Capacitance for Improvement of
RF Performance of Multi-finger MOSFETs in 90-nm
CMOS Technology
Seong-Yong Jang, Sung-Kyu Kwon, Jong-Kwan Shin, Jae-Nam Yu, Sun-Ho Oh, Jin-Woong Jeong,
Hyeong-Sub Song, Choul-Young Kim, Ga-Won Lee, and Hi-Deok Lee*
Abstract—In this paper, the RF characteristics of
multi-finger MOSFETs were improved by decreasing
the parasitic capacitance in spite of increased gate
resistance in a 90-nm CMOS technology. Two types of
device structures were designed to compare the
parasitic capacitance in the gate-to-source (Cgs) and
gate-to-drain (Cgd) configurations. The radio
frequency (RF) performance of multi-finger
MOSFETs, such as cut-off frequency (fT) and
maximum-oscillation frequency (fmax) improved by
approximately 10% by reducing the parasitic
capacitance about 8.2% while maintaining the DC
performance.
technology has continued to scale down, the effect of
external parasitic capacitance components has become
more pronounced, particularly when the devices operate
in a high-frequency range [4-6]. That is, the external
parasitic capacitances due to the interconnection lines
can deteriorate the RF performance. Therefore, to
improve the RF performance of multi-finger MOSFETs,
we must reduce the parasitic capacitance.
In this paper, we investigated the effect of the routing
of interconnect lines on the RF characteristics of 90 nm
MOSFETs using gate-to-drain and gate-to-source
parasitic capacitances.
II. EXPERIMENTAL DETAILS
Index Terms—Multi-finger MOSFET, layout, cut-off
frequency (fT), parasitic capacitance, RF performance
I. INTRODUCTION
The continuous scaling down in CMOS technology
has resulted in a dramatic improvement in radio-frequency
(RF) performance of multi-finger MOS transistors [1, 2].
Both high cut-off frequency (fT) and high maximumoscillation frequency (fmax) characteristics have been
realized in RF circuit designs [3]. However, as CMOS
Manuscript received Aug. 25, 2014; accepted Mar. 10, 2015
A part of this work was presented in the Asia-Pacific Workshop on
Fundamentals and Applications of Advanced Semiconductor Devices
in Kanazawa, Japan, in July 2014.
Dept. of Electronics Engineering, Chungnam National University,
Daejeon 305-764, Korea
E-mail : hdlee@cnu.ac.kr
The multi-finger nMOSFETs used in this experiment
were fabricated using a 90-nm CMOS technology. The
sizes of the fabricated devices were fixed to a unit width
of 2.5 μm and a unit length of 90 nm (Nfinger = 16). Fig.
1(a) shows the layout of a meander-type gate structure
(Device A), whereas Fig. 1(b) shows a ring-type gate
structure (Device B). Device A has a conventional multifinger MOS structure used in industrial field for low gate
resistance. That is, the gate layer was connected both to
the top and bottom regions to reduce the parasitic gate
resistance which affects the performance of fmax. For this
connection, a Metal 2 layer around the active region was
necessary, as shown in Fig. 1(a). However, the crosssectional views along B–B' and C–C' in Fig. 1 show that
the capacitance components of the gate-to-drain (Cgd)
and gate-to-source (Cgs) were abundantly generated
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.2, APRIL, 2015
313
(a)
(b)
Fig. 1. Two device types used in the analysis of the layout effect (a) Device A, (b) Device B.
(a)
(b)
Fig. 2. Cross-sectional views along A–A', B–B', and C–C' of (a) Device A. (b) Device B.
30
25
Device A
Device B
20
gm [mS]
because of the Metal 2 layer of the gate-to-metal contact,
as shown in Fig. 2(a). To realize improved RF
performance, we must minimize the parasitic capacitance
components such as Cgd and Cgs. Therefore, we proposed
Device B structure with removal of the circular-shaped
Metal 2 layer, which is employed for the gate-to-metal
contact. Then, to reduce the possible fluctuation in the
RC delay among the gate lines, we considered a ringtype tied gate structure at the drain side, as shown in Fig.
1(b). Because a metal-overlap region no longer exists
between the gate metallization of Device A, the Metal 3
layer of the source was replaced by the Metal 2 layer of
Device B.
15
10
5
0
0.2
0.4
0.6
0.8
1.0
1.2
VG [V]
Fig. 3. Transconductance (gm) as function of the gate bias of
Devices A and B at VDS = 1.2 V. Two devices show little
difference of DC characteristics.
III. RESULTS AND DISCUSSION
To confirm the DC performance of the MOSFETs, the
transconductance values were compared, as shown in Fig.
3. The maximum transconductance values of Devices A
314
SEONG-YONG JANG et al : DECREASE OF PARASITIC CAPACITANCE FOR IMPROVEMENT OF RF PERFORMANCE OF …
80
60
50
75
MAG
30
H21
20
10
0
70
fmax (GHz)
Gain (dB)
40
65
60
Device A
Device B
1
55
10
Frequency (GHz)
50
100
Fig. 4. Current gain (H21) and MAG as a function of frequency
of Devices A and B. VDS = 1.2 V and VGS = 0.9 V. W/L = 2.5
µm/90 nm.
Device A
Device B
0.6
0.7
0.8
0.9 1.0
VG (V)
1.1
1.2
(a)
105
100
 =


  + 

)( +  
90
85
80
75
Device A
Device B
0.6
0.7
0.8
0.9 1.0
VG (V)
1.1
1.2
(b)
Fig. 5. Comparison of the RF performance as a function of the
gate bias at VDS = 1.2 V (a) fmax, (b) fT.
(1)

  =
95
fT (GHz)
and B exhibited a small difference of approximately
0.66% at VGS = 0.9 V (that of Device A was 25.65 mS
and that of Device B was 25.82 mS). Then, the RF
characteristics were investigated using an Agilent
E8361A network analyzer at frequencies from 0.1–20
GHz. To obtain accurate estimates, we carried out an
“open–short” two-step de-embedding method. fT and fmax
of the devices can be expressed using the following
equations :
(2)
where gm is the transconductance; Cgs and Cds are the
gate-to-source
and
gate-to-drain
capacitances,
respectively; Rg is the gate resistance; and gds is the
output conductance. Fig. 4 shows the current gain (H21)
and maximum available gain (MAG) versus frequency.
fT is proportionally related to the transconductance [7].
The maximum value of fT was estimated at maximum
transconductance. Device B has an fT value of
approximately 100 GHz, which was a 10% improvement
over Device A. The other RF property fmax improved by
approximately 9% (the Device A fT value was 64.5 GHz,
whereas that of Device B was 70.6 GHz), which implies
that there is little increase of parasitic gate resistance for
Device B. Fig. 5(a) shows fmax, and Fig. 5(b) shows the fT
versus gate bias curve. fT initially increased as the gate
bias increased. Then, fT decreased after a gate bias of 0.9
V when the transconductance of the multi-finger
MOSFETs decreased. This result shows totally improved
RF performance of Device B.
According to the analytical expression, parasitic
capacitances Cgs and Cgd can be extracted from the
converted S-parameters to the imaginary part of the Yparameters, as expressed by the following [8, 9]:
 =
 ( +  )

 = −
(3)
 ( )

(4)
The extracted parasitic capacitances of Device A were
compared with those of Device B, as shown in Fig. 6.
Compared with that in Device A, Cgs in Device B was
reduced by approximately 4%; Cgd was reduced by
approximately 18%. The Cgd component was
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.2, APRIL, 2015
parasitic gate resistance increased. We thus confirmed
that reducing the parasitic components is a very effective
method in improving the RF performance of multi-finger
MOSFETs in the 90-nm CMOS technology. Therefore,
choosing gate-layout geometries to minimize the
parasitic capacitance is critical in high-performance RF
IC applications.
50
Cgs
Capacitance (fF)
40
30
20
Cgd
10
0
Device A
Device B
0
5
10
15
Frequency (GHz)
105
fT (GHz)
VGS= 0.9V
85
80
44
This work was supported by the IT R&D program of
MKE/KEIT (10041855, Development of e-NVM
[embedded Non-Volatile Memory] analog mixed signalbased convergence process technology & IP).
REFERENCES
VGS= 1.0V
VGS= 1.1V
VGS= 1.2V
95
90
ACKNOWLEDGMENTS
20
Fig. 6. Parasitic capacitances of Devices A and B as a function
of frequency VDS = 1.2 V and VGS= 0.9 V. W/L = 2.5 µm/90 nm.
100
[1]
VGS= 0.8V
VGS= 0.7V
VGS= 0.6V
Device A
Device B
46
48
50
52
Parasitic Capacitance (fF)
315
54
[2]
Fig. 7. Comparison of fT versus parasitic capacitance at VDS =
1.2 V. W/L = 2.5 µm/90 nm.
considerably reduced for the proposed structure.
Fig. 7 shows fT versus parasitic capacitance Cgs and Cds
under a gate bias. Ctotal (Cgs + Cds) was reduced by
approximately 8.2%. These results shows that the RF
performance of multi-finger MOSFETs strongly depends
on the parasitic capacitance between the interconnection
of the metal line and gate polysilicon. As mentioned
earlier, the difference in the reduced parasitic capacitance
under the same gate bias (gm remains unchanged) clearly
contributes to better fT in multi-finger MOSFETs.
[3]
[4]
[5]
IV. CONCLUSIONS
In this paper, the gate-to-source and gate-to-drain
parasitic capacitances were decreased by modified
routing of interconnection lines of multi-finger
MOSFETs. As a result, the RF performance (fT and fmax)
improved by approximately 10% by reducing the
parasitic capacitance (approximately 8.2%) although the
[6]
C. H. Doan, S. Emami, A. M. Niknejad, and R. W.
Brodersen, “Millimeter-wave CMOS design,”
IEEE J. Solid-State Circuits, vol. 40, no. 1, pp.
144–155, Jan. 2005.
E. Morifuji, H. S. Momose, T. Ohguro, T.
Yoshitomi, H. Kimijima, F. Matsuoka, M.
Kinugawa, Y. Katsumata, and H. Iwai, “Future
perspective and scaling down roadmap for RF
CMOS,” in VLSI Symp. Tech. Dig., pp. 165–166,
1999.
P. H. Woerlee, M. J. Knitel, R. V. Langevelde, D.
B. M. Klaassen, L. F. Tiemeijer, A. J. Scholten, and
T. A. Z. Dhuijnhoven, “RF-CMOS Performance
Trends,” IEEE Trans. Electron Devices, vol.48,
no.8, pp.1776-1782, Aug. 2001.
C. Y. Chan, S. C. Chen, M. H. Tsai, and S. S. H.
Hsu, “Wiring effect optimization in 65-nm lowpower NMOS,” IEEE Electron Device Lett., vol.
29, no. 11, pp. 1245–1248, Nov. 2008.
H. S. Jhon, J. H. Lee, J. Lee, B. C. Oh, I. H. Song,
Y. Yun, B. G. Park, J. D. Lee, and H. C. Shin, “fmax
Improvement by Controlling Extrinsic Parasitics in
Circuit-Level MOS Transistor,” IEEE Electron
Device Lett., vol. 30, no. 12, pp. 1323–1325, Dec.
2009.
A. Nakamura, N. Yoshikawa, T. Miyazako, T.
Oishi, “Layout optimization of RF CMOS in the 90
nm generation by a physics-based model including
the multi-finger wiring effect,” in IEEE Radio Freq.
316
[7]
[8]
[9]
SEONG-YONG JANG et al : DECREASE OF PARASITIC CAPACITANCE FOR IMPROVEMENT OF RF PERFORMANCE OF …
Integrated Circuits Symp., pp. 419-422, June. 2006,
W. K. Yeh, C. C. Ku, S. M. Chen, Y. K. Fang, and
C. P. Chao, “Effect of Extrinsic Impedance and
Parasitic Capacitance on Figure of Merit of RF
MOSFET,” IEEE Trans. Electron Devices, vol.52,
no.9, pp.2054-2060, Sep. 2005.
S. Lee and H. K. Yu, “Parameter extraction
technique for the small signal equivalent circuit
model of microwave silicon MOSFETs,” in Proc.
High Speed Semicond. Dev. Circuits, pp. 182–199,
1997.
I. Kwon, M. Je, K. Lee, and H. Shin, “A simple and
analytical parameter extraction method of a
microwave MOSFET,” IEEE Trans. Microw.
Theory Tech., vol. 50, no. 6, pp. 1503–1509, Jun.
2002.
Seong-Yong Jang received the B.S.
degree in Electronics Engineering, in
2013, and is currently working
toward the M.S. degree in the Dept.
of Electronics Engineering from the
Chungnam National University,
Daejeon, Korea. His main research
interests include characterization of RF CMOS and
modeling.
Sung-Kyu Kwon received the B.S.
degree and M.S. degree in electronics
engineering from the Chungnam
National University, Daejeon, Korea
in 2011 and 2013. Since 2013, he has
been a Ph.D. student in electronics
engineering from the Chungnam
National University, Daejeon, Korea. His main research
interests include reliability and low frequency noise
characteristics of nano-CMOS devices for analog mixed
signal application. His research interest also includes
research of test pattern for matching and low frequency
noise characteristics in analog mixed signal application.
Jong-Kwan Shin received the B.S.
degree in Electronics Engineering, in
2012, and is currently working
toward the M.S. degree in the Dept.
of Electronics Engineering from the
Chungnam National University,
Daejeon, Korea. His main research
interests include characterization of RF CMOS and
modeling.
Jae-Nam Yu received the B.S.
degree in Electronics Engineering, in
2012, and is currently working
toward the M.S. degree in the Dept.
of Electronics Engineering from the
Chungnam National University,
Daejeon, Korea. His main research
interests include reliability and low frequency noise
characteristics of CMOS devices for analog mixed signal
application. His research interest also includes research
of test pattern for matching and low frequency noise
characteristics of CMOS and Si-based high-κ devices in
analog mixed signal application.
Sun-Ho Oh received the B.S. degree
in Electronics Engineering, in 2013,
and is currently working toward the
M.S. degree in the Dept. of
Electronics Engineering from the
Chungnam National University,
Daejeon, Korea. His main research
interests include a study on reliability mechanism (NBTI,
HCI) and low frequency noise characteristics of CMOS
and Si-based high-κ devices for analog mixed signal.
Jin-Woong Jeong received the B.S.
degree in Electronics Engineering, in
2014, and is currently working toward
the M.S. degree in the Dept. of
Electronics Engineering from the
Chungnam National University,
Daejeon, Korea. His main research
interests include characterization of RF CMOS and
modeling.
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.2, APRIL, 2015
Hyeong-Sub Song received the B.S.
degree in Electronics Engineering, in
2014, and is currently working
toward the M.S. degree in the Dept.
of Electronics Engineering from the
Chungnam National University,
Daejeon, Korea. His main research
interests include a study on reliability mechanism (NBTI,
HCI) and low frequency noise characteristics of CMOS
and Si-based high-κ devices for analog mixed signal.
Choul-Young Kim received the B.S.
degree in electrical engineering from
Chungnam
National
University
(CNU), Daejeon, Korea, in 2002 and
M.S. and Ph.D degrees in electrical
engineering from Korea Advanced
Institute of Science and Technology
(KAIST), Daejeon, Korea, in 2004 and 2008,
respectively. From March 2009 to February 2011, he was
a Postdoctoral Research Fellow at the department of
electrical and computer engineering at the University of
California, San Diego (UCSD). He is assistant professor
of electronics engineering at Chungnam National
University, Daejeon, Korea. His research interests
include mm-wave integrated circuits and systems for
short range radar and phased-array antenna applications.
Ga-Won Lee received a B.S., M.S.,
and Ph.D. degrees in Electrical
Engineering from Korea Advanced
Institute of Science and Technology
(KAIST), Daejeon, Korea, in 1994,
1996, and 1999, respectively. In1999,
she joined Hynix Semiconductor Ltd.
(currently SK Hynix Semiconductor Ltd.) as a senior
research engineer, where she was involved in the
development of 0.11-μm, 0.09-μm DDRII DRAM
technologies. Since 2005, she has been at Chungnam
National University, Daejeon, Korea, as an Associate
Professor with the Department of Electronics
Engineering. Her main research fields are flash memory,
flexible display technology including fabrication,
electrical analysis, and modeling.
317
Hi-Deok Lee received the B. S., M.
S. and Ph. D. degrees from Korea
Advanced Institute of Science and
Technology (KAIST), Daejeon,
Korea, in 1990, 1992, and 1996,
respectively, all in electrical engineering. In 1996, he was with the LG
Semicon Company, Ltd. (currently SK Hynix
Semiconductor Ltd.), Chongju, Korea, where he was
involved in the development of 0.35-, 0.25-, and 0.18-μm
CMOS technologies, respectively. He was also
responsible for the development of 0.15- and 0.13-μm
CMOS technologies. Since 2001, he has been with
Chungnam National University, Daejeon, as an Assistant
Professor with the Department of Electronics Engineering. From 2006 to 2008, he was with the University
of Texas, Austin, and SEMATECH, Austin, as a Visiting
Scholar. His research interests are nanoscale CMOS
technology and its reliability physics, silicide technology,
and test element group design. His research interests also
include RF CMOS device modeling, circuit design, cross
talk, and time delay modeling of interconnection lines.
Dr. Lee is a member of the Institute of Electronics
Engineers of Korea. He received the Excellent Professor
Award from Chungnam National University in 2001,
2003 and 2014.