Multi-Channel Controller
Purpose:
• The multi-channel controller transports data between a multiplexed data stream and
channel data buffers using a user defined format. For a complete understanding of this
section, a good understanding of the serial interface is required. If you haven’t already
done so, it is advisable to study that module first.
Objectives:
• There are a number of parameters and registers that are used by the MCC to control the
operation. This module will explain the functionality of those features as well as how to
configure them in multiple receive/transmit routing and control situations.
Contents:
• The basic fundamentals of the MCC followed by transmit and receive examples for
parameters and registers. The module is concluded by an exercise.
Learning Time:
• There are 22 pages in this module with 16 reference pages, which will take approximately
41 minutes.
The multi-channel controller transports data between a multiplexed data stream and channel data buffers using a
user defined format. For a complete understanding of this section, a good understanding of the serial interface is
required. If you haven’t already done so, it is advisable to study that module first.
There are a number of parameters and registers that are used by the MCC to control the operation. This module
will explain the functionality of those features as well as how to configure them in multiple receive/transmit
routing and control situations.
The contents of this module include the basic fundamentals of the MCC followed by
transmit and receive examples for parameters and registers. The module is concluded by an exercise.
There are 22 pages in this module with 16 reference pages, which will take approximately 41 minutes.
1
Multi-Channel Controller
• Two identical multi-channel controllers support a maximum of 256 channels.
• MCC1 connects through SI1 for channels 0 - 127
• MCC2 connects through SI2 for channels 128 - 255.
There are two identical Multi-channel Controllers supporting a maximum of
256 channels.
MCC1 connects through serial interface one for channels 0- 127.
MCC2 connects through serial interface two for channels 128-255.
2
MCC Key Features
• Supports up to 128 serial, full duplex channels
• Can be divided into up to 4 subgroups of 32 fixed channels
• Independent mapping for receive and transmit
• Interrupt support per channel using circular queues
• External buffer descriptor tables per channel
• 64-bit data transactions for buffer descriptor access
• HDLC or transparent protocol per channel
• Supports super-channel synchronization
• Supports in-line synchronization in transparent mode
The multi-channel controllers each offer the following key features:
Support up to 128 serial, full duplex channels.
Can be divided into up to four subgroups of 32 fixed channels.
Independent mapping for receive and transmit.
Interrupt support per channel using circular queues.
External buffer descriptor tables per channel.
64-bit data transactions for buffer descriptor access.
HDLC or transparent protocol per channel.
Supports super-channel synchronization.
Supports in-line synchronization in transparent mode.
3
Connections
MCCFn
SIRAMn
Channels 0 - 31
Channels
Channels128
0 - -31
159
TDMna
Channels 32
0 --31
63
Channels
Channels160
0 - -31
191
Serial Data
TDMnb
TDMnc
Channels 64
0 --31
95
Channels
Channels192
0 - -31
223
TDMnd
Channels
Channels96
0 - 127
31
Channels
Channels224
0 - -31
255
This diagram provides a basic indication of how a controller can be connected and the associated controls.
The basic operation of the MCC is to take serially multiplexed data , collect it into bytes and route it to the
required channel. On the left are indicated the four possible serial connections available to each MCC
connected through the four time division multiplexers. Each one of four groups of channels can be connected
to any TDM selected in the MCCF register and each connection is independently controlled, so there is a
completely free choice. All the channels could be connected to one TDM or any combination.
The channels are in fixed groups of 32. For MCC1, the groups are channels 0-31, 32-63, 64-95, and 96-127.
MCC2 groups are 128-159, 160-191, 192-223, and 224-255. Channel routing and control is handled by the
SIRAM, as shown in the serial interface module. The lower case n appended to the MCCF register and
SIRAM indicates that there is one of each for each MCC. This also applies to the TDM’s and the a, b, c, d,
appended to those indicates the four available for each MCC.
4
Example Operation
Serial Interface
SIRAM (channel Route)
Data_p
Data_q
Data_r
Data_s
TDM
Data_t
Data_u
Data_v Data_w Data_x
Data_y
Buffer Descriptors
MCC
Ch.69
Ch.74
Ch.69
Ch.74
Ch.81
Ch.90
Parameters
Buffers
Ch.81
Ch.90
Data in the time slot is directed to or
from the appropriate channel buffer.
This example is a simple demonstration of what the MCC does to help understand the basic principles. This example
only covers the receive process but transmit is basically the same in reverse. At the top is a representation of the TDM
with the data stream shown in groups of bytes. The TDM receives the serial data and groups it into bytes and the
SIRAM associated with it defines the channel that each byte is allocated to. All of this block is controlled by the serial
interface. The timing is represented by data blocks from left to right, such that the green block, data P, is the first byte
received. To simplify the description the data has been defined as P-Y to indicate the order. For this example only four
channels are indicated. In this case, channels 69, 74, 81 and 90 and they are color coded blue, green, pink, and tan.
The MCC has parameters which enable it to control data flow from the serial interface to the appropriate buffers.
The first byte received is allocated by the SIRAM to channel 74 and passed to the MCC, which accesses the
parameters for this channel finds the appropriate buffer descriptor for channel 74, and then transfers the data to the
current buffer for that channel according to all the other controls provided.
The next byte is processed by the TDM and this time is directed to channel ninety. The control is handed to the MCC,
which accesses the parameters for channel 90, finds the appropriate BD and transfers the data to the next location in
the current buffer for channel 90.
The next byte is processed in the same way and the data transferred to the current buffer for channel 69 and in this
case the TDM recognizes that this is the end of a frame and so that buffer is closed and any following data for that
channel will be directed to the next buffer.
This process continues for all the data as it is received, the MCC passing the data directed a specific channel to the
appropriate buffer. The net result, as shown here, is that as data is received it is collected into the appropriate buffer for
the channel it is directed to, so that over a period of time the full message for each channel is combined to the same
form as the original.
5
Basic MCC Parameters
Internal Memory
Programming involves :
Channel Specific Parameters
Channel Extra Parameters
Superchannel Transmit Table
+0x8700
MCC1 Global Parameters
+0x8800
MCC2 Global Parameters
Registers
MCCF, MCCE, MCCM
SIRAM
• One set of global parameters at a
predefined location in DPRAM that relate
to all channels
• Channel-specific parameters for each
channel control and run time variables
• Channel-specific extra parameters
providing pointers to buffer descriptors in
external memory for each channel
• Receive and transmit interrupt tables
located in external memory defined by
global parameters
• When required, a superchannel table
located in DPRAM and defined by global
parameters
• Three registers-MCCFn (configuration),
MCCEn, and MCCMn
• SIRAM defining channel routing
The MCC uses a number of parameters and registers to control the operation. This
shows the basic groups. There is one set of Global Parameters at a predefined
location in DPRAM that relate to all channels. These relate to functions that are
constant for all channels, and include pointers to the other parameters and functions
required. There are channel Specific parameters for each channel control and run
time variables. Channel specific Extra Parameters providing pointers to Buffer
Descriptors in external memory for each channel. Receive and Transmit Interrupt
Tables located in external Memory defined by Global Parameters. When required, a
Super-channel Table is located in DPRAM and defined by Global parameters.
Three registers, MCCF, MCCE, and MCCM are used for each controller to define
the configuration, register events, and enable events to generate interrupt requests.
SIRAM is a function of the serial interface defining Channel routing, but when
selected to control the MCC, it takes on a slightly different format from the normal
serial interface. Notice that the global parameters are located and the fixed offset in
dual port ram of hex 8700 for MCC1 and hex 8800 for MCC2.
6
Buffer Descriptors Pointers
External Memory
Internal Memory
Channel Extra Parameters
TBASE0
TBPTR0
RBASE0
Buffer Descriptors
Channel 0 TxBDs
RBPTR0
RBASE255
Channel 0 RxBDs
RBPTR255
..
..
.
Global Parameters
Channel 255 RxBDs
MCCBASE
XTRABASE
512 Kb
As always buffer control is handled by using buffer descriptors. In this case, there is a set of transmit and
receive buffer descriptors required for each channel to be used. The pointers to the buffer descriptors are
provided in the channel extra parameters, which provide an offset to the top of each BD chain for that
channel and an offset to the current or next BD. In this diagram, only channel one transmit buffer descriptors
are shown, but BDs for all channels are required.
Buffer descriptors are located in a block of up to 512Kb in external memory pointed to by the global
parameter MCC base. The extra parameters are located in dual port ram by the global parameter extra
base. To examine the channel extra parameters, global parameters, or buffer descriptors, click on the block
of interest.
7
Channel-Specific Parameters
Internal Memory
DPR_base
Ch.0 Specific Parameters
Ch.1 Specific Parameters
Ch.2 Specific Parameters
Ch.3 Specific Parameters
• These parameters provide all the basic
channel-specific control information
and run-time variables to handle each
individual channel
• The parameters are located at the top
of DPRAM and each set is located at
DPR_base+64*ch_number
Ch.255 Specific Parameters
• If channels are not used, that area of
DPRAM can be used for alternative
purposes
Channel Extra Parameters
Global Parameters
The channel specific parameters provide all the basic channel specific control information and
run time variables for the CP to handle each individual channel. Each set of channel specific
parameters are 64 byte long. They are located at the top of dual port ram and each set is
located at DPR base plus 64 times the channel number. Where any channels are not used,
that area of dual port ram can be used for alternative purposes. To view any of the
parameters click on the block of interest.
8
Registers (One for each MCC)
0
7
MCCF
MCC Configuration Register – Maps the MCC channels to TDM channels and
this defines which group of 32 channels is routed through each TDM
0
15
MCCE
MCC Event Register – Reports events generated in the interrupt queue
0
15
MCCM
MCC Mask Register – Enables events to be reported to the interrupt controller
There are three registers for each of the multi channel controllers. MCCF is
the configuration register which maps the channel groups to the TDM
through which they are transferred. MCCE is the event register where events
relevant to the MCC are recorded and MCCM is the associated register that
enables events to generate an interrupt request. To view any of these
registers click on the one of interest.
9
Superchannel
• A “superchannel” is a channel that which has several time slots assigned to it.
Example Frame
1
24
T1 Frame
Typically, one time slot is
routed to one channel
In some cases, a subscriber requires
several time slots.
• The programming of receiver superchannels is only required for transparent mode requiring
slot synchronization.
• HDLC is more efficient when programmed without using the specific superchannel option.
A super-channel is simply one where more than one byte of data in the data stream
is associated with the single channel. This example shows a T1 frame and the
highlighted bytes are handled by a single channel. That is termed a super-channel.
The controller has a specific super-channel control option but this should only be
used for receivers using transparent mode and requiring slot synchronization.
HDLC mode is more efficient not using this special option. Transmitters using
super-channels must always use this mode.
10
SI RAM entries for TDM
0
1
2
1
LO
OP
SUP
3
4
Superchannel entry
(all 1 byte entries)
Loop/Echo
MCC use
Route data via MCC
5
6
7
8
MCSEL
MCC Channel Select
Which channel data is
routed to
0-127 for SI1
128-255 for SI2
9
10
11
12
13
CNT
14
15
BYT
LST
Count
If SUP = 0
1 - 8 bits/bytes
If SUP = 1
CNT+BYT = :
0001:this is first byte
1110:not first byte
Byte Resolution
0 = bit
1 = byte
Last Entry
(must be in odd entry)
wait for next sync
Reference Manual section 14.4.3
This diagram shows the programming functions of the SIRAM entries when the serial interface is used for
the MCC, which is when bit zero of the entry is set. For a complete explanation of the serial interface, study
the serial interface module.
The specific functions that have a special relationship for MCC, use the channel selection, super-channel
selector, and the count when super-channel is selected. For MCC1, the options for the channel selection are
0-127, and for MCC2, channels 128-255. The data associated with this time slot is handled by the channel
selected here. If the special super-channel function is selected by setting bit two then the data associated
with this time slot is an 8- bit value and is routed differently from usual by using an additional feature known
as the super-channel table. In that case, the function in the entry normally used for defining the data size is
used to define whether this slot contains the first byte of the frame.
The reason for that is slot synchronization, which is associated with super-channels, requires that new
frames should be directed to a new buffer. When the receiver detects the first byte of a new frame it
automatically closes the current buffer and opens a new one. When a super-channel is not selected, then
the data size is defined by the count and resolution functions, which enables selection of anything between
1- bit and 8- bytes by using a fiddle factor of adding one the content of the count.
The controller works it’s way through each entry of the SIRAM until it reaches the one defined as the last.
That is the end of the frame, and the controller then waits for the next sync pulse when it resets to the first
entry and repeats the process. The loop bit enables the data associated with this time slot to be internally
connected to the receiver or transmitter for loop-back or echo.
11
Example SI_RAM for Receive
(with Superchannels Requiring Slot Sync)
Time Slots
Channel Numbers
SIxRAM
1
10
5
24
1 5 2 3 5 2 4 5 2 6 7
20
Time slot
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
10 1
11 1
12 1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
1
1
0
0
0
00000001
00000101
00000010
00000011
00000101
00000010
00000100
00000101
00000010
00000110
00000111
00001000
000
000
000
000
111
111
000
111
111
000
000
000
1
1
1
1
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
00010010
00010011
00010100
000
000
000
1
1
1
0
0
1
22
23
24
Start new buffer
Start new buffer
When superchannels are used, Rx and Tx SIRAM must be programmed the same way.
This example shows how the SIRAM is initialized for the frame organization indicated at the top. The frame is shown as 24
time slots of one byte each. Generally each time slot is associated with an individual channel, but only twenty channels are
used, and channels two and five are super-channels.
The first slot is for channel one, the second for channel five which is a super-channel, the next for channel two which is also
a super-channel. The next is for channel three followed again by two slots for channel five and two. After channel four, there
are another pair of channel five and two. All the remainder of the time slots relate to channels 6-20 in ascending order. To
obtain the necessary control for this frame the SIRAM entries are shown below. The first time slot entry is not for a superchannel and so bit one is clear. The data is intended for channel one and so the value one is programmed in M channel. The
data is one byte and so the count is shown as zero which the fiddle factor makes one, and the resolution is defined as byte.
Alternatively, this could have been defined as 8-bits by programming 7 into the count and zero in the resolution. It’s not the
end of the frame so bit fifteen is clear. The second entry is for a super-channel and so bit two is set, and the channel number
is five. This is the first byte for this channel in this frame and so the count and resolution is initialized to 0001 which will result
in this byte being sent to a new buffer. Entry three is also a super-channel and so that bit is set. It’s for channel two so that is
the channel number and once again, it’s the first byte in the frame for channel two so the count and resolution is
programmed for that. That will result in that byte being sent to a new buffer for channel two. Entry four is for a standard
channel, channel three, so the super-channel bit is clear and the count and resolution is defined as one byte.
The remainder of the programming follows the same structure except the remainder of the super-channels have the count
and resolution initialized to 1110 indicating that they are not the first byte of the frame and therefore the byte will be sent to
the same buffer as the previous one unless the buffer is full. As you can see, the last entry has bit 15 set indicating to the
controller that is the last entry. The result will be that for every frame received the data will be sent to the channels specified,
but in the case of channel two and five a new buffer will be opened for each TDM frame. The data for the other channels will
be loaded into buffers in the normal way, being controlled by the buffers and the higher level framing. When super-channels
are used both receive and transmit SIRAM must be programmed the same.
12
Superchannel Table
Superchannel Table
• The superchannel table consists of 16-bit
entries where bits 2 - 9 provide the 8-bit
channel number.
• This must be programmed for superchannel
transmitters requiring slot synchronization.
Global Parameters
+0x24
SCTPBASE
• When the SUP bit of the SIRAM is set, then
the value in the MCSEL bits is an entry
offset into the superchannel table, and the
channel number there indicates the actual
channel for this data.
• Entries in the Table which align to
non-superchannel entries in SIRAM
must be left vacant.
Superchannel Table Entry
9
15
0
2
0 0 0 Channel
0 0 0 0 0 0 0 0 0 0
0 0 0 Number
Reference Manual section 27.5
The super-channel table consists of sixteen bit entries where bits 2-9 provide the 8-bit
channel number. This must be programmed for super-channel transmitters requiring slot
synchronization. When the SUP bit of the SIRAM is set then the value in the MC select
bits is an entry offset into the super-channel table and the channel number there
indicates the actual channel for this data. In other words, the channel numbers are
located in a separate table in an entry defined by the SIRAM channel number. Entries in
the table which align to non-super-channel entries in SI ram must be left vacant. The
super-channel table must be located in dual port ram with a pointer in the global
parameters as an offset from the top. An entry for the table is shown below.
13
Example Initialization for Transmit
(with Superchannels Requiring Slot Sync)
Time Slots
Channel Numbers
Time Slot
1 1
2 1
3 1
4 1
5 1
6 1
7 1
8 1
9 1
10 1
11 1
12 1
1
10
5
1 5 2 3 5 2 4 5 2 6 7
SIxRAM
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
1
1
0
0
0
1
0
2
3
5
21
4
22
23
6
7
8
1
1
1
1
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1 0 0
1 0 0
1 0 0
18
19
20
000
000
000
1 0
1 0
1 1
20
Superchannel Table
Entry
0
5
1
2
2
3
4
5
5
6
7
8
9
10
11
=
000
000
000
000
111
111
000
111
111
000
000
000
==
22
23
24
24
20
21
22
23
2
5
2
Exercise
This example will help in understanding how the super-channel table is used and how to set it up. The only reason the
super-channel table is necessary is because at least one slot of the TDM frame is to be a super-channel requiring slot
synchronization. If that is not needed, then the table is not required and the channels can simply be controlled by the
SIRAM entry.
The TDM frame has the same structure used for the previous example and so you might expect the SIRAM entries to
be the same, however, you can see that is not the case for some of the super-channels. On the previous slide, there
was a rule specified that entries in the table which align to non-super-channel entries in SIRAM must be left vacant.
Then to build the table all non-super-channels, that is channels one, three, four, and six through twenty, must have the
associated entry in the table vacant, so the table is built with those entries clear. Channel zero is not used, and
channels two and five are super-channels and so those entries can be used.
The SIRAM is programmed for all the non-super-channels as required and the only consideration here is the
programming of the SIRAM entries for channels two and five, and the super-channel table. The first super-channel is
channel five, and so the channel select can be directed to the first unused entry in the table, which in this example is
entry zero. The value zero is programmed into that SI, ram entry, and entry zero in the table is loaded with five,
directing the data to channel five.
The next super-channel is two and the next available entry in the table is two, so two is loaded into both the SIRAM
channel select and entry two in the table, although the fact that this time slot data is for channel two is purely
coincidence as far as the SIRAM is concerned. The same applies for the next incidence of channel five and both SI,
ram and the table entry five are programmed with five.Now all the remaining entries in the table up to twenty cannot
be used, so the next available entry is twenty one.
The next super-channel pointer, which is two, must be entered into the next available table entry, twenty-one, and the
table entry number loaded into the SIRAM for that super-channel. The remaining super-channels are initialized
accordingly into table entries 22 and three. The remainder of the initialization is as normal. To test your understanding
of how this works click on the exercise button which will provide you with an exercise to perform and a result for you
to check against.
14
Interrupt Circular Queue
• The interrupt circular queue is a structure in memory where
interrupt information is stored when a channel event occurs.
INTBASE
CPU Pointer
INTPTR
V
0
0
0
1
1
1
1
0
0
0
W
0
0
0
0
0
0
0
0
0
1
Events
Events
Events
Events
Events
Events
Events
Events
Events
Events
32-bits
Ch. Number
Ch. Number
Ch. Number
Ch. Number
Ch. Number
Ch. Number
Ch. Number
Ch. Number
Ch. Number
Ch. Number
– There are 5 base pointers, one for Tx
and four for Rx. These are global
parameters defining locations in
external memory.
– For each table there is a current entry
pointer (global parameter) used by the
CP for writing new information.
– The ‘V’ bit is used by the CP to
indicate an updated entry.
– The CPU must keep track of updated
entries.
• When a channel event occurs, the information is written to the location defined
by INTPTR (if V = 0), ‘V’ is set, INTPTR increments , and the appropriate bit in
the event register is sets which can generate an Interrupt.
• The CPU must keep track of the queue and clear ‘V’ for each entry serviced by
the interrupt service routine.
For some of the simpler controllers there is an event register to record events and provide the option to
generate interrupt requests. The same requirements are necessary for the MCC but for each channel, and
since it’s possible to have up to 256 channels, a similar process would require the same number of event
registers. To alleviate that the event registers are provided as a table of entries in memory defined as the
interrupt queue, providing the same recording options for events and includes an entry for the channel that
the entry relates to. It also provides a mechanism for servicing the queue appropriately. An event register is
still used but only one, and this is used to indicate the type of event generated, and with the mask register
enables an interrupt request to the core.
A single interrupt queue is required for the transmitter but it’s possible to use up to four queues for the
receiver, providing some flexibility for servicing receiver events. There are five base pointers provided in
parameter ram, one for transmit and four for receive. These are global parameters defining locations in
External memory.
An interrupt queue table is shown here. For each table there is a current entry pointer as a global parameter
used by the CP for writing new information into the queue. The V-bit is used by the CP for indicating an
updated entry. This is to enable the interrupt service routine to find entries requiring action and to prevent an
entry that hasn’t been serviced from being overwritten. The wrap bit indicates the end of the table so that
when all the entries in the queue have been used the controller wraps back to the top of the table. The CPU
must keep track of updated entries, and so the service routine must keep a pointer to the last entry serviced
or the next to be serviced.
When a channel event occurs, the information is written to the next location in the queue defined by the
parameter INT pointer. However, this can only take place if the entries V-bit is clear. The controller sets the
appropriate event bit in the entry, sets the V-bit to indicate that it contains valid data and increments the
pointer. The appropriate bit in the event register is sets which can generate an interrupt. Events must be
serviced as soon as possible and the queue entries cleared before the controller wraps back to a used entry,
otherwise an error will occur due to an unavailable entry. When an interrupt request is acknowledged and the
service routine handles the events, the associated entries must be made available for future use by clearing
the V-bit and of course these must be handled in descending order.
15
Interrupt Queues
External Memory
Internal Memory
Tx Int. Queue
Global Parameters
Rx Int. Queue 1
TINTBASE
TINTPTR
CHAMR
Rx Int. Queue 2
RINTBASE0
RINTPTR0
RINTBASE1
RINTPTR1
Rx Int. Queue 0
RINTBASE2
RINTPTR2
RINTBASE3
Rx Int. Queue 3
RINTPTR3
The global parameters provide pointers for all the interrupt queues. Each queue has a base pointer to the top
of the table and a current pointer to the next entry to be used. As events occur, the controller accesses the
entry defined by the parameters. The channel mode register, actually a channel specific parameter, specifies
which queue to use for the receiver. To view the channel mode register, global parameters or interrupt queue
entries click on the block of interest.
16
Event Processing (1 of 2)
Start
Event Occurs
GOV or GUN
?
N
INTMSK = 1
?
End
Y
Y
Set bit in MCCE
End
N
Entry [V] = 0
?
N
Y
Enter event information into queue
Set
MCCE - QOVn
End
set V
increment INTPTR
A
When an event occurs, the first check is for a global receiver over-run, when there is
no receiver buffer available, or a global transmitter under-run, when there is no data
in the FIFO. If one of those is the event then the respective bit is set in the event
register and no other event activity is required. If this is another event then is the
associated interrupt mask bit in the INTMSK parameter set? If not, the event is
masked and the process ends. If the mask is set enabling the event to be generated,
is the current entry in the table available, that is the V-bit clear? If not, then an
interrupt queue overflow is set in the event register for the queue in use. If the entry
is available, the respective bit associated with the event is set, the channel number
that the event relates to loaded into the entry, the valid bit set and the queue pointer
incremented. The next two slides show flow charts of how events are processed.
17
Event Processing (2 of 2)
A
RxF Event
?
Y
N
Decrement GRFCNT
N
GRFCNT = 0
?
Y
Load GRFCNT with GRFTHR
End
Set MCCE [RINTn]
End
There is one additional special circumstance that could occur for a channel
complete frame received. If that is the event, there is the possibility of
reducing the number of interrupts due to frames using the received frame
threshold facility, for which a counter is provided. The event is only
generated subject to the counter expiring. In that case, the counter is
decremented and checked for zero. If not, no event is generated but when it
does reach zero then it is reloaded with the value in the received frames
threshold parameter and the event is written to the event register interrupt bit
related to the queue being used. All other events result in the event register
update immediately.
18
Commands
Command
Init Tx params
Init Rx params
Stop Transmission
Stop Reception
Effect
Initializes parameters for each block of 32 channels starting
with channel specified. Only issue when Tx is disabled.
As for Tx
Disables Tx of specified channel, clears CHAMR[POL],
during frame sends ABORT, then Idles/flag
Forces select channel to stop receiving, no parameters changed.
Reinitialize to restart.
Reference Manual sections 27.9 & 13.4
Details
These are the commands that are used for the multi channel controllers. As in most cases when the
parameters have been initialized the initial parameters command must be issued using the command register.
It is vital that this is done after the parameters are initialized. Otherwise the controller will not function
correctly.
Notice that the command must be issued for each block of channels. Once the controller is operating,
transmission can be stopped, which is channel related. This disables the channel specified, disables buffer
descriptor polling by clearing the bit in the channel mode register that enables it, sends an abort signal and
then idles or flags. Reception can also be stopped which simply disables incoming data. No parameters are
changed and to restart the channel it must be re-initialized. For further details on the commands click on the
details button.
19
Programming Procedure (1 of 2)
Program SIRAM with all channels null
Program MCCF, MCCM
and clear MCCE
Load Global Parameters:
MCCBASE
MRBLR
GRFTHR/ GRFCNT
TINTBASE/TINTPTR
C-MASK32 *
XTRABASE
C-MASK16 *
RINTBASE0/RINTPTR0
¶
Clear:
MCCSTATE
TINTTMP
RINTTMPA
Load Channel Specific Parameters
for each Channel Required
ZISTATE *
ZIDATA0/1 *
INTMASK
CHAMR
ZDSTATE *
ZDDATA0/1 *
MFLR
Load Channel Extra Parameters
TBASEn/TBPTRn
RBASEn/RBPTRn
As required
INIT via CPCR
set up Tx Buffer Descriptors
set up Rx Buffer Descriptors
* predefined values
¶ other options
A
This is the programming procedure for the multi channel controllers. Generally there is no specific
order that the initialization should take place other than a few special cases. Initialization should take
place with the SIRAM cleared. Other than for the TSTATE and/or RSTATE parameters, the initialize
parameters command must be issued after all parameters have been programmed. The TSTATE and
RSTATE parameters must have bit 8 clear. To view the registers click on name of interest, and for
parameters click on the block of interest.
20
Programming Procedure (2 of 2)
A
Initialize Interrupt Queues
Clear all entries except the last,
which must have WRAP set.
Program SIRAM with channel info.
• For transmit, CHAMR[POL] must be set to
enable the CP to check the BDs are ready
• If superchannels are to be used, then additional
programming is required as follows :
Load T/RSTATE channel specific
parameters for each channel with MSB,
bit-8 set, and rest zero
– Global Parameters: SCTPBASE
Channels are now enabled and operate
following the next sync pulse.
• For all other programming, refer to the
Serial Interface Section 6.
Reference Manual section 27.12
– DPRAM: Superchannel tables must be set up
Exercise
If super-channels are to be used then the tables must be set up and the appropriate
parameters initialized. The serial interface must also be initialized appropriately. For details
on that see the serial interface module. The last operation must be to load the TSTATE and
or RSTATE parameter for each channel to function with bit 8 set and 9 through 15 clear.
Once that is done the channel will start operating with the next sync pulse. Be aware that for
the transmitter the polling enable bit in the channel mode register must be set to enable the
BDs to be checked for ready.
For an exercise to check your understanding on the requirements for setting up an MCC,
click on the exercise button. Be aware that this only shows the initialization process for the
MCC and other functions must also be initialized including the port connections, memory
controller, and interrupt controller, to name a few.
21
Example Interface to a T1 Framer
PA6/L1RSYNC1A
PA7/L1TSYNC1A
PA8/L1RXD[0]1A
PA9/L1TXD[0]1A
PC30/CLK2
PC31/CLK1
IFP1
EFP1
ID1
ED1
ECLK1
ICLK1
CSx*
A[21-31]
D[0-7]
PGPL2*
PGPL3*
CS*
A[10-0]
D[7-0]
RDB*
WRB*
XCLK
MPC8260
PM4388
MPC931FA
This example shows the connections for using an MCC with a T1 framer using the
PM4388.
22