Data sheet
ESD clamps for 40nm
On-chip ESD protection clamps for
TSMC 40nm CMOS technology
Despite the rising cost for development, EDA tools and mask sets IC design
companies continue to use the most advanced CMOS technology for high
performance applications because benefits like lower power dissipation,
increased gate density, higher speed and lower manufacturing cost per die
more than compensate the higher cost.
This return on investment however only pays off for ultra high volume
applications that are released well ahead of the competition. Due to the
use of sensitive thin-oxide transistors, increased complexity through
multiple voltage domains and the use of IP blocks from various vendors, a
comprehensive ESD protection strategy becomes more important.
Sofics has verified its TakeCharge ESD protection clamps on TSMC 40nm
CMOS G and LP technology. The devices are product proven in more than
25 mass produced 40nm products. This document provides an overview of
the available structures. The cells provide competitive advantage through
improved yield, reduced silicon footprint and enable advanced multimedia
and wireless interfaces like HDMI, USB 3.0, SATA, WIFI, GPS and Bluetooth.
Data sheet: Sofics on-chip ESD protection cells for TSMC 40nm CMOS
ESD protection clamps for 40nm CMOS technology
The following tables provide an overview of the Sofics ESD clamps for the 40nm technology for the 0.9V, 1.0V, 1.2V,
1.8V and 3.3V domains. The cells are designed for 2.5kV HBM and 200V MM (unless otherwise mentioned) but can
be easily adapted for other ESD protection levels. The cells can be further customized to ensure compatibility with
specific metal schemes and IO pitch.
The Sofics ESD cells cover all types of protection concepts and approaches as detailed in the figure below.
Different pad types available in the 40nm solution set from Sofics. For each power domain (0.9V, 1.2V, 1.8V and 3.3V) a
power clamp is available. Protection cells for RF interfaces are available for the 1.1V domain. For the IO’s several pad-types
exist: Pad-type ‘A’ consists of a standard dual diode. Pad-type ‘B’ is used for some RF interfaces. Pad-type ‘C’ consists of a full
local protection with 2 clamps and dual diode. Pad-type ‘D’ uses dual diode as a primary protection and a secondary
protection concept with small local clamps. Pad-type ‘E’ uses a full local protection concept as primary protection but adds
secondary local clamps specifically for improved CDM protection levels.
The unique clamp name is mentioned under the clamp type.
Voltage
Clamp type
Silicon
Leakage
Junction
domain
footprint
capacitance
0.9V
Power clamp <1000um²
<200pA
TS40PC0V9
0.9V
PAD-type A
<500um²
<100pA
<100fF
<1500um²
<150pA
<350fF
<2100um²
<100nA
<440fF
<1000um²
<10pA
<180fF
TS40Axx
0.9V
PAD-type C
TS40C0V9
0.9V
PAD-type E
TS40E0V9
0.9V
PAD-type B
TS40Bxx
Sofics Proprietary – ©2011
ESD
performance
>2kV HBM
>200V MM
>2kV HBM
>200V MM
>2kV HBM
>200V MM
>2kV HBM
>200V MM
>5kV HBM
>250V MM
Vt1
*
Comment
2.36V
D
1.98V
2.36V
D
Dual diode protection not
always feasible
Protects thin oxide output
drivers
Protects thin oxide
bidirectional interfaces,
Riso=20 Ohm
Protects thin oxide
bidirectional interfaces
PAD-GND
Page 2
Data sheet: Sofics on-chip ESD protection cells for TSMC 40nm CMOS
Voltage
domain
1.1V
Clamp type
Power clamp
Junction
capacitance
Leakage
<500um²
<100pA
<100fF
<1000um²
<10pA
<180fF
<1400um²
<100pA
<180fF
>4.5kV HBM
>200V MM
3.03V
<1700um²
<150pA
<350fF
2.35V
<2200um²
<100nA
<500fF
>2.5kV HBM
>220V MM
>3.5kV HBM
>300V M
<1900um²
<10nA
<250fF
>2kV HBM
>200V MM
D
Silicon
footprint
<1000um²
Leakage
Junction
capacitance
Vt1
<500um²
<100pA
<100fF
<1700um²
<150pA
<350fF
<2200um²
<100nA
<500fF
ESD
performance
>2kV HBM
>200V MM
>2kV HBM
>200V MM
>2.5kV HBM
>220V MM
>3.5kV HBM
>300V M
<1900um²
<10nA
<250fF
>2kV HBM
>200V MM
D
<1000um²
<10pA
<180fF
>5kV HBM
>250V MM
D
<1400um²
<100pA
<180fF
>4.5kV HBM
>200V MM
3.03V
<100pA
TS40PC1V1
1.1V
PAD-type A
TS40Axx
1.1V
PAD-type B
TS40Bxx
1.1V
PAD-type B
TS40BxxOVT
1.1V
PAD-type C
TS40Cxx
1.1V
PAD-type E
TS40ExxR20
1.1V
PAD-type E
TS40ExxR5
Voltage
domain
1.2V
Clamp type
Power clamp
<100pA
TS40PC1V2
1.2V
PAD-type A
TS40Axx
1.2V
PAD-type C
TS40Cxx
1.2V
PAD-type E
TS40ExxR20
1.2V
PAD-type E
TS40ExxR5
1.2V
PAD-type B
TS40Bxx
1.2V
PAD-type B
TS40BxxOVT
Sofics Proprietary – ©2011
ESD
performance
>2kV HBM
>200V MM
>2kV HBM
>200V MM
>5kV HBM
>250V MM
Vt1
*
Silicon
footprint
<1000um²
Comment
2.8V
D
D
2.99V
*
Dual diode protection not
always feasible
Protects thin oxide
bidirectional interfaces
Q-factor 71
PAD-GND
Protects thin oxide
bidirectional interfaces
OVT protection
Q-factor 43
PAD-GND
Protects thin oxide output
drivers
Protects thin oxide
bidirectional interfaces,
Riso=20 Ohm
Protects thin oxide
bidirectional interfaces,
Riso=5 Ohm
Comment
2.8V
D
2.35V
2.99V
Dual diode protection not
always feasible
Protects thin oxide output
drivers
Protects thin oxide
bidirectional interfaces,
Riso=20 Ohm
Protects thin oxide
bidirectional interfaces,
Riso=5 Ohm
Protects thin oxide
bidirectional interfaces
PAD-GND
Protects thin oxide
bidirectional interfaces
OVT protection
Q-factor 43
PAD-GND
Page 3
Data sheet: Sofics on-chip ESD protection cells for TSMC 40nm CMOS
Voltage
domain
1.8V
Clamp type
Power clamp
Silicon
footprint
<1300um²
Leakage
Junction
capacitance
<500um²
<100pA
<100fF
<2000um²
<200pA
<400fF
<1500um²
<1nA
<250fF
<1900um²
<10nA
<250fF
<1300um²
<100pA
<100fF
Silicon
footprint
<2000um²
Leakage
Junction
capacitance
<500um²
<100pA
<100fF
<2000um²
<200pA
<200fF
<150pA
TS40PC1V8
1.8V
PAD-type A
TS40Axx
1.8V
PAD-type C
TS40C1V8O
1.8V
PAD-type C
TS40C1V8IO
1.8V
PAD-type E
TS40E1V8
1.8V
PAD-type B
TS40B1V8LC
Voltage
domain
3.3V
Clamp type
Power clamp
<200pA
TS40PC3V3
3.3V
PAD-type A
TS40Axx
3.3V
PAD-type B
TS40B3V3
ESD
performance
>3kV HBM
>240V MM
>2kV HBM
>200V MM
>2kV HBM
>200V MM
>3kV HBM
>250V MM
>2kV HBM
>200V MM
>2kV HBM
>200V MM
ESD
performance
>4kV HBM
>300V MM
>2kV HBM
>200V MM
>4kV HBM
>300V MM
Vt1
*
Comment
3.72V
D
3.55V
2.78V
D
4.05V
Vt1
*
Dual diode protection not
always feasible
Protects thick oxide
output drivers
Protects bidirectional
interfaces
Protects bidirectional
interfaces, Riso=5 Ohm
Used as clamp for XTAL
oscillator module
PAD-GND
Comment
5.7V
D
5.7V
Dual diode protection not
always feasible
PAD-GND
Remarks
- * For some cells, the Vt1 trigger voltage depends on other circuits. This is depicted by ‘D’.
o For the dual diode IO protection concept the trigger voltage depends on the power clamp
and core circuits
o For certain IO protection clamps the trigger voltage is aligned to the supply voltage state
o Some output driver protection clamps align the trigger voltage to the driver behavior under
ESD conditions.
- In most cases a ‘PAD-type B’ cell can be created from ‘PAD-type C’ cell. Such work can be
performed by Sofics under customization and support services.
- Sofics can provide custom cells (reduced capacitance, specific IO pitch, other protection level, other
trigger voltage …) based on extensive analysis on each of the technology nodes.
- For thin oxide gate protection local CDM clamps should be used. Such clamps may add capacitance,
leakage and PAD resistance. Sofics has a set of concepts and versions available.
- Further information including LVS net lists, leakage numbers at high temperature and protection
concepts can be provided on request.
Sofics Proprietary – ©2011
Page 4
Data sheet: Sofics on-chip ESD protection cells for TSMC 40nm CMOS
Leakage and latch-up relevant data points
Clamp
0.9V Power
clamp
1.2V Power
clamp
1.8V Power
clamp
0.9V Local
clamp
3.3V Power
clamp
Leakage
25°C
59pA
125°C
87nA
TLP, 25°C
1.1
Holding voltage
DC, 25°C
1.25
80pA
141nA
1.98
1.925
1.47
113pA
334nA
2.05
2.03
1.77
122pA
147nA
1.02
1.29
0.89
180pA
300nA
4.8
4.7
3.2
DC, 125°C
1.02
Portability
The 40nm Sofics cells have been measured on both LP and G process flavors. The device behavior is
identical – as shown on TLP data of clamp versions designed for 1.8V power (left) and IO (right) protection.
Sofics Proprietary – ©2011
Page 5
Data sheet: Sofics on-chip ESD protection cells for TSMC 40nm CMOS
About Sofics
Sofics (www.sofics.com) is the world leader in on-chip ESD protection. Its
patented technology is proven in more than a thousand IC designs across all
major foundries and process nodes. IC companies of all sizes rely on Sofics for offthe-shelf or custom-crafted solutions to protect overvoltage I/Os, other nonstandard I/Os, and high-voltage ICs, including those that require system-level
protection on the chip. Sofics technology produces smaller I/Os than any generic
ESD configuration. It also permits twice the IC performance in high-frequency and
high-speed applications. Sofics ESD solutions and service begin where the foundry
design manual ends.
ESD SOLUTIONS AT YOUR FINGERTIPS
Our service and support
Our business models include
 Single-use, multi-use or royalty bearing license for ESD clamps
 Services to customize ESD protection
o Enable unique requirements for Latch-up, ESD, EOS
o Layout, metallization and aspect ratio customization
o Area, capacitance, leakage optimization
 Transfer of individual clamps to another target technology
 Develop custom ESD clamps for foundry or proprietary process
 Debugging and correcting an existing IC or IO
 ESD testing and analysis
Notes
As is the case with many published ESD design solutions, the techniques and
protection solutions described in this data sheet are protected by patents and
patents pending and cannot be copied freely. PowerQubic, TakeCharge, and
Sofics are trademarks of Sofics BVBA.
Version
June 2011
Sofics Proprietary – ©2011
Sofics BVBA
Groendreef 31
B-9880 Aalter, Belgium
(tel) +32-9-21-68-333
(fax) +32-9-37-46-846
bd@sofics.com
RPR 0472.687.037
Page 6