Chinese Journal of Electronics
Vol.23, No.4, Oct. 2014
An Ultra Low Steady-State Current Power-onReset Circuit in 65nm CMOS Technology∗
SHAN Weiwei, WANG Xuexiang, LIU Xinning and SUN Huafang
(National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China)
Abstract — A novel Power-on-reset (POR) circuit is
proposed with ultra-low steady-state current consumption. A band-gap voltage comparator is used to generate a
stable pull-up voltage. To eliminate the large current consumptions of the analog part, a power switch is adopted
to cut the supply of band-gap voltage comparator, which
gained ultra-low current consumption in steady-state after
the POR rest process completed. The state of POR circuit
is maintained through a state latch circuit. The whole circuit was designed and implemented in 65nm CMOS technology with an active area of 120µm∗160µm. Experimental
results show that it has a steady pull-up voltage of 0.69V
and a brown-out voltage of 0.49V under a 1.2V supply voltage rising from 0V, plus its steady-state current is only
9nA. The proposed circuit is suitable to be integrated in
system on chip to provide a reliable POR signal.
Key words — Power-on-reset circuit, Brown-out detection, Ultra-low steady-state current, Band-gap voltage
comparator.
I. Introduction
Low power has been a big issue for System on chip (SoC)
design, especially for the Wireless sensor networks (WSN)
chips and battery supplied mobile applications, where static
power is very important[1−4] . The static power of SoC is com1 the leakage power of digital circuits which can be
posed of: 2 the static power
cut off by power gating technology, and of analog circuits such as Power-on-reset (POR), which is an
important part of the static current consumption for most of
SoC chips. A POR circuit provides a reset signal to the system during power up stage to ensure the chip can start with
a known state. In many applications, brown-out detection is
also needed to reset the system when the supply drops suddenly in order to protect the system, especially for those with
CPUs. What’s more, since it is connected to supply voltage
all the time, its power consumption is an import part in the
chip’s whole static power.
Many POR circuits were proposed with different features
for different applications[5−8] , such as near zero steady state
current POR[5] , band-gap reference based POR[6] , a long resettime POR[7] , process and temperature-tolerant POR[8] and so
on. There are also commercial POR Intellectual property (IP)
cores provided by IP vendors[9] . A compact-structured POR
is obtained by simply using series connection of an off-chip
capacitor and a resistor, with the split voltage connected to
several inverters as a buffer to generate the reset signal for
the chip[5] . When the supply voltage VDD begins to rise from
zero, the capacitor begins to charge the input node of the
inverter. The reset signal is activated until the voltage of capacitor’s upper plate reaches the switching threshold voltage
of the inverter with the charging of the capacitor. Although
this method is very simplified in its structure, it is not widely
1 its pull-up voltage is
used in many applications because 2 it can’t provide brown-out detection.
unstable; The POR circuits based on accurate voltage detection[6−8]
can obtain a stable pull-up voltage, but at the price of nonnegligible static current. A near zero steady-state POR in
Ref.[5] provided an on-chip POR reset signal and a brownout reset signal with near-zero steady-state current consumption. However, it used the split voltage of two resistors in series
connection to detect the rise of the supply voltage; therefore,
its pull-up voltage is susceptible to the impact of supply voltage and process variations.
Therefore, in this paper, a novel POR circuit composed
of a band-gap voltage comparator, a state latch and a brownout detector is presented, which provides both ultra-low power
consumption and stable pull-up voltage. The circuit is designed and implemented in 65nm CMOS technology. The experimental and post simulation results show that it functions
well with only several nano-Amp current in steady-state, which
is ultra-low.
II. Circuit Structure and Operating
Principle
A novel ultra-low steady-state current POR circuit is proposed as shown in Fig.1, which is mainly composed of several
parts: band-gap voltage detector, current comparator, state
latch, brown-out detector and buffer.
To make the pull-up voltage stable, a band-gap voltage
detector is employed using band-gap reference and current
∗ Manuscript Received Nov. 2013; Accepted Jan. 2014. This work was supported by the National Natural Science Foundation of China
(No.61006029) and Qing Lan Project.
An Ultra Low Steady-State Current Power-on-Reset Circuit in 65nm CMOS Technology
679
The first derivative of VT P with respect to T is:
2R2 ln N dVT
dVT
VT ln N
dVT
dVT P
=
+
ln
+
dT
R1
dT
dT
R1
dT
dVT
αV
T
−
ln(C0 T α ) −
dT
T
Fig. 1. General structure of POR circuit
comparator. And the reset states are stored by state latch circuit. Meanwhile, a power switch transistor is used to cut off the
power of the analog parts after the reset process is completed
with a stable high output voltage. Therefore, the steady-state
current of POR circuit is the leakage current of the digital
part, which is of only several nano-Amp.
The whole schematic diagram of our proposed POR circuit
is shown in Fig.2. Their principles are analyzed in the following
sections.
1. Band-gap voltage detector circuit
The band-gap reference circuit shown in Fig.2 Part A is
mainly composed of two pairs of current mirrors by NPN transistors of Q0 , Q1 , Q2 , Q3 and two resistors of R1 , R2 . The
emitter area of Q1 and Q2 is set as eight times large as Q0
and Q3 ’s.
At first when VDD rises from 0, I2 is larger than I1 because
the PN junction is cut off until VBE0 = VR1 +VBE1 . That is, I2
is higher than I1 when VDD is lower than the pull-up voltage
VT P , and it is lower than I1 when VDD > VT P , then the reset
signal generates.
The supply voltage of the band-gap voltage detector is denoted as VE , which can be differently described for each branch
of Q0 and Q1 as Eqs.(1) and (2):
VE = (I1 + I2 )R2 + VBE0 = (I1 + I2 )R2 + VT ln
I1
IS
(1)
VE = (I1 + I2 )R2 + I2 R1 + VBE1
= (I1 + I2 )R2 + I2 R1 + VT ln
I2
N IS
(2)
It can be easily deduced from the equations above that:
I2 =
VT
N I1
ln
R1
I2
(3)
When VE is equal to the pull-up voltage VT P , at this time,
I1 = I2 = I, Eq.(3) becomes Eq.(4):
I=
VT
ln N
R1
(4)
The reverse saturation current of PN junction IS =
Vg
), where C0 is the diffusion coefficient, α is
C0 T α exp(−
VT
a constant, Vg is the band-gap voltage. Therefore, the pull-up
voltage VT P can be modified as:
VT P = VT
VT ln N
2R2
ln N + VT ln
− VT ln(C0 T α ) + Vg (5)
R1
R1
(6)
When temperature is 300K, we can obtain that dVT /dT =
k/q. It can be deduced that by letting Eq.(6) equal to 0, the
pull-up voltage of the POR will be influenced least by the
temperature fluctuates near 300K. This is accomplished by
designing R1 and R2 properly according to Eq.(7) to make
VT P stable.
2R2 ln N
k ln N
α−1−
R1
=e
(7)
α−1
qC0 R1 T
Then a current comparator circuit is used to compare I1
and I2 to generate the detection output signal “Det out” when
VDD reaches the pull-up voltage. The currents of NPN transistors Q4 and Q5 are mirrored from Q0 to be compared with
the current mirrored from Q1 . At the beginning of the poweron process, VDD is lower than VT P and I2 is higher than I1 ,
M5 starts to turn on as node a been charged. Meanwhile, the
potential of node b keeps low because of that M6 is still cut
off, VDet out stays low consequently. When VDD rises to the
point of VT P , I2 is equal to I1 . After that, I2 is lower than I1
and node awill be gradually pulled down as VDD exceeds VT P ,
then Det out will be pulled up as M5 turns off and M6 turns
on.
2. State latch circuit
State latch circuit is used here to generate a detection enable signal of “Det en” to control the power switch of the analog part as shown in Fig.2 Part A, which will turn off its power
supply after reset process finished. The band-gap voltage detector and the state latch are connected through a PMOS transistor M13 .
It has two working status: first, in the initial stage of
power-on, as the supply voltage VDD rises, the voltage at node
n1 will rise accordingly, and then n2 is pulled down that makes
M13 conductive to latch Det out is latched as the global reset signal. Next, when VDD exceeds the pull-up voltage VT P ,
VDet out ramps up and increases as VDD increases. Therefore,
as M13 is still on, VDet out passes through M13 gate to make
node n1 turn to low voltage, which in turn makes node n2 high
voltage to turn off M13 to isolate analog parts from state latch
circuit. Meanwhile, the analog part will be powered off as the
power switch transistor M0 in Fig.2 is cut off by the signal
buffered from Latch out.
3. Brown-out detector circuit
A brown-out detector circuit shown in Fig.2 Part C [5] is
used to generate a reset signal when VDD drops suddenly or
when it is too low, in order to prevent the system to work in
an unknown state.
When VDD drops suddenly, node n4 will stay at a high
voltage of VDD –Vth just as power supply is still on due to the
existence of capacitance C2 . Afterwards, Latch out signal and
node n3 will be pulled down by the output of the inverter composed of M9 and M10 , therefore, the system resets again and
power switch M0 turns on again for another reset process. It
can be seen that when VDD has been stable at high level, the
680
Chinese Journal of Electronics
2014
Fig. 2. Schematic diagram of the POR circuit. Part A is the bandgap voltage detector and current comparator; Part B is
the state latch circuit, and Part C is the brown-out detector.
brown-out circuit has little power consumption because there
is no direct access from VDD to GND.
III. Experimental results
The proposed POR circuit was designed and fabricated in SMIC 65nm CMOS technology with an area of
120µm∗160µm. Its layout is shown in Fig.3(a), where most of
the areas are occupied by current mirrors of NPN transistors,
resistors and capacitance arrays. During the circuit and layout design, strict matching and isolation techniques are used to
eliminate the influence of process variation. And post simulations are performed to guarantee the correctness of the circuit
under different process corners.
Its testing PCB board and the test platform are shown in
Fig.3(b). To be clear, there are only one input and one output
in POR: VDD and Por reset signals. However, it was fabricated
together with several other circuits in one chip. Plus, the PCB
board was not designed only for our POR circuit. The measurement was realized by an oscilloscope, an arbitrary waveform
generator, and a digital multimeter.
Fig. 3. Microphoto of POR circuit and test platform
The experimental results including initial power-on reset,
brown-out reset and second power-on reset are shown in Fig.4,
where the power supply is a triangular voltage of 0V to 1.2V. It
can be seen that the circuit generates a POR signal when the
VDD raises to 0.69V and a brown-out reset signal when VDD
drops to 0.49V. When the power supply VDD rises again, the
circuit can also generate the correct reset signal. The steadystate current of the POR circuit after the reset prcess finished
is ultra low to be measured during the actual chip test by Angilent digital multimeter. In order to show how small the steadystate curret is, the post-layout simulation under HSPICE was
performed, which showed that except for a pulse current of
several microamps level at the instant of pull-up voltage, the
steady-state current of the circuit is only 9nA.
Fig. 4. Experimental results of initial power-on-reset, brownout and second power-on-reset
The performance summaries of the proposed POR circuit
are listed in Table 1 with comparison to other POR circuits,
which shows that our proposed circuit can achieve both stable power-on and brown-out reset with ultra-low steady state
current. Here Ref.[5] used the basic structure of series connection of a capacitor and a resistor, which offers medium pull-up
voltage stability. Ref.[9] had a low pull-up stability whose VT P
is between 1.0V and 1.6V. Although Refs.[7–9] used different
CMOS process of 0.18µm, due to the analog pull-up voltage
detection circuit, their steady-state current consumptions were
among micro-Amps, which should be much larger than the digital leakage current of our work even using the same CMOS
process as ours.
An Ultra Low Steady-State Current Power-on-Reset Circuit in 65nm CMOS Technology
Table 1. Performance summaries of the
proposed POR circuit and comparisons
Our work Ref.[5]∗∗ Ref.[7] Ref.[8]∗∗ Ref.[9]∗∗∗
CMOS Technology 65nm
65nm 0.18µm 70nm
0.18µm
Supply voltage
1.2V
1.1V
1.8V
3V
1.8V
Steady state
9nA∗
Near 0
1µA
1.2µA
1µA
current
VT P stability
High Medium NA
High
Low
Brown-out
Yes
Yes
Yes
No
No
Active area
120·
120·
120· 0.064mm2
185·
160µm2 60µm2 100µm2
75µm2
∗: Our work provides simulated current consumption with IC
fabrication. ∗∗: Refs.[5] and [8] provided simulation results without
IC fabrication. ∗∗∗: Ref.[9] is a commercial IP.
IV. Conclusion
In this paper, a novel power-on reset circuit with both
ultra-low steady-state current and a stable pull-up voltage is
proposed in 65nm CMOS technology. The POR circuit can
perform both power-on reset and brown-out detection. The
advantage of our proposed circuit is that it uses a band-gap
comparator to generate a stable pull-up voltage. Plus, by using a power gate and a state latch circuit to cut the power
supply of the comparator and keep the POR state, the steady
state current is ultra-low. Therefore, by reducing the power
consumption of the circuit and increasing its stability at the
same time, our proposed circuit is suitable to be integrated in
large VLSI circuit for low power applications.
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SHAN Weiwei was born in 1982.
She received Ph.D. degree in microelectronics from Tsinghua University in
2009. She is currently an associate professor in Southeast University, China. Her research mainly focuses on low power integrated circuit design and information security. (Email: wwshan@seu.edu.cn)
WANG Xuexiang was born in
1972. She received the M.S. and Ph.D. degrees in Information Engineering and Electrical Engineering from Southeast University of China in 2002 and 2009 respectively. She is an associate professor of
Southeast University. Her research interests include SoC design and reconfigurable
computing. (Email: wxx@seu.edu.cn)
LIU Xinning recevied B.S. and
M.S. degrees of electronics engineering
from Southeast University, China, in 2000
and 2003 respectively. Now, he is a lecturer of the School of Electronic Science
and Engineering, Southeast University. His
research mainly foucus on the SoC design
technology and low power design technology. (Email: xinning.liu@seu.edu.cn)
SUN Huafang was born in 1966.
She received bachelor degree of electronic engineering from Southeast University in 1989. Currently she is an engineer in Collage of Electrical Science &
Engineering, Southeast University. (Email:
se filly@seu.edu.cn)