Proceedings of the 13th
IEEE International Conference on Nanotechnology
Beijing, China, August 5-8, 2013
Multi-Level Cell Spin Transfer Torque MRAM
Based on Stochastic Switching
Yue Zhang1,2, WeiSheng Zhao1,2, Jacques-Olivier Klein1,2, Wang Kang1,2, Damien Querlioz1,2, Claude Chappert1,2,
Dafiné Ravelosona1,2
1
IEF, Univ. Paris-Sud, Orsay, 91405, France
2
CNRS, UMR 8622, Orsay, 91405, France
Email: yue.zhang@u-psud.fr and weisheng.zhao@u-psud.fr
Abstract —Spin Transfer Torque Magnetic Random
Access Memory (STT-MRAM) provides a promising pathway
forthe next generation of non-volatile memory and logic chips.
The perpendicular magnetic anisotropy (PMA) in CoFeB/MgO
/CoFeB magnetic tunnel junction (MTJ) nanopillar provides
high thermal stability and low critical current. However, the
STT switching mechanism of MTJ has been revealed
intrinsically stochastic, which results from the unavoidable
thermal fluctuations of magnetization. This phenomenon
affects deeply the reliability of hybrid CMOS/MTJ interface
circuits and drives important power overhead. In this paper,
we present a multilevel cell (MLC) STT-MRAM benefiting
from the stochastic behaviors. It allows not only higher storage
density, but also reduces the programming power and delay.
This new cell can be also used as electrical synapse to build up
neuromorphic computing systems or other biological networks.
Monte-Carlo statistical simulations based on a 40 nm
technology node have been carried out to validate its
functionality and demonstrate its performance.
Index Terms – MRAM, Perpendicular Magnetic Anisotropy,
Stochastic, Multilevel cell, Non-Volatile
I. INTRODUCTION
Thanks to the key enhancement such as non-volatile,
high access speed and high endurance, Magnetic Random
Access Memory (MRAM) technology has become more and
more convincing to become the next generation of nonvolatile universal memory and logic device [1]. Based on the
transfer of angular momentum by a spin-polarized current,
Spin transfer Torque (STT) switching mechanism simplified
and optimized greatly the switching process [2-3]. Recent
research progress demonstrated that the perpendicular
magnetic anisotropy (PMA) in the CoFeB/MgO/CoFeB
Magnetic Tunnel Junction (MTJ) could decrease the critical
switching current while remaining relatively high thermal
stability, which clears the main bottleneck for the
miniaturization of MTJs [4-5].
However, an intrinsic stochastic feature has been revealed
in STT switching, which is caused by the unavoidable
thermal fluctuations of magnetization [6-7]. They are
responsible for large fluctuations in the switching duration,
the latter following a sigmoidal distribution with exponential
tails. Because of this phenomenon, some write errors might
occur, which affects the reliability of hybrid CMOS/MTJ
circuit.
978-1-4799-0675-8/13/$31.00 ©2013 IEEE
On the other hand, despite the apparent drawbacks of
stochastic behavior, we are thinking about how to profit from
its probabilistic or random property. Clustering multiple
MTJs to realize a multilevel cell (MLC) [8] is a way out for
that. MLC is a key method for density improvement of STTMRAM, and is also an important concept for neuromorphic
computing applications [9-10].
IP ->AP >IC0
P
AP
CoFeB
CoFeB
MgO
MgO
CoFeB
CoFeB
CoFeB
CoFeB
P
AP
MgO
MgO
CoFeB
CoFeB
IAP ->P >IC0
(a)
(b)
Fig.1. (a) Spin transfer torque switching mechanism: the MTJ state changes
from parallel (P) to anti-parallel (AP) under positive electron flow direction
IP->AP>IC0. It changes from AP to P under negative electron flow direction IAP>IC0. Note that the red arrows represent the electron flow and not the
>P
current (b) Experimental measurement of STT stochastic switching.
In this paper, we demonstrate a novel design of MLC
based on stochastic STT switching in PMA MRAM. This
design allows a higher density through the multilevel feature,
but also reduces the programming power and delay. MonteCarlo simulations for 2-bits parallel and serial MLCs based
on 40 nm technology node have been carried out to validate
their functionality and demonstrate its performance. The
models of these MLCs base on a stochastic compact model of
PMA MTJ programmed with the Verilog-A language.
The rest of this paper is organized as follows: in Section.
II, we describe the compact model of PMA MTJ integrating
stochastic STT switching behavior. In Section. III, the
architecture of parallel and serial MLCs are respectively
introduced, Monte-Carlo simulation results and performance
analysis are also exhibited. A discussion and conclusion is
provided in the Section. IV.
II. PHYSICAL MODELS USED TO DESCRIBE STOCHASTIC
BEHAVIOR
Recently, lots of experimental and theoretical results
have shown that, although STT switching may allow subnanosecond switching duration, the switching process of
STT is stochastic [11-13]. Furthermore, depending on the
relative magnitude between switching current (I) and critical
233
current (Ico), the STT stochastic behaviors of this PMAMTJ can be categorized into two regions: Sun model (I>Ico)
and Neel-Brown model (I<0.8Ico) [14-15]. For practical
applications, the two regions have their own specific
interest: The region of Sun model addresses fast switching
(sub 3ns) but high current density. The region of NeelBrown model addresses low current (I<0.8Ico) but slower
switching.
These two regions are separated by the critical current
which is defined as follows for p-MTJ [4]:
I c0 =α
γ e
γ e
(μ 0 M S ) H K V = 2α
E
μB g
μB g
E
μ M ×V × H
=
0
S
(1)
K
2
(2)
where E is the barrier energy, HK is the effective anisotropy
field, μ0 is permeability of free space, Ms is the saturation
magnetization, is the magnetic damping constant, is the
gyromagnetic ratio, e is the elementary charge, μB is the
Bohr magneton, V is the volume of the free layer, kB is the
Boltzmann constant, and g = TMR(TMR+ 2) / 2(TMR+1) is the
spin polarization efficiency factor. The default values of the
critical parameters used in this model are given in Table.I.
Parameter
Area
TMR(0)
V
R·A
Ms
m
Jc0
PARAMETERS PRESENT IN THE FITTING FUNCTION
Description
MTJ surface
TMR ratio with 0 Vbias
Volume of free layer
Resistance-area product
Saturation magnetization
Free layer magnetic moment
Critical current density
1
<τ >
=[
2
C + ln( π
eM sV (1 + P ref P
free
)
( I write − I c 0 )
(3)
90
80
0.71 Ir/Ico
70
10 us
20 us
60
10 us
5 us
50
40
2.5 us
30
20
< Dap->p >
10
100.0
0
0.6
I (uA)
)
μ B P ref
100
Default Value
40 nm x 40 nm x /4
120 %
Area x1.3 nm
5 μm2
7.96 x 105 A/m
MS×V
5.0 x 105 A/cm2
P -> AP
0.65
0.7
Reading Current (Ir/Ico)
0.75
0.8
Fig.3. Dependence of sensing bit error rate (BER_S) versus sensing current
for different switching duration pulses.
0.0
< Dp->ap >
AP -> P
-200.0
0.0
4
ξ
]
d Pr(t )
1
(4)
=
(1 − Pr( t ))dt τ 1
E
I
(5)
τ 1 = τ 0 exp(
(1 −
))
k BT
I CO
where 0 is the attempt period. From Eq. 4, the probability
density function (PDF) of the switching duration in this
region follows an exponential distribution with characteristic
time τ1 decreasing with the current density.
200.0
-100.0
2
where C•0.577 is the Euler’s constant, =E/kBT the thermal
stability factor, T is the temperature, Pref, Pfree the tunneling
spin polarizations of the reference and free layers assumed to
be equal (Pref=Pfree=P) in this compact model, m is the
magnetic moment of free layer.
In the corresponding sub-threshold region (I<0.8Ico,
Neel-Brown model), the switching can still occur thanks to
thermal activation above the voltage/current-dependent
barrier. In this region, the switching probability can be
described by [17]:
Sensing Disturbance (%)
TABLE I.
which is described in [16]. The average switching delay time
is expressed by [5]
5.0
10.0
15.0
Time (ns)
20.0
25.0
Fig.2. 100 complete writing operation simulations (parallel (P) to
antiparallel (AP) and back to parallel (P))
Sun model is used to describe the case where the current
flowing through the MTJ exceeds the critical current. In this
switching mechanism, the switching is triggered by a
thermal fluctuation which creates an initial angle between
the current spin-polarization and the magnetization of the
storage layer. The switching duration then follows a specific
distribution centered on the average switching delay time,
To verify the functionality of this STT simulation model
taking into account these stochastic aspects, writing and
sensing operations of single MTJ cell were simulated
respectively. Fig. 2 shows a simulation of 100 writing
operations. As expected the switching probability follows a
distribution centered on the average switching delay time as
calculated by Eq. 3. The dependence of Sensing Disturbance
(SD) versus sensing current for different duration pulses is
illustrated in Fig. 3. The SD grows exponentially with
respect to the sensing current which is consistent with the
switching probability theory described by Eq. 4-5. In
addition, for fixed amplitude of sensing current, increasing
the read current pulse duration yields an increase in
switching probability meaning an increase of probability of
undesired write during read.
234
III. MLC PMA STT MRAM BASED ON STOCHASTIC
SWITCHING
MLC is a design to store multiple bits of information in
one cell, which is a promising technology used for memory
and neuromorphic computing. Two traditional structures of
MLC are the parallel and the serial structures (see Fig. 4 and
Fig.5) [18]. In addition, MLC usually uses a selected
transistor (Tp for parallel and Ts for serial) to enable the
switching process, which is similar to the 1T/1MTJ structure
used in MRAM.
SL
SL
SL
Tp
Tp
WL
Tp
Tp
WL
00
SL
WL
WL
11
10
01
Each process has actually been executed 100 times under a
10 ms pulse. However, we only show 5 times among them
for the purpose of clarity. We can find that the states of
MLCs vary randomly and step by step, which is the
functionality that we anticipated. Note that these two
simulations were executed in the aforementioned regime of
Neel-Brown model. When expecting to accelerate the
programming procedure, higher current can be applied to
drive the MLC to work in the Sun’s model regime. In this
condition, the switching duration can reach nanosecond or
sub-nanosecond.
Fig.4. 2-bits parallel MLC
Fig. 4 shows a parallel MLC structure where 3 separated
free layers are grown on an entire pinned layer, although it is
not yet achievable with the existing technology capability. In
the following simulations of this paper, we used the clusters
of parallel-connecting MTJs as the parallel MLCs. The serial
MLC is a stack of MTJs connected vertically. Ordinarily, the
serial MLCs requires a lower current but a higher voltage
than the parallel ones, thereby it is preferable to use current
source for programming the serial MLC and voltage source
for parallel MLC. Furthermore, in order to generate a higher
current for the parallel ones, the selected transistor used in
the circuit will be larger than those for serial MLC; the serial
structure thus seems more achievable between these two
types of structures.
SL
Ts
SL
Ts
WL
00
SL
Ts
WL
01
Fig.6. Monte-Carlo simulation for 2-bits parallel MLC. Data switches from
‘00’ to ‘11’.
SL
Ts
WL
10
WL
Fig.7. Monte-Carlo simulation for 2-bits serial MLC, Data switches from
‘11’ to ‘00’.
11
Fig.5. 2-bits serial MLC
As shown in the Fig.4 and Fig.5, due to the stochastic
behavior, the 3 MTJs are switched successively. If we
consider antiparallel state of MTJ as the logic ‘0’ and
parallel state as ‘1’, the MLCs can be programmed from
‘00’ to ‘11’ or from ‘11’ back to ‘00’. In addition, the
number of levels is determined by the number of bits. N bits
N
in the MLC can yield 2 levels correspondingly.
The functionalities of these two structures are respectively
validated by the Monte-Carlo simulations (see Fig.6 and
Fig.7). Fig.6 shows the case for parallel MLC programming
from ‘000’ to ‘100’. Fig.7 illustrates the other case for serial
structure in the reversal process from ‘100’ back to ‘000’.
Thanks to the 3-D integration technology implementing
MRAM above the CMOS part, the area efficiency of hybrid
MRAM/CMOS circuits can be improved. However this also
makes the CMOS part dominate the overall area. On the
other hand, the currents through the MLCs govern the
programming speed, which is also determined by the area
overhead of transistors. Fig.8 demonstrates the tradeoff
between the average switching duration and the area of serial
MLC. We also take account of the effect of pulse magnitude
into our analysis by applying 3 different magnitudes of
pulses (0.9 V, 1.2 V and 1.5 V). It shows that the higher
voltage improves the MLC performance.
235
impact of transistor area and switching pulse magnitude on
the programming speed have been also investigated. This
MLC cell based on stochastic behaviors has a great potential
to achieve denser, faster and low power non-volatile
memory chips and neuromorphic computing systems.
9
0.9 V
1.2 V
1.5 V
8
Switching Duration (ns)
7
6
ACKNOWLEDGMENT
5
The authors wish to acknowledge financial support from
French programs ANR-MARS, ANR-DIPMEM and the
European FP7 program through MAGWIRE (257707).
4
3
2
REFERENCES
1
0
70
80
90
100
110
Area (F2)
120
130
140
150
Fig.8. Tradeoff dependence of switching duration versus area and pulse
magnitude
Moreover, due to the stochastic feature, the switch for
neighbor states could be ultra-fast. If it can be controlled
strictly and properly, for instance, integrating with “SelfEnable” switching mechanism [19] (see Fig.9), this device
can be advantageous in terms of fast speed and low power
consumption. In the “Self–Enable” switching circuit, besides
the synchronized Pre-charge sense amplifier (PCSA) [20]
and switching circuit, the comparison logic (Com Logic)
circuit is able to control the input signal by monitoring the
state change of MLCs. The input pulse will be automatically
blocked once the state of MLC changes. This makes the
switching operation deterministic instead of stochastic,
which saves a great deal of energy consumed by the
conventional iterations for probabilistic switching [8]. .
Output
Input
Vdda
SelfBi-directional STT Enable Com
Logic
switching circuit
PCSA
SL
WL
WL
M
L
C
RL
WL
M
L
C
M
L
C
RL
R
e
f
1
RL
R
e
f
2
R
e
f
3
Gnd
Fig.9. MLCs served by Self-Enable switching circuit
IV. CONCLUSION AND DISCUSSION
In this paper, we presented a design of MLC based on
the STT stochastic switching behavior in PMA MRAM,
which allows lower power and higher storage density. Two
types of structures, in parallel and in serial, were introduced
and analyzed. By using a stochastic compact model of PMA
STT-MTJ and CMOS 40 nm design kit, these structures
were validated by Monte-Carlo statistical simulations. The
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