IEEE TRANSACTIONS ON MAGNETICS, VOL. 49, NO. 7, JULY 2013
4375
Electrical Modeling of Stochastic Spin Transfer Torque Writing in Magnetic
Tunnel Junctions for Memory and Logic Applications
Yue Zhang
, Weisheng Zhao , Guillaume Prenat , Thibaut Devolder , Jacques-Olivier Klein
Claude Chappert , Bernard Dieny , and Dafiné Ravelosona
,
IEF, Univ. Paris-Sud, Orsay, 91405, France
CNRS, UMR 8622, Orsay, 91405, France
SPINTEC Laboratory, CEA/CNRS, Grenoble, 38054, France
Magnetic tunnel junctions (MTJ) are considered as one of the most promising candidates for the next generation of nonvolatile memories and programmable logic chips. Spin transfer torque (STT) in CoFeB/MgO/CoFeB MTJs with perpendicular magnetic anisotropy
(PMA) exhibits noticeable performance enhancements compared to that with In-plane magnetic anisotropy, particularly in terms of
thermal stability, critical current for switching, access speed and power consumption. However, the STT switching of MTJ has been
revealed stochastic, which results from unavoidable thermal fluctuations of magnetization. This leads to the occurrence of write errors
which deeply affects the reliability of hybrid CMOS/MTJ circuits. In this paper, we present the first spice-compact model of CoFeB/
MgO/CoFeB structure PMA-MTJ integrating STT stochastic behaviors. Depending on the relative magnitude between the switching
current (I) and the critical current (Ico), the STT stochastic behaviors of this PMA-MTJ can be categorized into two regions: Sun model
and Neel-Brown model
. The Monte-Carlo simulations for single cell and hybrid CMOS/MTJ circuits show the
stochastic behaviors in both writing and sensing operations. This model can be very useful for investigating the reliability issues during
the design and simulation before process fabrication.
Index Terms—Compact modeling, magnetic tunnel junction, nonvolatile, perpendicular magnetic anisotropy, stochastic behavior.
I. INTRODUCTION
S
PINTRONICS is an emergent technology beyond CMOS
which can help reducing the static and dynamic power consumption of CMOS circuits beyond the 90 nm technology node
[1]. Magnetic tunnel junctions (MTJ) are key basic elements
in spintronics. They essentially consist of three layers (a thin
tunnel oxide layer sandwiched between two ferromagnetic (FM)
layers) [2]. Due to the tunnel magnetoresistance (TMR) effect,
the nanopillar resistance,
or
, depends on the relative
orientation, Parallel (P) or Anti-Parallel (AP), of the magnetization of the two FM layers [3]. Remarkably, in MgO based
MTJs, the
can reach a quite
high value (e.g., 600%) at room temperature, which allows
the state of MTJs to be easily detected by CMOS sense amplifiers [4]. It is possible to switch from one configuration to the
opposite by using the Spin-Transfer Torque phenomenon (STT)
[Fig. 1(a)]. Nowadays, STT-RAM are regarded as one of the
most promising candidates for next generation of nonvolatile
memories and programmable logic chips thanks to their performances in terms of power consumption, miniaturization and integration with CMOS process [5], [6]. MTJ with perpendicular
magnetic anisotropy (PMA) attract even more attention compared to their In-plane magnetized counterparts because of their
improved performances in many aspects [7], [8]. STT PMA
MTJ can combine good thermal stability, low critical current
and high access speed. We presented recently a spice compact
model for memory and logic simulation, which integrates the
static and dynamic behaviors of STT PMA MTJ [9].
Manuscript received October 29, 2012; accepted January 14, 2013. Date
of current version July 15, 2013. Corresponding author: W. Zhao (e-mail:
weisheng.zhao@u-psud.fr).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMAG.2013.2242257
Fig. 1. (a) Spin transfer torque switching mechanism: the MTJ state changes
from parallel (P) to anti-parallel (AP) under positive electron flow direction
. It changes from AP to P under negative electron flow direction
. Note that the red arrows represent the electron flow and not the
current (b) experimental measurement of STT stochastic switching behaviors,
high writing current drives faster speed and higher switching probability.
However, the STT switching of MTJ has been revealed intrinsically stochastic [see Fig. 1(b)] [10], which results from the
unavoidable thermal fluctuations of magnetization [11]. They
are responsible for large fluctuations in the switching duration,
the latter following a sigmoidal distribution with exponential
tails [11]. Because of this phenomenon, some write errors might
occur. For instance, desired data may not be correctly stored
in writing operation and unexpected switching may happen in
sensing operation. This phenomena deeply affect the reliability
of hybrid CMOS/MTJ circuits [12].
In order to be able to investigate these reliability issues by
electrical simulation during the design, before process fabrication, we developed a spice-compatible model of PMA-MTJ integrating these STT stochastic behaviors. It is written in Verilog-A language [13], which is compatible with standard CMOS
computer-aided design tools (e.g., Cadence platform) and can
provide an easy parameter interface. The physical models to describe the stochastic behaviors will be explained in detail in the
Section II. After that, by using this accurate spice-model and
CMOS 40 nm design-kit [14], we performed Monte-Carlo (MC)
simulations for single cell and hybrid CMOS/MTJ circuits to
0018-9464/$31.00 © 2013 IEEE
4376
IEEE TRANSACTIONS ON MAGNETICS, VOL. 49, NO. 7, JULY 2013
TABLE I
PARAMETERS AND VARIABLES PRESENT IN THE FITTING FUNCTIONS
demonstrate and validate the model stochastic behavior in both
writing and sensing operations. The reliability analysis will also
be carried out.
II. PHYSICAL MODELS USED
TO DESCRIBE
BEHAVIOR
STOCHASTIC
Recently, lot of experimental and theoretical results have
shown that, although STT switching may allow subnanosecond
switching duration, the switching process of STT is stochastic
[15]–[17]. Furthermore, depending on the relative magnitude
between switching current
and critical current
, the
STT stochastic behaviors of this PMA-MTJ can be categorized
into two regions: Sun model
and Neel-Brown model
[18], [19]. For practical applications, the two regions have their own specific interest: The region of Sun model
addresses fast switching (sub 3 ns) but high current density.
The region of Neel-Brown model addresses low current density
but slower switching.
These two regions are separated by the critical current which
is defined as follows for p-MTJ [7]:
(1)
(2)
where E is the barrier energy,
is the effective anisotropy
field,
is permeability of free space,
is the saturation magnetization, is the magnetic damping constant, is the gyromagnetic ratio, e is the elementary charge,
is the Bohr magneton, V is the volume of the free layer,
is the Boltzmann
constant, and
is the
spin polarization efficiency factor [20]. The default values of
the critical parameters used in this model are given in Table I.
Sun model is used to describe the case where the current
flowing through the MTJ exceeds the critical current. In this
switching mechanism, the switching is triggered by a thermal
fluctuation which creates an initial angle between the current
spin-polarization and the magnetization of the storage layer. The
switching duration then follows a normal distribution centered
on the average switching delay time. The average switching
delay time is expressed by [8]
(3)
Fig. 2. 100 complete writing operation simulations (parallel (P) to antiparallel
(AP) and back to parallel (P)).
where
is the Euler’s constant,
the
thermal stability factor, T is the temperature,
,
the
tunneling spin polarizations of the reference and free layers assumed to be equal
in this compact model,
m is the magnetic moment of free layer.
In the corresponding subthreshold region (
, NeelBrown model), the switching can still occur thanks to thermal
activation above the voltage/current-dependent barrier. In this
region, the switching probability can be described by [21]:
(4)
(5)
is the attempt period. From (4), the probability denwhere
sity function (PDF) of the switching duration in this region follows an exponential distribution with characteristic time decreasing with the current density. From the above expressions,
it follows that in both regions, increasing the switching probability requires either to increase the write current or the current
pulse duration. It could also be of great benefit for tolerating the
high mismatch and process variations [22], [23].
In order to integrate the stochastic behaviors into our model,
we used the random statistical functions provided by Verilog-A
[13]. For example, we utilize the function “$rdist_normal” to
generate a normal distribution and the function “$rdist_exponential” to generate an exponential distribution. To verify the
functionality of this STT simulation model taking into account
these stochastic aspects, writing and sensing operations of
single MTJ cell were simulated respectively. Fig. 2 shows a
simulation of 100 writing operations. As expected the switching
probability follows a normal distribution around the average
switching delay time as calculated by (3).
The dependence of sensing Bit Error Rate (BER_S) versus
sensing current for different duration pulses is illustrated in
Fig. 3. The BER_S grows exponentially with respect to the
sensing current, which is consistent with the switching probability theory described by (4)–(5). In addition, for a fixed
amplitude of sensing current, increasing the read current pulse
duration yields an increase in switching probability meaning an
increase of probability of undesired write during read.
ZHANG et al.: ELECTRICAL MODELING OF STOCHASTIC SPIN TRANSFER TORQUE WRITING IN MAGNETIC TUNNEL JUNCTIONS
Fig. 3. Dependence of sensing bit error rate (BER_S) versus sensing current
for different switching duration pulses.
4377
Fig. 5. Monte-Carlo simulation of a whole writing operation implemented by
the writing circuit shown in Fig. 4.
Fig. 4. Schematic for STT writing circuit to generate a bidirectional current,
which is composed of 2 NMOS and 2 PMOS.
III. MONTE-CARLO SIMULATION OF HYBRID MTJ/CMOS
CIRCUIT AND RELIABILITY ANALYSIS
Fig. 6. Dependence of writing Bit Error Rate (BER_W) versus die area of
writing circuit.
Beyond the 90 nm node, high reliability is becoming more
and more crucial for the IC design. As mentioned above, thanks
to the integration of STT stochastic behavior into this model,
an overall reliability investigation is possible. Normally a MC
statistical analysis is used to perform the reliability simulation
taking into account mismatch and process variation. Thanks to
this model, the MTJ intrinsic stochastic behavior will be taken
into account as well.
Beyond the single cell simulation shown in the above section, hybrid MTJ/CMOS circuit should also be simulated to
validate this model. In order to do that, a STT writing circuit
was designed, composed of 2 NMOS
and 2 PMOS
(Fig. 4). By controlling the input signals (
and
), this circuit can generate a bidirectional current to
switch the MTJ cell. Fig. 5 shows the MC simulation of 100
complete writing operations using the writing circuit shown in
Fig. 4. The writing current at each write event is different because of the mismatch and process variation of CMOS part. The
switching delay times vary randomly due to the stochastic behavior of MTJ cell.
We have also performed the MC simulations for different
writing pulse durations (5 ns, 10 ns and 20 ns) to observe the
dependence of write bit error rate (BER_W) versus die area
of writing circuit (four transistors). The simulation results (see
Fig. 6) demonstrate their tradeoff relation: the increase of area
can improve the BER performance. The reason is that a larger
circuit allows larger write current, which in average reduces
the time required to switch. For a given pulse duration, this increases the switching probability. Correlatively, it is observed
that a longer pulse increases the reliability, which confirms the
explanation mentioned in Section II.
Furthermore, another important reliability issue has to be considered: the sensing reliability. Precharge sense amplifier is proposed to provide not only the best sensing reliability and power
efficiency, but also high-speed performance [24]. In reality, to
realize a memory-in-logic function, numbers of words of memories (e.g. 1 k) normally share a sense amplifier. As shown in
Fig. 7, a 16 k-bits (1 k words of 16 bits) PCSA sensing circuit
has been simulated. One unit of PCSA sensing circuit consists of
precharge subcircuit
discharge subcircuit
and a pair of inverters
. This enormous
parallel structure leads to a huge capacitance, which drives the
current pulse through the MTJ. As a result, an evaluation phase
lasts almost 10 ns. In order to clarify the effect of stochastic behavior, the MC simulation after 1 us of sensing duration (i.e.
1000-times sensing operations) has been studied (see Fig. 8).
We found that the 33 errors occurred among 100 simulations.
Similarly to the case of the writing circuit, they are caused by
either mismatch and process variations of CMOS part or STT
stochastic behaviors of MTJ, or sometimes by both of them.
To identify the impact from each of them, we also performed
MC simulations for sensing circuit with only mismatch and
process variations. We found that the BER_S was 11%. Compared with the result presented in Fig. 8, the stochastic behaviors
of MTJ greatly increase the error probability for a long-pulse
current.
4378
IEEE TRANSACTIONS ON MAGNETICS, VOL. 49, NO. 7, JULY 2013
ACKNOWLEDGMENT
This work was supported in part by French programs
ANR-MARS, ANR-DIPMEM, and the European FP7 program
through MAGWIRE (257707).
REFERENCES
Fig. 7. Schematic for 16 k-bits PCSA sensing circuit (
,
).
Fig. 8. Monte-Carlo simulation of a 16 k-bits PCSA circuit.
IV. CONCLUSION
In this paper, we presented a compact model of CoFeB/MgO/
CoFeB PMA MTJ integrating STT stochastic behaviors. It can
be very helpful for the reliability investigation of STT-MRAM,
which is one of major issues for advanced node integration.
Two classic STT physic models, Sun model
and
Neel-Brown model
, were used to describe in detail
the stochastic behaviors. As it is programmed with Verilog-A
language, this model can be easily extended to other PMA MTJ
structures. Single cell simulations were firstly performed to validate its behaviors. Based on this model and CMOS 40 nm design
kit, 1-bit writing and 16 k-bits sensing circuits were simulated to
demonstrate its usefulness for circuit performance analysis and
optimizations. By using this model, stochastic effect in other
complex circuits can be further investigated [25], [26].
[1] C. Chappert, A. Fert, and F. N. Van Dau, “The emergence of spin electronics in data storage,” Nat. Mater., vol. 6, p. 813, 2007.
[2] International Roadmap for semiconductor (ITRS) 2011, ERD Update.
[3] M. Julliere, “Tunneling between ferromagnetic films,” Phys. Lett. A,
vol. 54, pp. 225–226, 1975.
[4] S. Ikeda et al., “Tunnel magnetoresistance of 604% at 300 K by suppression of Ta diffusion in CoFeB/MgO/CoFeB pseudo-spin-valves
annealed at high temperature,” Appl. Phys. Lett, vol. 93, p. 082508,
2008.
[5] J. C. Slonczewski, “Current-driven excitation of magnetic multilayers,” J. Magn. Magn. Mater., vol. 159, pp. L1–L7, 1996.
[6] B. Dieny et al., “Spin-transfer effect and its use in spintronic components,” Int. J. Nanotechnol., vol. 7, pp. 591–614, 2010.
[7] S. Ikeda et al., “A perpendicular-anisotropy CoFeB-MgO magnetic
tunnel junction,” Nat. Mater., vol. 9, pp. 721–724, 2010.
[8] D. C. Worledge et al., “Spin torque switching of perpendicular
—Based magnetic tunnel junctions,” Appl. Phys.
Lett., vol. 98, p. 022501, 2011, 2.
[9] Y. Zhang et al., “Compact modeling of perpendicular-anisotropy
CoFeB/MgO magnetic tunnel junctions,” IEEE Trans. Electron Devices, vol. 59, no. 3, pp. 819–826, 2012.
[10] T. Devolder et al., “Single-shot time-resolved measurement of
nanosecond-scale spin-transfer induced switching: Stochastic versus
deterministic aspects,” Phys. Rev. Lett., vol. 100, p. 057206, 2008.
[11] M. Marins de Castro et al., “Processional spin-transfer switching in a
magnetic tunnel junction with a synthetic anti-ferromagnetic perpendicular polarizer,” J Appl. Phys., 2012:111:07C912.
[12] G. Prenat et al., “CMOS/magnetic hybrid architectures,” in Proc.
IEEE-ICECS, Morocco, 2007, pp. 190–193.
[13] “Verilog-A Manuel” Agilent, 2007 [Online]. Available: http://www.
designers-guide.org/
[14] “Manuel of Design Kit for CMOS 40 nm,” STMicroelectronics, 2012.
[15] J. J. Nowak, R. P. Robertazzi, J. Z. Sun, G. Hu, D. W. Abraham, P. L.
Trouilloud, and S. Brown et al., “Demonstration of ultralow bit error
rates for spin-torque magnetic random-access memory with perpendicular magnetic anisotropy,” IEEE Magn. Lett., vol. 2, p. 3000204, 2011.
[16] Z. Wang, Y. Zhou, J. Zhang, and Y. Huai, “Bit error rate investigation
of spin-transfer-switched magnetic tunnel junctions,” Appl. Phys. Lett.,
vol. 101, pp. 142406–142406-4, 2012.
[17] W. S. Zhao, Y. Zhang, T. Devolder, J. O. Klein, D. Ravelosona, C.
Chappert, and P. Mazoyer, “Failure and reliability analysis of STTMRAM,” Microelectron. Rel., vol. 52, pp. 1848–1852, 2012.
[18] R. H. Koch, J. A. Katine, and J. Z. Sun, “Time-resolved reversal of spintransfer switching in a nanomagnet,” Phys. Rev. Lett., vol. 92, 2004.
[19] R. Heindl et al., “Validity of the thermal activation model for spintransfer torque switching in magnetic tunnel junctions,” J. Appl. Phys.,
vol. 109, 2011.
[20] J. Z. Sun et al., “Effect of subvolume excitation and spin-torque efficiency on magnetic switching,” Phys. Rev. B, vol. 84, 2011.
[21] L. Faber et al., “Dynamic compact model of spin-transfer torque based
magnetic tunnel junction (MTJ),” in Proc. IEEE Design Technol. Integrated Syst. (DTIS), 2009, pp. 130–135.
[22] K. Lee and S. H. Kang, “Development of embedded STT-MRAM for
mobile system-on-chips,” IEEE Trans. Magn., vol. 47, no. 1, p. 131,
Jan. 2011.
[23] Y. Kim et al., “Integration of 28 nm MTJ for 8–16 Gb level MRAM
with full investigation of thermal stability,” in Proc. IEEE Symp. VLSI
Technol., 2011, pp. 210–211.
[24] W. S. Zhao, C. Chappert, V. Javerliac, and J.-P. Noziere, “High speed,
high stability and low power sensing amplifier for MTJ/CMOS hybrid
logic circuits,” IEEE Trans. Magn., vol. 45, pp. 3784–3787, 2009.
[25] K. Nepal et al., “Designing MRF based error correcting circuits for
memory elements,” Proc. IEEE-DATE, pp. 792–793, 2006.
[26] Y. Lakys et al., “Self-enabled “error-free” switching circuit for spin
transfer torque MRAM and logic,” IEEE Trans. Magn., vol. 48, pp.
2403–2406, 2012.