Basic PLL Building Blocks (Part II), High Speed Frequency Dividers
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Short Course On
Phase-Locked Loops and Their Applications
Day 2, PM Lecture
Basic Building Blocks (Part II)
High Speed Frequency Dividers, Phase Detectors,
Charge Pumps, and Loop Filter Design
Michael Perrott
August 12, 2008
Copyright © 2008 by Michael H. Perrott
All rights reserved
Fractional-N Frequency Synthesis
Fout = M.F Fref
Fref
ref(t)
e(t) Charge
PFD
Pump
Loop
Filter
v(t)
out(t)
VCO
div(t)
Nsd[m]
Divider
N[m]
Σ−Δ
Modulator
M+1
M
Σ−Δ
Quantization
Noise
M.H. Perrott
f
Challenging building blocks
- VCO
- Divider
- Charge Pump (and PFD)
2
Outline of Talk
High speed frequency dividers
PFD and Charge Pumps
Loop filter design
M.H. Perrott
- Background of key digital building blocks
- Closed loop PLL design using CAD
3
Digital Background for Dividers
Edge-triggered Registers
Single-Ended Register
IN
Differential Register
MASTER
SLAVE
MASTER
SLAVE
LATCH
LATCH
LATCH
LATCH
D
Q
D
Q
Φ
Φ
Φ
Φ
OUT
IN
S
IN
R
Φ
Q
S
Q
R
Φ
Φ
Q
OUT
Q
OUT
Φ
Achieved by cascading two latches that are
transparent out of phase from one another
Two general classes of latches
- Static – employ positive feedback
Robust
- Dynamic – store charge on parasitic capacitance
Smaller, lower power in most cases
Negative: must be refreshed (due to leakage currents)
M.H. Perrott
5
Static Latches
LATCH
IN
S
Q
OUT
IN
R
Q
OUT
Φ
Q
Q
Φ
Φ
S
R
Φ
Classical case employs cross-coupled NAND/NOR
gates to achieve positive feedback
Above example uses cross-coupled inverters for
positive feedback
Set, reset, and clock transistors designed to have
enough drive to overpower cross-coupled inverters
Relatively small number of transistors
Robust
M.H. Perrott
6
Dynamic Latches
IN
MASTER
SLAVE
LATCH
LATCH
D
Q
D
Φ
Q
Φ
Φ
Φ
Φ
OUT
Φ
IN
OUT
Φ
Φ
Leverage CMOS technology
- High quality switches with small leakage available
- Can switch in and store charge on parasitic
capacitances quite reliability
M.H. Perrott
Achieves faster speed than full swing logic with fewer
transistors
Issues: higher sensitivity to noise, minimum refresh
rate required due to charge leakage
7
True Single Phase Clocked (TSPC) Latches
Doubled n-C2MOS latch
Doubled p-C2MOS latch
LATCH
IN
OUT
D
IN
OUT
Φ
Q
Φ
Φ
Φ
Φ
IN
OUT
Φ
Allow register implementations with only one clock!
- Latches made transparent at different portions of clock
cycle by using appropriate latch “flavor” – n or p
n latches are transparent only when Φ is 1
p latches are transparent only when Φ is 0
M.H. Perrott
Benefits: simplified clock distribution, high speed
8
Example TSPC Registers
Positive edge-triggered version
SLAVE
IN
Φ
MASTER
OUT
Φ
Φ
Φ
Negative edge-triggered version
MASTER
SLAVE
IN
Φ
Φ
Φ
Φ
OUT
M.H. Perrott
9
A Simplified Approach to TSPC Registers
Clever implementation of TSPC approach can be
achieved with reduced transistor count
Positive-edge triggered
Negative-edge triggered
Φ
IN
Φ
OUT
Φ
Φ
Φ
IN
Φ
Φ
OUT
Φ
For more info on TSPC approach, see
- J. Yuan and C. Svensson, “New Single-Clock CMOS
Latches and Flipflops with Improved Speed and Power
Savings”, JSSC, Jan 1997, pp 62-69
M.H. Perrott
10
Embedding of Logic within Latches
Φ
LATCH
IN
Logic Function
(NAND,NOR, etc.)
OUT
OUT
D
Q
Φ
IN
PDN
Φ
Φ
Φ
We can often increase the speed of a logic function
fed into a latch through embedding
- Latch slowed down by extra transistors, but logic/latch
combination is faster than direct cascade of the
functions
Method can be applied to both static and dynamic
approaches
- Dynamic approach shown above
M.H. Perrott
11
Highest Speed Achieved with Differential CML Latch
Load
Load
OUT
OUT
IN
IN
LATCH
IN
S
Q
OUT
IN
R
Q
Φ
OUT
Φ
Φ
Φ
Φ
Employs positive feedback for memory
Method of operation
M.H. Perrott
Φ
- Realized with cross-coupled NMOS differential pair
- Follow mode: current directed through differential
amplifier that passes input signal
- Hold mode: current shifted to cross-coupled pair
12
High Speed Frequency Dividers
High Speed Frequency Dividers in Wireless Systems
Zin
From Antenna
and Bandpass
Filter
PC board
trace
Zo
Mixer
RF in
Package
Interface
IF out
To Filter
LNA
LO signal
VCO
Reference ref(t) Frequency v(t)
Frequency
Synthesizer
ref(t)
e(t) Charge
PFD
Pump
out(t)
Loop
Filter
v(t)
out(t)
VCO
div(t)
Divider
N
Design Issues: high speed, low power
M.H. Perrott
14
Divide-by-2 Circuit (Johnson Counter)
Register
LATCH 1
LATCH 2
D
D
Q
clk
IN
IN
M.H. Perrott
Q
Q
clk
Q
OUT
TIN
OUT
IN
OUT
Achieves frequency division by clocking two latches
(i.e., a register) in negative feedback
Latches may be implemented in various ways
according to speed/power requirements
15
Divide-by-2 Using a TSPC register
OUT
IN
OUT
IN
Advantages
Disadvantages
- Reasonably fast, compact size
- No static power dissipation, differential clock not required
M.H. Perrott
- Slowed down by stacked PMOS, signals goes through
three gates per cycle
- Requires full swing input clock signal
16
Divide-by-2 Using Razavi’s Topology
IN
IN
IN
IN
Φ1
Φ1
Φ3
Φ2
Φ4
Φ2
Φ3
Φ4
Φ1
Φ3
Φ2
Φ4
Faster topology than TSPC approach
See B. Rezavi et. al., “Design of High Speed, Low Power
Frequency Dividers and Phase-Locked Loops in Deep
Submicron CMOS”, JSSC, Feb 1995, pp 101-109
M.H. Perrott
17
Explanation of Razavi Divider Operation (Part 1)
IN
Φ1
Φ2
IN
Φ3
Φ2
Φ4
Φ3
Φ4
Φ1
Left latch:
- Clock drives current from PMOS devices of a given latch
onto the NMOS cross-coupled pair
- Latch output voltage rises asymmetrically according to
voltage setting on gates of outside NMOS devices
Right latch:
- Outside NMOS devices discharge the latch output
voltage as the left latch output voltage rises
M.H. Perrott
18
Explanation of Razavi Divider Operation (Part 2)
IN
Φ1
Φ2
IN
Φ3
Φ2
Φ4
Φ3
Φ4
Φ1
Right latch:
- Clock drives current from PMOS devices of a given latch
onto the NMOS cross-coupled pair
- Latch output voltage rises asymmetrically according to
voltage setting on gates of outside NMOS devices
Left latch:
- Outside NMOS devices discharge the latch output
voltage as the left latch output voltage rises
M.H. Perrott
19
Explanation of Razavi Divider Operation (Part 3)
IN
Φ1
Φ2
IN
Φ3
Φ2
Φ4
Φ4
Φ3
Φ1
Process starts over again with current being driven
into left latch
- Voltage polarity at the output of the latch has now
flipped
M.H. Perrott
20
Advantages and Disadvantages of Razavi Topology
IN
IN
IN
IN
Φ1
Φ1
Φ3
Φ2
Φ4
Φ2
Φ3
Φ4
Φ1
Φ3
Φ2
Φ4
Advantages
- Fast – no stacked PMOS, signal goes through only two
gates per cycle
Disadvantages
Note: quarter period duty cycle can be turned into fifty
percent duty cycle with OR gates after the divider
- Static power
- Full swing, differential input clock signal required
- See my thesis at http://www-mtl.mit.edu/~perrott
M.H. Perrott
21
Divide-by-2 Using Wang Topology
IN
IN
IN
Φ1
Φ2
Φ3
Φ4
Φ2
Φ3
Φ4
Φ1
IN
Φ1
Φ3
Φ2
IN
IN
Φ4
Claims to be faster than Razavi topology
- Chief difference is addition of NMOS clock devices and
different scaling of upper PMOS devices
M.H. Perrott
See HongMo Wang, “A 1.8 V 3 mW 16.8 GHz Frequency
Divider in 0.25μm CMOS”, ISSCC 2000, pp 196-197
22
Explanation of Wang Topology Operation (Part 1)
IN
Φ1
Φ2
IN
Φ3
Φ2
Φ4
IN
Φ4
Φ3
Φ1
IN
Left latch
- Current driven into latch and output voltage responds
similar to Razavi architecture
Right latch
- Different than Razavi architecture in that latch output
voltage is not discharged due to presence of extra NMOS
M.H. Perrott
23
Explanation of Wang Topology Operation (Part 2)
IN
Φ1
Φ2
Φ3
Φ2
Φ4
IN
IN
Φ3
Φ4
Φ1
IN
Same process repeats on the right side
- The left side maintains its voltages due to presence of
NMOS device
M.H. Perrott
24
Advantages and Disadvantages of Wang Topology
IN
IN
IN
Φ1
Φ3
Φ2
Φ4
Φ2
Φ3
Φ4
Φ1
IN
Φ1
Φ3
Φ2
IN
IN
Φ4
Advantages
- Fast – no stacked PMOS, signal goes through only two
gates per cycle
M.H. Perrott
Disadvantages
- Static power
- Full swing, differential input clock signal required
25
Divide-by-2 Using CML Latches
Φ3
Load
Load
Φ2
Load
Load
Φ1
Φ2
Φ4
Φ3
IN
IN
IN
Φ4
Φ1
IN
IN
IN
Φ1
Φ3
Φ2
Φ4
M.H. Perrott
Fastest structure uses resistors for load
26
Explanation of CML Topology Operation (Part 1)
Φ3
Φ2
Φ4
IN
Load
Load
Φ2
Load
Load
Φ1
Φ3
IN
Φ4
Φ1
IN
IN
Left latch
- Current directed into differential amp portion of latch
Latch output follows input from right latch
Right latch
- Current directed into cross-coupled pair portion of latch
Latch output is held
M.H. Perrott
27
Explanation of CML Topology Operation (Part 2)
Φ3
Φ2
Φ4
IN
Load
Load
Φ2
Load
Load
Φ1
Φ4
Φ3
IN
Φ1
IN
IN
Left latch
- Current is directed into cross-coupled pair
Latch output voltage retained
Right latch
- Current is directed into differential amp
Latch output voltage follows input from left latch
M.H. Perrott
28
Explanation of CML Topology Operation (Part 3)
Φ3
Φ2
Φ4
IN
M.H. Perrott
Φ3
IN
IN
Load
Load
Φ2
Load
Load
Φ1
Φ4
Φ1
IN
Same process repeats on left side
- Voltage polarity is now flipped
29
Advantages and Disadvantages of CML Topology
Advantages
- Very fast – no PMOS at all, signal goes through only two
gates per cycle
- Smaller input swing for input clock than previous
approaches
Allows signal transitioning at higher frequencies
Disadvantages
Note: additional speedup can be obtained by using
inductor peaking (i.e., place inductor in load)
M.H. Perrott
- Static power
- Differential signals required
- Large area compared to previous approaches
- Biasing sources required
30
Creating Higher Divide Values (Synchronous Approach)
Register
1
T
Q
clk
Q
A
Register
T
Q
clk
Q
B
Register
T
OUT
Q
clk
IN
Q
Toggle Register
IN
Register
A
T
D
B
clk
Q
Q
Q
Q
OUT
clk
Cascades toggle registers and logic to perform division
- Advantage: low jitter (explained shortly)
- Problems: high power (all registers run at high frequency),
high loading on clock (IN signal drives all registers)
M.H. Perrott
31
Creating Higher Divide Values (Asynchronous Approach)
IN
2
A
2
B
2
OUT
IN
A
B
OUT
Higher division achieved by simply cascading
divide-by-2 stages
Advantages over synchronous approach
Disadvantage: jitter is larger
M.H. Perrott
- Lower power: each stage runs at a lower frequency,
allowing power to be correspondingly reduced
- Less loading of input: IN signal only drives first stage
32
Jitter in Asynchronous Designs
In
X
Y
Out
Each logic stage adds jitter to its output
- Jitter accumulates as it passes through more and more
gates
M.H. Perrott
33
Jitter in Synchronous Designs
In
X
Register
Y
D
Q
clk
Out
Q
CLK
Transition time of register output is set by the clock,
not the incoming data input
- Synchronous circuits have jitter performance
corresponding to their clock
- Jitter does not accumulate as signal travels through
synchronous stages
M.H. Perrott
34
High Speed, Low Power Asynchronous Dividers
IN
Differential
CML registers
(for high speed)
A
IN
2
2
A
Full Swing
TSPC registers
(to save power)
B
B
Differential to
Full Swing
Converter
B
2
C
2
OUT
IN
A
B
C
OUT
Highest speed achieved with differential CML registers
- Static power consumption not an issue for high speed
sections, but wasteful in low speed sections
Lower power achieved by using full swing logic for low
speed sections
M.H. Perrott
35
Differential to Full Swing Converter
Vdd
Vin
Vin
Inverter
Threshold
Voltage
Y
M.H. Perrott
0
Out
Use an opamp style circuit to translate differential
input voltage to a single-ended output
Use an inverter to amplify the single-ended output to
full swing level
36
Issue: Architecture Very Sensitive to DC Offset
Vdd
Vin
Vin
Inverter
Threshold
Voltage
Y
0
Out
Opamp style circuit has very high DC gain from Vin to
node Y
DC offset will cause signal to rise above or fall below
inverter threshold
- Output signal rails rather than pulsing
M.H. Perrott
37
Use Resistor Feedback to Reduce DC Gain
Vdd
Vin
Vin
Inverter
Threshold
Voltage
Y
0
Vdd
Rf
Out
0
Idea: create transresistance amplifier rather than voltage
amplifier out of inverter by using feedback resistor
- Presents a low impedance to node Y
- Current from opamp style circuit is shunted through resistor
- DC offset at input shifts output waveform slightly, but not
node Y (to first order)
Circuit is robust against DC offset!
M.H. Perrott
38
Alternate Implementation of Inverter Feedback
Vdd
Vin
Vdd
Vin
Y
0
Out
0
M.H. Perrott
Nonlinear feedback using MOS devices can be used
in place of resistor
- Smaller area than resistor implementation
Analysis done by examining impact of feedback when
output is high or low
39
Impact of Nonlinear Feedback When Output is High
Vdd
Vin
Vdd
Vin
Y
0
Vgs
Out
0
Corresponds to case where current flows into node Y
Output is approximately set to Vgs of NMOS feedback
device away from inverter threshold voltage
- NMOS device acts like source follower
- PMOS device is shut off
- Inverter input is set to a value that yields that output voltage
High DC gain of inverter insures it is close to inverter threshold
M.H. Perrott
40
Impact of Nonlinear Feedback When Output is Low
Vdd
Vin
Vdd
Vin
Y
0
Vsg
Out
0
Corresponds to case where current flows out of node Y
Output is approximately set to Vgs of PMOS feedback
device away from inverter threshold voltage
- NMOS device is shut off
- PMOS device acts like source follower
- Inverter input is set to a value that yields that output voltage
High DC gain of inverter insures it is close to inverter threshold
M.H. Perrott
41
Variable Frequency Division
Prescaler
IN
Asynchronous
Divider
Synchronous
Divider
OUT
Control Logic
Divide Value (N)
Classical design partitions variable divider into two sections
- Asynchronous section (called a prescaler) is fast
Often supports a limited range of divide values
- Synchronous section has no jitter accumulation and a wide
range of divide values
- Control logic coordinates sections to produce a wide range of
divide values
M.H. Perrott
42
Dual Modulus Prescalers
IN
2/3
A
2
B
2
OUT
CON*
CON
Control
Qualifier
8 + CON Cycles
IN
A
B
OUT
CON
CON*
Dual modulus design supports two divide values
-
In this case, divide-by-8 or 9 according to CON signal
One cycle resolution achieved with front-end “2/3” divider
M.H. Perrott
43
Divide-by-2/3 Design (Classical Approach)
Reg B
Reg A
D
IN
Q
Y
D
Q
OUT
Q
Q
2/3
CON *
Normal mode of operation: CON* = 0 ) Y = 0
Divide-by-3 operation: CON* = 1 ) Y = 1
- Register B acts as divide-by-2 circuit
- Reg B remains high for an extra cycle
Causes Y to be set back to 0 ) Reg B toggles again
CON* must be set back to 0 before Reg B toggles to
prevent extra pulses from being swallowed
M.H. Perrott
44
Control Qualifier Design (Classical Approach)
IN
A
2/3
2
B
2
OUT
CON*
CON
Control
Qualifier
IN
A
B
OUT
CON
CON*
Must align CON signal to first “2/3” divider stage
- CON signal is based on logic clocked by divider output
There will be skew between “2/3” divider timing and CON
M.H. Perrott
Classical approach cleverly utilizes outputs from each
section to “gate” the CON signal to “2/3” divider
45
Multi-Modulus Prescalers
CON0
IN
2/3
CON1
A
2/3
CON2
B
2/3
OUT
8 + CON0 *20 + CON1 *21 + CON2 *22
IN
A
B
OUT
Cascaded 2/3 sections achieves a range of 2n to 2n+1-1
Asynchronous design allows high speed and low
power operation to be achieved
M.H. Perrott
- Above example is 8/ L /15 divider
- Only negative is jitter accumulation
46
A More Modular Design
2/3
IN
IN
OUT
modout modin
CON
CON0
2/3
A
IN
2/3
B
OUT
modout modin
CON
CON1
IN
OUT
OUT
modout modin
CON
Vdd
CON2
8 + CON0 *20 + CON1 *21 + CON2 *22
IN
A
B
OUT
Perform control qualification by synchronizing within
each stage before passing to previous one
- Compare to previous slide in which all outputs required
for qualification of first 2/3 stage
M.H. Perrott
See Vaucher et. al., “A Family of Low-Power Truly
Modular Programmable Dividers …”, JSSC, July 2000
47
Implementation of 2/3 Sections in Modular Approach
2/3 Circuits
LATCH
CON *
D
LATCH
Q
clk
D
Q
Q
clk
Q
OUT
IN
modout
LATCH
Q
Q
LATCH
D
Q
Q
clk
D
clk
modin
Control
Qualifier
Circuits
CON
Approach has similar complexity to classical design
Cleverly utilizes “gating” register to pass synchronized
control qualifying signal to the previous stage
M.H. Perrott
- Consists of two registers with accompanying logic gates
48
Implementation of Latch and And Gate in 2/3 Section
RL
RL
Q
D
Q
CLK
Q
B
clk
A
A
LATCH
A
B
Q
B
Q
CLK
CLK
Combine AND gate and latch for faster speed and lower
power dissipation
Note that all primitives in 2/3 Section on previous slide
consist of this combination or just a straight latch
M.H. Perrott
49
Can We Go Even Faster?
Speed Limitations of Divide-by-2 Circuit
delay1
delay2
D Register
LATCH 1
LATCH 2
D
D
Q
clk
IN
IN
Q
clk
Q
OUT
Q
OUT
TIN
IN
OUT
M.H. Perrott
Maximum speed limited only by propagation delay
(delay1, delay2) of latches and setup time of
latches (Ts)
51
Speed Limitations of Gated Divide-by-2/3 Circuit
delay1
delay3
delay2
Register
A
CON
GATING
LOGIC
LATCH 1
D
Q
clk
IN
IN
Q
LATCH 2
D
clk
Q
OUT
Q
OUT
TIN
IN
A
OUT
CON
Maximum speed limited by latch plus gating logic
Gated divide-by-2/3 fundamentally slower than divide-by-2
M.H. Perrott
52
Divide-by-2/3 Using Phase Shifting
DIVIDE-BY-2
LATCH
D
Q
clk
.A
LATCH
D
Q
Q
clk
MUX
LOGIC
.B
Q
IN
IN
OUT
OUT
CON
IN
.A
.B
OUT
CON
.B
M.H. Perrott
OUT
.A
OUT
Achieves speed of divide-by-2 circuits!
- MUX logic runs at half the input clock speed
53
Implementation Challenges to Phase Shifting
Avoiding glitches
- By assumption of sine wave characteristics
-
Craninckx et. al., “A 1.75 GHz/3 V Dual-Modulus Divideby-128/129 Prescaler …”, JSSC, July 1996
By make-before-break switching
My thesis: http://www-mtl.mit.edu/~perrott/
Through re-timed multiplexor
Krishnapura et. al, “A 5.3 GHz Programmable Divider for
HiPerLan in 0.25μm CMOS”, JSSC, July 2000
Avoiding jitter due to mismatch in phases
- Through calibration
Park et. al., “A 1.8-GHz Self-Calibrated Phase-Locked
Loop with Precise I/Q Matching”, JSSC, May 2001
M.H. Perrott
54
Further Reduction of MUX Operating Frequency
MUX
LOGIC
DIVIDE-BY-2
(4 PHASE)
DIVIDE-BY-2
IN
IN
OUT
IN
IN
OUT
IN/2
Φ1
Φ2
Φ3
Φ4
IN
IN
IN/2
4 cycles
5 cycles
Φ1
Φ2
Φ3
Φ4
OUT
OUT
OUT
OUT
CON
IN
IN/2
Φ1
Φ2
Φ3
Φ4
OUT
Φ1
M.H. Perrott
OUT
Φ2
OUT
Leverage the fact that divide-by-2 circuit has 4 phases
- Create divide-by-4/5 by cascading two divide-by-2 circuits
Note that single cycle pulse swallowing still achieved
- Mux operates at one fourth the input frequency!
55
Impact of Divide-by-4/5 in Multi-Modulus Prescaler
CON0
IN
4/5
CON1
A
2/3
CON2
B
2/3
OUT
16 + CON0 *20 + CON1*22 + CON2*23
IN
A
B
OUT
Issue – gaps are created in divide value range
- Divide-by-4/5 lowers swallowing resolution of following
stage
M.H. Perrott
56
Method to “Fill In” Divide Value Range
4/5/6/7
IN
4/5
A
2/3
B
2/3
OUT
IN
A
B
OUT
AT LEAST 3 CYCLES
NEEDED AT NODE A
M.H. Perrott
Allow divide-by-4/5 to swallow more than one input
cycle per OUT period
- Divide-by-4/5 changed to Divide-by-4/5/6/7
Note: at least two divide-by-2/3 sections must follow
57
Example Architecture for a Phase-Shifted Divider
Divide-by-2
IN
OUT
IN
OUT
Divide-by-2
Φ1
Φ2
Φ3
Φ4
IN
IN
4-to-1 MUX
Φ1
Φ2
Φ3
Φ4
OUT
IN
OUT
IN
OUT
PH_SEL
Control
Qualifier
CON CON*
QUAL
M.H. Perrott
Remaining Divider Stages
Qualification Signals
Phase Select
Logic
CON*
PH_SEL
CLK
Phase shifting in first divide-by-4/5/6/7 stage to
achieve high speed
Remaining stages correspond to gated divide-by-2/3
cells
For details, see my thesis
- http://www-mtl.mit.edu/~perrott/
58
PFD/Charge Pump
Analog Phase Comparison Path
I
0
-I
Ref
PFD
E
Charge
Pump
IIN
Loop
Filter
Vout
IIN
Div
Digital
Gain Control
I
I
0
-I
D/A
Performs measurement of Ref and Div phase difference
Sets PLL bandwidth and determines PLL stability
Key performance issues
- Note: Digital control of charge pump current allows tuning
M.H. Perrott
- Linearity, noise, power, area
60
Achieving Linear Operation of PFD/Charge Pump
Wide Pulse
Narrow Pulse
Linear
Nonlinear
Nominal
Positive
Perturbation
Negative
Perturbation
Key issue: pulses need to fully settle to avoid
nonlinearity in PFD/charge pump
- Impact of nonlinearity is noise folding/spurs
- Runt pulses cause “dead zone” in PFD characteristic
M.H. Perrott
61
Add Delay in Reset Path to Prevent Dead Zone
Up
Ref
1
Q
D
Q
R
Delay
Div
1
DRQ
Down
Q
Ref
Div
Up
2
0
2
Down
M.H. Perrott
0
Minimum pulse width set by length of delay
- Avoids incomplete settling at the expense of higher noise
62
Simple View of Charge Pump
I
Vup
IIN
Vdown
I
Current sources implemented by current mirror circuits
Key issue: hard to achieve precise matching of up and
down currents
- Variation puts switches at supply/gnd rails
M.H. Perrott
63
Practical Charge Pump Characteristic
<IIN>
2I+ε1
−2π
ε1
2π
ΔΦ
-2I+ε1-ε2
Gain slope changes due to up/down current mismatch
Offset in phase due to timing mismatch between Up
and Down PFD paths
M.H. Perrott
- Causes nonlinearity in phase comparison operation
64
Offset PFD for High Linearity
Up
Ref
1
Q
D
Output charge transfer
Q
R
Delay
Div
1
DRQ
Down
Q
Phase
Variation
Ref
Phase error
Div
2
Up
0
2
Down
0
Change delay path such that Up pulse is always constant
and follows Down pulse
- Only Down pulse varies in width
Confines phase variation to one side of PFD characteristic
M.H. Perrott
65
Single-Ended Versus Differential Charge Pumps
Single-Ended
Differential
IIN
Large ΔV
Results
Cp
I
Cp
I
ΔV Reduced
Stray capacitance causes increased transient times for
charge pump
- Increases the minimum required on-time of PFD pulses
Differential structure substantially reduces impact of
stray capacitance
- Reduces voltage variation on cap due to switching action
M.H. Perrott
66
Example Differential Charge Pump Structure
2I
2I
IIN
IIN
Vup
Vup
2I
M.H. Perrott
Vdown
Vdown
2I
Zero output current is achieved by canceling Up and
Down currents
In practice, this structure is rarely used due to high
noise it produces
67
Loop Filter Design
Outline
Closed-Loop Design of Frequency Synthesizers
- Introduction
- Background on Classical Open Loop Design Approach
- Closed Loop Design Approach
- Example and Verification
- Conclusion
M.H. Perrott
69
Σ−Δ Fractional-N Frequency Synthesizer
Focus on this architecture since it is essentially a
“super set” of other synthesizers, including integer-N
and fractional-N
- If we can design and simulate this structure, we can also
do so for classical integer-N designs
ref(t)
PFD
e(t) Charge
Pump
Loop
Filter
out(t)
v(t)
VCO
div(t)
Nsd[m]
M.H. Perrott
Divider
Σ−Δ
Modulator
N[m]
70
Frequency-domain Model
PFD
Φref [k]
Tristate: α=1
XOR: α =2
α
T
C.P.
e(t)
2π
Loop
Filter
Icp
H(f)
VCO
v(t)
KV
Φout(t)
jf
Divider
Φdiv[k]
1
1
T
Nnom
Φd [k]
n[k]
-1
z
2π
1 - z-1
j2πfT
z=e
See Perrott et. al. JSSC,
Aug. 2002 for details
M.H. Perrott
Closed loop dynamics parameterized by
71
Review of Classical Design Approach
Given the desired closed-loop bandwidth, order, and
system type:
1. Choose an appropriate topology for H(f)
Depends on order, type
2. Choose pole/zero values for H(f) as appropriate for the
required bandwidth
3. Adjust the open-loop gain to achieve the required
bandwidth while maintaining stability
Plot gain and phase bode plots of A(f)
Use phase (or gain) margin criterion to infer
stability
M.H. Perrott
72
Example: First Order, Type I with Parasitic Poles
Evaluation of
Phase Margin
Closed Loop Pole
Locations of G(f)
Im(s)
20log|A(f)|
Open loop
gain
increased
C
Dominant
pole pair
0 dB
f
fp fp2fp3
B
Non-dominant
poles
\A(f)
-90
C
B
A
Re(s)
A
o
o
0
A
PM = 72 for A
PM = 51o for B
B
o
-165
o
-180
-240
o
-315
o
M.H. Perrott
PM = -12o for C
C
73
First Order, Type I: Frequency and Step Responses
Closed Loop Step Response
Closed Loop Frequency Response
C
C
2
0 dB
B
B
A
1
A
0
Frequency
M.H. Perrott
Time
74
Limitations of Open Loop Design Approach
Constrained for applications which require precise
filter response
Complicated once parasitic poles are taken into
account
Poor control over filter shape
Inadequate for systems with third order rolloff
- Phase margin criterion based on second order systems
Closed loop design approach:
Directly design G(f) by specifying dominant pole and
zero locations on the s-plane (pole-zero diagram)
M.H. Perrott
75
Closed Loop Design Approach: Overview
G(f) completely describes the closed loop dynamics
- Design of this function is the ultimate goal
Performance
Specifications
{type, fo, ...}
Open Loop
Design
Approach
G(f) =
|A(f)|
\A(f)
{K, fzA, fpA, ...}
A(f)) =
A(f)
1+A(f)
G(f)
G(f)
{fz , fp , ...}
1-G(f)
1-
Closed Loop Design Approach
M.H. Perrott
Instead of indirectly designing G(f) using plots of A(f), solve
for G(f) directly as a function of specification parameters
Solve for A(f) that will achieve desired G(f)
Account for the impact of parasitic poles/zeros
76
Closed Loop Design Approach: Implementation
Download PLL Design Assistant Software
Read accompanying manual
Algorithm described by C.Y. Lau et. al. in “Fractional-N
Frequency Synthesizer Design at the Transfer Function
Level Using a Direct Closed Loop Realization
Algorithm”, Design Automation Conference, 2003
- Part of CppSim package at http://www.cppsim.com
M.H. Perrott
77
Definition of Bandwidth, Order, and Shape for G(f)
0
G(f)
(dB)
Bandwidth – fo
Order – n
Shape
fo
f
rolloff =
-20n
dB/decade
- Defined in asymptotic manner as shown
- Defined according to the rolloff characteristic of G(f)
- Defined according to standard filter design
methodologies
Butterworth, Bessel, Chebyshev, etc.
M.H. Perrott
78
Definition of Type
Type I: one integrator in PLL open loop transfer
function
- VCO adds on integrator
- Loop filter, H(f), has no integrators
Type II: two integrators in PLL open loop transfer
function
- Loop filter, H(f), has one integrator
Tristate: α=1
PFD XOR-based: α=2
Φref(t)
Φdiv(t)
M.H. Perrott
α
2π
Loop Filter
e(t)
VCO
v(t)
H(f)
Kv
jf
Φout(t)
Divider
1
N
79
Loop Filter Transfer Function Vs Type and Order of G(f)
H(s) Topology For Different Type and Orders of G(f)
Type I
Order 1
Order 2
Order 3
Type II
KLP
KLP
KLP
KLP
1+s/wp
1+s/wz
s(1+s/wp)
KLP(1+s/wz)
KLP
1+s/(wpQp)+(s/wp)
1+s/wz
s
2
where KLP = K
s(1+s/(wpQp)+(s/wp)2)
Nnom
KvIcpα
Calculated from software
Practical PLL implementations limited to above
Open loop gain, K, will be calculated by algorithm
- Prohibitive analog complexity for higher order, type
M.H. Perrott
- Loop filter gain related to open loop gain as shown above
80
Passive Topologies to Realize a Second Order PLL
Type I, Order 2
Type II, Order 2
Idac
DAC
Vout
Iin
C1
Vout
Iin
Vout
Iin
=
C1
R1
C2
R1
R1
Vout
1+sR1C1
Iin
=
1
1+sR1C2
s(C1+C2) 1+sR1C||
DAC is used for Type I implementation to coarsely
tune VCO
- Allows full range of VCO to be achieved
M.H. Perrott
81
Passive Topologies to Realize a Third Order PLL
Type I, Order 3
Type II, Order 3
Idac
DAC
Iin
L1
Iin
C1
Vout
Iin
L1
=
Vout
C1
Vout
R1
C2
R1
R1
Vout
2
1+sR1C1+s L1C1
Iin
=
1
1+sR1C2
s(C1+C2) 1+sR1C||+s2L1C||
where C||= C1C2/(C1+C2)
M.H. Perrott
Inductor is necessary to create a complex pole pair
- Must be implemented off-chip due to its large value
82
Problem with Passive Loop Filter Implementations
Large voltage swing required at charge pump output
Non-ideal behavior of inductors (for third order G(f)
implementations)
- Must support full range of VCO input
- Hard to realize large inductor values
- Self resonance of inductor reduces high frequency
attenuation
Cp
L1
L1
Alternative: active loop filter implementation
M.H. Perrott
83
Guidelines for Active Loop Filter Design
Use topologies with unity
gain feedback in the
opamp
- Minimizes influence of
opamp noise
R1
Perform level shifting in
feedback of opamp
- Fixes voltage at charge
pump output
Use current
to achieve
level shift
R2
Level
Shift
Element
2
Vnoise,in
Vout
Set nominal
voltage to Vref
Vout
Vref
Prevent fast edges from directly reaching opamp inputs
- Will otherwise cause opamp to be driven into nonlinear
region of operation
M.H. Perrott
84
Active Topologies To Realize a Second Order PLL
Type I, Order 2
Idac
Type II, Order 2
C2
R2
Iin
DAC
C3
Vref
Vout
Iin
Iin
C1
R1
R1
C1
Vref
Vref
Vout
Iin
=
Vout
R1
Vout
1+sR1C1
Iin
=
1+sR1(C1+C2+C3)
sC2(1+sR1C1)
Follows guidelines from previous slide
Charge pump output is terminated directly with a high
Q capacitor
- Smooths fast edges from charge pump before they
reach the opamp input(s)
M.H. Perrott
85
Active Topologies To Realize a Third Order PLL
Type I, Order 3
Type II, Order 3
C2
C2
R1
R2
R1
C3
R2
Idac
DAC
C1
Iin
C1
Iin
Vout
Vout
Vref
Vout
Iin
=
Vref
Vout
-R2
2
1+s(R1+R2)C2+s R1R2C1C2
Iin
=
-1
1+sR2C3
s(C1+C2) 1+sC||(R1(1+C1/C3)+R2)+s2R1R2C1C||
where C||= C2C3/(C2+C3)
M.H. Perrott
Follows active implementation guidelines from a few
slides ago
86
Example Design
Type II, 3rd order, Butterworth, fo = 300kHz, fz/fo = 0.125
Required loop filter transfer function can be found from
table:
M.H. Perrott
- No parasitic poles
87
Use PLL Design Assistant to Calculate Parameters
M.H. Perrott
88
Resulting Step Response and Pole/Zero Diagram
M.H. Perrott
89
Impact of Open Loop Parameter Variations
Open loop parameter variations can be directly entered
into tool
M.H. Perrott
90
Resulting Step Responses and Pole/Zero Diagrams
M.H. Perrott
Impact of variations on the loop dynamics can be
visualized instantly and taken into account at early
stage of design
91
Design with Parasitic Pole
Include a parasitic pole at nominal value fp1 = 1.2MHz
Ö K, fp and
Qp are adjusted to obtain the same dominant
pole locations
M.H. Perrott
92
Noise Estimation
M.H. Perrott
Phase noise plots can be easily obtained
Jitter calculated by integrating over frequency
range
-
93
Calculated Versus Simulated Phase Noise Spectrum
Without parasitic pole:
60
Output Phase Noise of Synthesizer
SD Noise
Detector Noise
VCO Noise
Total Noise
Simulated Noise
80
100
120
100
120
140
140
160
160
180 4
10
105
106
Frequency Offset (Hz)
107
Simulated Phase Noise of SD Freq. Synth.
80
L(f) (dBc/Hz)
L(f) (dBc/Hz)
60
108
180 4
10
105
106
107
108
Frequency Offset (Hz)
RMS jitter = 13.791ps
M.H. Perrott
94
Calculated Versus Simulated Phase Noise Spectrum
With parasitic pole at 1.2 MHz:
60
Output Phase Noise of Synthesizer
SD Noise
Detector Noise
VCO Noise
Total Noise
Simulated Noise
80
100
120
100
120
140
140
160
160
180
104
105
106
Frequency Offset (Hz)
107
Simulated Phase Noise of SD Freq. Synth.
80
L(f) (dBc/Hz)
L(f) (dBc/Hz)
60
108
180 4
10
105
106
107
108
Frequency Offset from Carrier (Hz)
RMS jitter = 14.057ps
M.H. Perrott
95
Noise under Open Loop Parameter Variations
60
Output Phase Noise of Synthesizer
SD Noise
Detector Noise
VCO Noise
Total Noise
L(f) (dBc/Hz)
80
100
120
140
160
180 4
10
105
106
107
108
Frequency Offset (Hz)
RMS jitter = 11.678ps (min), 18.211ps (max)
M.H. Perrott
Impact of open loop parameter variations on phase
noise and jitter can be visualized immediately
96
Conclusion
CAD-based closed loop design approach facilitates:
Techniques implemented in a GUI-based CAD tool
Beginners can quickly come up to speed in designing
PLL’s
Experienced designers can quickly evaluate the
performance of different PLL configurations
M.H. Perrott
- Accurate control of closed loop dynamics
Bandwidth, Order, Shape, Type
- Straightforward design of higher order PLL’s
- Direct assessment of impact of parasitic poles/zeros
97
