Very Large Scale Integration
(VLSI)
Lecture 1
Dr. Ahmed H. Madian
Ah_madian@hotmail.com
Dr. Ahmed H. Madian-VLSI
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Course Objective
You’ll get a bottom-up tour of how integrated circuits are engineered.
We’ll talk about
 MOSFETs: how they work, how they’re built, effects of new
technologies
 Various design and layout techniques, from the ordinary to the
most complex, for creating combinational and sequential circuits,
datapaths, memories, buffers, regular logic structures, …etc.
 how you tackle the problem of designing circuits with 1,000,000
gates -- you’re not in Digital IC Technique anymore!
 Give different testing techniques for VLSI circuits.
Dr. Ahmed H. Madian-VLSI
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Administrative Rules
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Course schedule:
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Lectures:
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Saturday (3rd slot), 12:30 - 13:45
Tuesday (4th slot), 14:15- 15:45
Office hours: Saturday 14:30 - 16:30 (C3.221)
Teaching assistant: Eng. Mona Guindy
Grading
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Quizzes & Assignments: 20%
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Assignment of every lecture is due the following lecture
Final exam: 80%
Dr. Ahmed H. Madian-VLSI
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References
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Anantha Chandrakasan, William J. Bowhill, Frank Fox,
“Deign of high performance microprocessor circuits”
John P. Uyemura, “Introduction to VLSI circuits and
systems”
Or any VLSI references
Dr. Ahmed H. Madian-VLSI
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Course outline
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Overview of VLSI
Technologies for Micro- and Nanostructures
Low-Voltage and power design
Synchronous and Asynchronous Circuit Design
Architectures for VLSI Applications
Test and Measurement Techniques for VLSI
Circuits
Dr. Ahmed H. Madian-VLSI
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What is VLSI?
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VLSI stands for (Very Large Scale Integrated
circuits)
Craver Mead of Caltech pioneered the filed of VLSI
in the 1970’s.
Digital electronic integrated circuits could be
viewed as a set of geometrical patterns on the
surface of a silicon chip.
Complexity could thus be dealt with using the
concept of repeated patterns that were fitted
together in structured manner.
Dr. Ahmed H. Madian-VLSI
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VLSI History
•Jack Kilby, working at Texas Instruments, first dreamed up the idea of a
monolithic “integrated circuit” in July 1959. By the end of the year, he had
constructed several examples, including the flip-flop shown in the patent
drawing above. Components are connected by hand-soldered wires and
isolated by “shaping” and pn diodes used as resistors.
Dr. Ahmed H. Madian-VLSI
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VLSI History (cont.)


1961: TI and Fairchild introduced the first logic IC’s (cost
~$50 in quantity!). This is a dual flip-flop with 4 transistors.
1963: Densities and yields are improving. This circuit has
four flip flops.
In 1970, making good on its promise to its
investors Intel starts selling a 1K bit RAM,
the 1103.
Dr. Ahmed H. Madian-VLSI
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VLSI History (cont.)

Introduced in 1972, the 8008 had 3,500
transistors supporting a byte-wide data
path. Despite its limitations, the 8008
was the first microprocessor capable of
playing the role of computer CPU as
demonstrated on the cover of the July
‘74 issue of Radio-Electronics.
Dr. Ahmed H. Madian-VLSI
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Today
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Many disciplines have
contributed to the current
VLSI designs:
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solid-state physics
materials science
lithography and fab
device modeling
architecture
algorithms
CAD tools
circuit design & layout
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Chip Complexity
Chip classification according to number of active elements and minimal feature size:
Dr. Ahmed H. Madian-VLSI
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VLSI Chip Types
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Full custom
Every circuit is custom designed
Application-specific integrated circuits
(ASICS) Design is created using a
standard CAD tools without the need to
interact with the silicon structure
Semi-custom
In between of full-custom and ASIC-type
circuits. The majority of the chip is designed
using a primitive predefined cells (standard
cells) from library as building blocks.
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Top design level
Design
hierarchy
overview
bottom design level
System specifications
Initial concept
Abstract High-level model
VHDL, Verilog, HDL
System design
and verification
Logic synthesis
Logic design
and verification
Circuit design
CMOS design
and verification
physical design
Manufacturing
Finished
VLSI
chip
Dr. Ahmed H.
Madian-VLSI
Silicon logic design
and verification
Mass production,
testing and
packaging
Marketing
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Top design level
VLSI
Design
bottom design level
System specifications
Initial concept
Abstract High-level model
VHDL, Verilog, HDL
System design
and verification
Logic synthesis
Logic design
and verification
Circuit design
CMOS design
and verification
physical design
Manufacturing
Finished
VLSI
chip
Dr. Ahmed H.
Madian-VLSI
Silicon logic design
and verification
Mass production,
testing and
packaging
Marketing
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VLSI Challenges
The Moore’s Law (Moore is one of the co-founder of Intel corp.)
has been fundamental to the silicon industry, obeyed for the past
30 years; however, technology scaling will become difficult
beyond 0.18 micron, threatening Moore’s Law.
Dr. Ahmed H. Madian-VLSI
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Scaled-down Transistors
The principle of constant-filed
scaling lies in scaling the device
voltages and the device dimensions
(both horizontal and vertical) by the
same factor , k (>1) , such that the
electric filed remains unchanged.
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VLSI Challenges (cont.)
Design Challenges of Technology
Scaling
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Technology models 0.5µm, 0.35µm, 0.25µm,
0.18µm, 0.13µm, 90nm, 65nm, 45nm, 32nm,
20nm, ???.
Scaling factor of 0.7 in the dimension exist from
generation to the next one.
Scaling in Area = 0.7 X 0.7 = 0.490.5. This means
the transistor density doubles every generation.
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Challenges of VLSI (cont.)
Every Two years:
1. Capacitance per node reduces by 30% (usual scaling)
2. Electrical nodes in a given area increase by 2X
3. Die size grows by 14% every two years (Moore’s Law)
4. Supply voltage reduces by 15% every two years
5. And frequency increases by 2X.

This all adds up to 2.7X increase in active power of the
lead microprocessor every two years.
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Revision on MOSFET
Fabrication procedure
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Building MOSFET

bulk CMOS with a p-type substrate:
slice of a silicon ingot that has been
doped with an acceptor (typically
boron) to increase the concentration of
holes
P-type
Back is metallized to provide
a good ground connection.
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Building MOSFET (cont.)
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Next, a “thick” layer of silicon dioxide, called field oxide,
is formed on the surface by oxidation in wet oxygen.
This is then etched to expose surface where we want to
make a MOSFET:
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Building MOSFET (cont.)
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Now grow a “thin” layer of silicon dioxide, called
gate oxide, on the surface by exposing the wafer
to dry oxygen.
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Building MOSFET (cont.)
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On top of the thin oxide a thick layer of polycrystalline silicon,
called polysilicon or poly for short, is deposited by CVD. The
poly layer is patterned and plasma etched exposing the
surface where the source and drain junctions will be formed
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Building MOSFET (cont.)

The entire surface is doped, either by diffusion or ion
implantation, with phosphorus (an electron donor) which
creates two n-type regions in the substrate. The phosphorus
also penetrates the poly reducing its resistance and affecting
the nfet’s threshold.
n+
n+
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Building MOSFET (cont.)
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Finally an intermediate oxide layer is grown and
then reflowed to flatten its surface. Holes are
etched in the oxide (where contacts to poly/diff
are wanted) and aluminum deposited, patterned
and etched.
n+
n+
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Threshold voltage

The gate voltage required to form the channel is called the
threshold voltage. Many factors affect the gate-source voltage at
which the channel becomes conductive. Threshold voltage for
source-bulk voltage zero:
VTo   GC
Qb Qox
 2 F 

Cox Cox
As Vsb increases, the depth of the depletion region increases, exposing more
of the fixed acceptor (i.e. negative) ions in the substrate.
VT  Vtno  

VsB  2F  2F

2 si qN A
where  
Cox
Where F is the Fermi potential, Qb is the depletion region charge,

is the
substrate coefficient and VSB is the substrate bias voltage
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Channel-Length modulation
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SPICE Models
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There are different models used in circuit
simulators:
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level 1 is our simple model including the most
important second order effects described
level 2 model is based on device physics
level 3 is a semi-empirical model allowing to
match equations to the real circuit: example
BSIM model from Berkeley models
subthreshold characteristics.
Dr. Ahmed H. Madian-VLSI
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Physical design
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CMOS ICs are electronic switching
networks that are created on small area of
silicon wafer using complex set of physical
and chemical processes.
A primary task for VLSI designer is to
translate circuit schematics into silicon
form (this process is called physical design)
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Integrated Circuit Layers

ICs are made by
stacking different layers
of materials in a specific
order to form three
dimensional structures
that act as an electronic
switching network.
Layer M1
Substrate
Side view
Dr. Ahmed H. Madian-VLSI
Insulator
Substrate
M1
M1
Top view
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Integrated Circuit Layers (cont.)
Layer M2
Layer M1
insulator
Substrate
Layer M1
Layer M2
Side view
Top view
Dr. Ahmed H. Madian-VLSI
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Designing NFET Arrays layout
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Devices can share
patterned regions,
which may reduce
the layout area or
complexity
B
A
n+
n+
n+
n+
C
n+
n+
A
Dr. Ahmed H. Madian-VLSI
n+ n+
n+
B
n+
C
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Designing PFET Arrays layout

Devices can share
patterned regions,
which may reduce
the layout area or
complexity
B
A
p+
p+
p+
C
p+
p+ p+
N-well
p+
p+
A
Dr. Ahmed H. Madian-VLSI
p+
B
p+
C
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Design Examples VLSI
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Draw the CMOS realization and the
layout of NAND and NOR gates
Colors of layers
polysilicon (gates)
: Red
Doped n+/p+ (active) : Green
N-Well
: Yellow
Metal 1
: BLUE
Metal 2
: Grey
Contacts
: Black X’s
Dr. Ahmed H. Madian-VLSI
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CMOS Realization
VDD
VDD
a
F  a.b
b
a
F  ab
NAND gate CMOS realization
b
NOR gate CMOS realization
Dr. Ahmed H. Madian-VLSI
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NAND FET Layout
VDD
N-WELL
PFET
P+ Gate
P+
Gate P+
a
b
NFET
N+ Gate
N+
Gate N+
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NAND FET Layout (cont.)
VDD
VDD
PFET
X
X
a
b
NFET
X
GND
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NAND FET Layout (cont.)
VDD
VDD
PFET
X
a
X
X
b
OUT
NFET
X
X
a
b
GND
Dr. Ahmed H. Madian-VLSI
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NOR FET layout
VDD
VDD
PFET
X
X
OUT
a
b
NFET
X
X
X
a
b
GND
Dr. Ahmed H. Madian-VLSI
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Design Examples VLSI
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Draw the pass transistor realization
and the layout of MUX 4:1
Colors of layers
polysilicon (gates)
: Red
Doped n+/p+ (active) : Green
N-Well
: Yellow
Metal 1
: BLUE
Metal 2
: Grey
Contacts
: Black X’s
Dr. Ahmed H. Madian-VLSI
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CMOS realization of MUX 4:1
S1
S1
S0
S0
P0
P0
P1
MUX
4:1
P2
F
P1
F
P3
S0
S1
P2
P3
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MUX layout
S1
P0
X
P1
X
P2 X
S1
S0
X
S0
X
X
S1
S0
S0
P0
X
X
X
X
S1
F
P1
F
X
P2
X
P3
X
P3
X
Dr. Ahmed H. Madian-VLSI
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Design Examples VLSI

Draw the CMOS realization and the layout of
logic function
f  a  b. c

Colors of layers
polysilicon (gates)
: Red
Doped n+/p+ (active) : Green
N-Well
: Yellow
Metal 1
: BLUE
Metal 2
: Grey
Contacts
: Black X’s
Dr. Ahmed H. Madian-VLSI
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CMOS Realization
VDD
b
c
a
f
b
a
c
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Logic function Layout
VDD
N-Well
b
PFET
c
P+
a
f
b
a
NFET
N+
c
Dr. Ahmed H. Madian-VLSI
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Logic function Layout
VDD
VDD
N-Well
c
PFET
X
b
X
b
a
c
X
a
f
b
a
NFET
c
Dr. Ahmed H. Madian-VLSI
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Logic function Layout
VDD
VDD
N-Well
b
c
PFET
X
X
b
a
X
c
X
a
f
b
f
a
NFET
X
X
X
c
GND
Dr. Ahmed H. Madian-VLSI
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Layout Rules
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Layout rules are the common language between design and
process engineers
conservative rules absorb process disturbances and variations
layout rules must be respected by the designer
layout rules reflect the limits of a process, they describe:
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minimal distance, overlap
minimal width (e.x. channel length, λ)
layout readability is improved using colors:
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metal
polysilicium
n-diffusion
p-diffusion
n-well
contact, via
blue
red
green
yellow
brown
black
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Layout
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Stick Diagram
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stick diagrams are
technology independent
no layout rules need to
be known
mask layout may be
generated automatically
Dr. Ahmed H. Madian-VLSI
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Digital Layout: horizontal or vertical
gates?
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Vertical gates
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Good for circuits where fets
sizes are similar and each
gate has limited fanout. Best
choice for multiple input static
gates and for datapaths.
Horizontal gates
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Good for circuits where long and short
fets are needed or where nodes must
control many fets. Often used in
multiple-output complex gates (e.g,
sum/carry circuits).
Dr. Ahmed H. Madian-VLSI
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Eliminating Gaps
Dr. Ahmed H. Madian-VLSI
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Complex CMOS Gates compact
layout.
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Euler Rule:
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Generate an n-graph by replacing the nfet block
with vertices for nodes and edges for fets
Generate a dual p-graph
Find a sequence containing all edges in the ngraph. This sequence is called Euler n-path.
Generate an Euler p-path with the same labeling
as the Euler n-path. If not possible start again.
The labeling sequence of the 2 Euler paths are the
gate sequence of the single row nfet/pfet CMOS
gate.
Dr. Ahmed H. Madian-VLSI
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Example

Draw the most compact layout for the
following logic function using Euler’s rule.
F= A.(B+C)
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Solution
VDD
F
A
C
N1
A
B
F
A
N2
C
N2
VDD
C
N1
B
F
B
GND
GND
Dr. Ahmed H. Madian-VLSI
A  B  C
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Layout of Example
A  B  C
A
B
C
Dr. Ahmed H. Madian-VLSI
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Thanks
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Revision sheet will be soon available on
the web site
you must solve it
Download one of the layout tools and
practice on the lecture examples
Dr. Ahmed H. Madian-VLSI
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