MOS Capacitance
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EE141-Fall 2010 Digital Integrated Circuits MOS Capacitance Lecture 11 MOS Capacitance and Delay EE141 EECS141 Lecture #11 1 1 Announcements No EE141 EECS141 4 MOS Capacitances G lab Fri., Mon. Labs restart next week Midterm 4 Lecture #11 CGS CGD = CGCS + CGSO #1 Thurs. Oct. 7th, 6:30-8:00pm = CGCD + CGDO S Exam is open notes, book, calculators, etc. D CGB CSB = Cdiff = CGCB CDB = Cdiff B EE141 EECS141 Lecture #11 2 2 Class Material Last EE141 EECS141 Lecture #11 5 5 Gate Capacitance lecture Using the MOS model: Inverter VTC Today’s lecture MOS Capacitance Using the MOS Model: Delay Reading EE141 EECS141 Capacitance (per area) from gate across the oxide is W·L·Cox, where Cox=εox/tox (3.3.2, 5.4.2) Lecture #11 3 3 EE141 EECS141 Lecture #11 6 6 Gate Capacitance Transistor in Linear Region G S D W L C OL C jSB Distribution between terminals is complex Capacitance is really distributed Several operating regions: – Way off, off, transistor linear, transistor saturated 7 Lecture #11 7 Transistor In Cutoff Channel is formed and acts as the other terminal Model by splitting oxide cap equally between source and drain – Changing either voltage changes the channel charge EE141 EECS141 G S L C OL xj C jDB – Substrate acts as the other capacitor terminal – Capacitance becomes series combination of gate oxide and depletion capacitance 8 Lecture #11 Changing source voltage doesn’t change VGC uniformly EE141 EECS141 Transistor in Saturation Region (cont’ (cont’d) G S D W L C OL C OL xj C jDB 9 9 C OL xj C jDB LD Drain voltage no longer affects channel charge – Set by source and VDS_sat – Usually just approximate with CGCB = 0 in this region. (If VGS is “very” negative (for NMOS), depletion region shrinks and CGCB goes back to ~W·L·Cox) CG C JC C jSB When |VGS| < |VT|, total CGCB much smaller than W·L·Cox Lecture #11 11 11 Lecture #11 L EE141 EECS141 C jDB LD D W C jSB xj Bottom line: CGCS ≈ 2/3·W·L·Cox 8 G C GB C OL – E.g. VGC at pinch off point still VTH Transistor In Cutoff (cont’ (cont’d) C OL CG C JC C jSB When the transistor is off, no carriers in channel to form the other side of the capacitor. S D W L C OL C jSB EE141 EECS141 10 10 Lecture #11 D C GB C jDB Transistor in Saturation Region W C OL xj LD G S C OL – CGCB drops to zero (shielded by channel) – Useful models lump it to the terminals EE141 EECS141 CG C JC If change in charge is 0, CGCD = 0 EE141 EECS141 Lecture #11 12 12 Diffusion Capacitance Gate Capacitance NA+ Bottom Side wall – Area cap – Cbottom = Cj·LS·W Source W ND Bottom Sidewalls xj Side wall – Perimeter cap – Csw = Cjsw·(2LS+W) Cgate vs. VGS (with VDS = 0) Cgate vs. operating region Channel Substrate LS NA GateEdge – Cge = Cjgate·W – Usually automatically included in the SPICE model EE141 EECS141 13 13 Lecture #11 Gate Overlap Capacitance 1.0 Source tox Drain xd n+ W Gate-bulk overlap Ld L n+ n+ Top view Junction caps are nonlinear – CJ is a function of junction bias Cross section 0.9 Capacitance [arbitrary units] Gate oxide xd 16 16 Lecture #11 Junction Capacitance (2) Polysilicon gate n+ EE141 EECS141 0.8 0.7 0.6 N+ junction area N+ junction perimeter P+ junction area P+ junction perimeter 0.5 SPICE model equations: CO = Cox ⋅ xd 0.4 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 Node voltage (V) )mj – Area CJ = area × CJ0 / (1+ |VDB|/φΒ – Perimeter CJ = perim × CJSW / (1 + |VDB|/φΒ)mjsw – Gate edge CJ = W × CJgate / (1 + |VDB|/φΒ)mjswg Off/Lin/Sat Æ CGSO = CGDO = CO·W How do we deal with nonlinear capacitance? EE141 EECS141 14 14 Lecture #11 Gate Fringe Capacitance Lecture #11 17 17 Linearizing the Junction Capacitance Fringing fields n+ EE141 EECS141 Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest n+ Cross section COV not just from metallurgic overlap – get fringing fields too Typical value: ~0.2fF·W(in µm)/edge EE141 EECS141 Lecture #11 15 15 EE141 EECS141 Lecture #11 18 18 1.8 Capacitance Model Summary Model Calibration - Capacitance Gate-Channel Capacitance CGC ≈ 0 CGC = Cox·W·Leff (|VGS| < |VT|) (Linear) Can calculate Cg, Cd based on tech. parameters CGC = (2/3)·Cox·W·Leff (Saturation) Another approach: – But these models are simplified too – 50% G to S, 50% G to D – Tune (e.g., in spice) the linear capacitance until it makes the simplified circuit match the real circuit – Matching could be for delay, power, etc. – 100% G to S Gate Overlap Capacitance CGSO = CGDO = CO·W (Always) Cload Junction/Diffusion Capacitance Cdiff = Cj·LS·W + Cjsw·(2LS + W) + CjgW EE141 EECS141 Delay1 Delay2 Match (Always) 19 19 Lecture #11 Capacitances in 0.25 µm CMOS Process EE141 EECS141 22 22 Lecture #11 Model Calibration for Delay A Cload Delay1 Delay2 Match For gate capacitance: – Make inverter fanout 4 – Adjust Cload until Delay1 = Delay2 For diffusion capacitance – Replace inverter “A” with a diffusion capacitance load EE141 EECS141 20 20 Lecture #11 Simplified Model EE141 EECS141 23 23 Lecture #11 Delay Calibration Capacitance models important for analysis and intuition 1 4 16 64 Load ??? – But often need something simpler to work with Simple switch model: Delay – Lump together as effective linear capacitance to (ac) ground – In most processes: CG = CD = 1.5 – 2fF·W(µm) Vin Vout Vin "Edge Shaper" Why did we need that last inverter stage? Vout CL EE141 EECS141 Lecture #11 21 21 EE141 EECS141 Lecture #11 24 24 The Miller Effect MOS Transistor as a Switch As Vin increases, Vout drops – Once get into the transition region, gain from Vin to Vout > 1 Cgd1 ∆V that real transistors aren’t exactly resistors ∆V Vin So, Cgd experiences voltage swing larger than Vin Saw Vout Look more like current sources in saturation M1 – Which means you need to provide more charge – Makes Cgd look larger than it really is Two Known as the “Miller Effect” in the analog world EE141 EECS141 questions: Which region of IV curve determines delay? How can that match up with the RC model? 25 25 Lecture #11 EE141 EECS141 28 28 Lecture #11 Transistor Driving a Capacitor • With a step input: VGS = VDD ID VDD Æ VDD/2 CMOS Switching Delay VDS VVSAT VDD /2 VDD • Transistor is in (velocity) saturation during entire transition from VDD to VDD/2 EE141 EECS141 26 26 Lecture #11 MOS Transistor as a Switch • In saturation, transistor basically acts like a current source: VOUT VOUT VDD i D = i D (v DS ) iD = C dVDS dt IDSAT C VDD/2 • We modeled this with: t tp R VOUT = VDD - (IDSAT/C)t tp = ln (2) RC C EE141 EECS141 29 29 Lecture #11 Switching Delay • Discharging a capacitor C EE141 EECS141 Lecture #11 27 27 EE141 EECS141 tp = C(VDD/2)/IDSAT Lecture #11 30 30 Switching Delay (with Output Conductance) The Book’s Method • Including output conductance: VOUT IDSAT C 1/(λIDSAT) VOUT = (VDD + λ −1 ) e • For “small” λ: tp ≈ -t ( C λI DSAT ) - λ −1 C (VDD 2 ) (1 + λVDD ) I DSAT EE141 EECS141 31 31 Lecture #11 RC Model EE141 EECS141 34 34 Lecture #11 The Transistor as a Switch • Transistor current not linear on VOUT – how is the RC model going to work? 7 x 10 5 6 • Look at waveforms: 2.5 5 • Voltage looks like a ramp for RC too (Ohm) 2.3 2.1 V 1.3 1 RC 1.1 0 0.5 0.9 1 1.5 V 0.2 0.4 0.6 0.8 t/τ EE141 EECS141 3 2 1.5 0 4 eq NMOS 1.7 R OUT 1.9 32 32 Lecture #11 DD 2 2.5 (V) 1 Finding Req EE141 EECS141 Lecture #11 35 35 The Transistor as a Switch • Match the delay of the RC model with the actual delay: tp = t p , RC C (VDD 2 ) = ln ( 2 ) Req C (1 + λVDD ) I DSAT • Often just: Req ≈ Req = (VDD 2 ) ln ( 2 )(1 + λVDD ) I DSAT 1 VDD 2 ⋅ ln ( 2 ) I DSAT • Note that the book uses a different method and gets 0.75·VDD/IDSAT instead of ~0.72·VDD/IDSAT. • Why did we do it this way vs. the book’s method? EE141 EECS141 Lecture #11 33 33 EE141 EECS141 Lecture #11 36 36
