Half-Bridge Drivers
A Transformer or an All-Silicon Drive?
Agenda
•
Topologies using a half-bridge configuration
•
The difference between soft and hard-switching
•
The gate-drive transformer
•
The all-silicon-solution
•
Comparison
•
Conclusions
Agenda
•
Topologies using a half-bridge configuration
•
The difference between soft and hard-switching
•
The gate-drive transformer
•
The all-silicon-solution
•
Comparison
•
Conclusions
Topology Trend for High Efficiency
•
•
Hard Switching
–
–
–
–
–
–
–
–
–
–
Flyback
Forward
2-sw flyback
2-sw forward
Full bridge
Active clamp
Forward
LLC-HB
Soft Switching
Active clamp
Flyback
LLC-HB resonant
Active clamp forward
Active clamp flyback
Asymmetrical half-bridge
Full bridge with phase shift
AHB
FB Phase-shift
The High-Side Switch
• To achieve high efficiency, the topologies with ZVS (ZeroVoltage Switching) behavior are preferred.
• All the soft switching topologies implement the power switch
with floating reference pin, e.g. the source pin of MOSFET.
• Why are MOSFETs used in soft switching applications?
– High frequency operation
– Body diode (current loop for ZVS)
How to drive the high side MOSFET?
Agenda
•
Topologies using a half-bridge configuration
•
The difference between soft and hard-switching
•
The gate-drive transformer
•
The all-silicon-solution
•
Comparison
•
Conclusions
Turn-on Procedure for Hard-switching
The Miller plateau
VGS
ID
VDRV
VGS,Miller
VTH
D
CGD
RHI
RGATE
RG,I
CDS
G
IG
IG
CGS
VDS
S
The miller plateau is caused by CGD
ID
S1 S2
•
•
S3
S4
Stages 2 and 3 dominate the switching losses of MOSFET and driver.
DRV’s source capability as VGS is around VGS,Miller is important.
Turn-off Procedure for Hard-switching
The Miller plateau
ID
VGS,Miller
VGS
VTH
D
VDRV
CGD
RLO
RGATE
RG,I
CDS
G
IG
IG
CGS
S
The miller plateau is caused by CGD
VDS
ID
S1
•
•
S2 S3 S4
Stages 2 and 3 dominate the switching losses of MOSFET and driver.
DRV’s sink capability as VGS is around VGS,Miller is important.
Simulation Circuit of Flyback
Iout
Rp
300m
Δ
2
Vclipp
Cclamp
1.4nF
R11
3.9k
D3
MUR160
Aux
18
R9
300m
10
C6
47pF
1
Isnub
Resr
100m
16
C2
440uF
21
C5
10uF
Ll
0.1uH
17
Vin
250
Vout
D1
1N4148
Lp
1.75mH
Ip
Iclipp
Out
7
Rclamp
88k
22
X1
MBRS340t3
RATIO_POW = -0.0667
RATIO_AUX = -0.0667
Out
5
Ipri
Verr
Rupper
4.851k
V1
C7
470pF
Aux
Vdrain
6
12
11
R17
20k
X2
PWMCM
C4
3.97nF
FB
23
OUT
3
D2
1N4148
OSC GND
SENS
R5
470
Vgs
Rg
15
CMP
9
Vramp
Vdrv
X3
IRF840
IDS
Rlower
0.97k
14
C1
470pF
13
R13
1k
Vsense
Rsense
1
• Simulate the VGS, VDS, and IDS on Flyback.
Rload
2.5
Turn-on Simulation of Flyback
16.0
1
2 V / div
plot1
vgs in volts
12.0
8.00
50 ns / div
4.00
VGS
0
plot3
vdrain in volts
700
200 V / div
500
VDS
300
50 ns / div
100
2
-100
plot2
ipri in amperes
1.20
200 mA / div
800m
3
400m
50 ns / div
0
IDS
-400m
1.01995m
1.02005m
1.02015m
time in seconds
• VGS rises with Miller effect.
1.02025m
1.02035m
Turn-off Simulation of Flyback
16.0
2 V / div
plot1
vgs in volts
12.0
VGS
8.00
100 ns / div
4.00
0
1
plot3
vdrain in volts
700
200 V / div
500
2
300
100 ns / div
100
VDS
-100
plot2
ipri in amperes
1.20
800m
200 mA / div
IDS
400m
100 ns / div
0
3
-400m
1.0244m
1.0246m
1.0248m
time in seconds
• Turn off with Miller effect.
1.0250m
1.0252m
Turn-on Procedure for Soft-switching
• Because of ZVS, there is no Miller
effect as turning on.
VGS
VTH
• The switching losses are dominated
by
IG
– The dead time (to reduce S1), and
– Source capability to charge CGS to
reduce S2
VDS
-Vf
ID
• Less driver capability requirement.
S1 S S
3
2
ID depends on
topology
Turn-off Procedure for Soft-switching
The Miller plateau
•
Similar as hard-switching: The Miller
plateau exists as turning off.
•
The difference is that IDS also reduces
at this duration since IDS will go through
the opposite MOSFET as VDS changes.
•
To avoid overlap between 2 MOSFETs,
minimize the duration of S1 ~ S4.
•
Strong DRV’s sink capability is needed.
VGS,Miller
VGS
VTH
IG
VDS
IDS
S1
S2
S3 S4
Simulation Circuit of LLC-HB
V3
{Vbulk}
WV3
*
26
D2
1N4148
IM1
V10
5
R11
15
YM1
IMU
22
B1
Voltage
Mupper
V(G2) < 2.5 ?
0:
15
Δ
23
Δ
M1
IRF840
X12
MBR2045
R10
5m
10
Vbridge
Ls
{Ls}
V4
D3
1N4148
12
1
2
ILmag
Lmag
{Lmag}
IML
Δ
24
?
19
B2
Voltage
VLmag
X13
MBR2045
Mlower 11
R14
15
M2
IRF840
Vcs
IML
ICs
Cs
4
Cs
{Cs}
X3
XFMR-TAP
RATIO = 1/N
ICS
•
•
Simulate the VGS_MU, VDS_MU, and IMU on LLC-HB
To ease the reading of current, the direction of IMU and IML is referred to ICS.
plot1
mlower, mupper in volts
Turn-on Simulation of LLC-HB
1
14.0
2 V / div
10.0
6.00
VGS_ML
VGS_MU
200 ns / div
2.00
2
-2.00
400
200 V / div
plot2
ym1 in volts
300
200
200 ns / div
VDS_MU
100
0
3
plot3
im1, iml in amperes
2.00
1.00
I_MU
I_ML
5
0
500 mA / div
4
-1.00
Not overlap; it is the current through CDS
-2.00
10.1922m
•
•
10.1926m
10.1930m
time in seconds
10.1934m
10.1938m
VGS_ML off, ICS reduces VDS_MU for ZVS.
VDS_MU is 0 V BEFORE VGS_MU, so VGS_MU rises smoothly.
200 ns / div
Plot1
mlower, mupper in volts
Turn-off Simulation of LLC-HB
1
14.0
2 V / div
10.0
6.00
VGS_ML
VGS_MU
2
-2.00
400
Plot2
ym1 in volts
100 ns / div
2.00
3
200 V / div
300
200
100 ns / div
VDS_MU
100
0
Plot3
iml, im1 in amperes
2.00
500 mA / div
1.00
5
4
0
-1.00
VGS_ML
I_MU
-2.00
10.1976m
10.1978m
10.1980m
time in seconds
10.1982m
• Strong turn off capability is required.
10.1984m
100 ns / div
Driver Comparison between Hard-Switching
and Soft-Switching
Hard-switching
Soft-switching
Source capability
requirement
Medium
Low
Sink capability
requirement
High
High
Dead time accuracy
requirement
Accurate
Accurate
The Solutions for High-Side Driver
• Transformer-based solution
– Single DRV input
– Dual DRV inputs
• Silicon integrated circuit driver: dual outputs
– Single DRV input
– Dual DRV inputs
Agenda
•
Topologies using a half-bridge configuration
•
The difference between soft and hard-switching
•
The gate-drive transformer
•
The all-silicon-solution
•
Comparison
•
Conclusions
Consideration as Designing Driver
Transformer
• Ground-referenced floating drive – keep 500 V isolation if a 400 V
pre-regulated PFC exists.
• Minimize the leakage inductance - the delay between output and
input windings may kill the power MOSFETs.
• Follow Faraday’s law – keep V*T constant, otherwise, saturate.
• Keep enough margin from saturation – the worst case happens
with transient load at high line.
• High permeability ferrite – minimize the IM.
• Keep high sink current capability
Single DRV Input
VDRV - VC
Driver
Dead time generator
VC
+
RC
CC
RGS
- VC
VC = DVDRV
Q>
1
RC
LM
= 0.5
CC
RC ≥
1
Q
LM
L
=2 M
CC
CC
DRV
C C to reset the driver
transformer and R C to
damp the L-C resonance.
•
An ac coupling capacitor (CC) is needed to reset the driver transformer flux.
•
The amplitude of VGS is dependent on duty. /
•
•
•
With (-VC) to turn off at steady state, but the sink capability is limited at start-up. /
Need a fast time constant (LM//RGS * CC) to avoid flux walking due to the fast transient.
Watch out the ringing between CC and drive transformer at skip mode or UVLO, a diode is
needed to damp the ringing.
Single DRV Input with DC Restore
VDRV - Vf
Dead time generator
Driver
VC
+ RC CC1
- Vf
VC-Vf
-
+
RC ≥ 2
CC2
RGS
DRV
VC = DVDRV
•
VGS amplitude is independent on duty ratio at steady state.
•
Limited sink capability. /
LM
CC
Single DRV Input with PNP Turn-Off
Dead time generator
Driver
DRV
• A pnp transistor + diode help to improve the switching off.
Don’t Forget the AND Gate
Dead time generator
High-side Driver
CC1
CC2
DRV
•
•
Add the totem-pole drivers if output capability of AND gate is limited.
Is the design finished?
Î No, not yet. Pay attention to the ringing among CC1, CC2 and driver
transformer when skip or UVLO. A diode and resistor to damp the ringing. /
Dual Polarity Symmetrical DRV Inputs
Driver
VDRV
- VDRV
DRVA
VDRV
- Vf
Roff
DRVB
Roff
•
•
•
DRVA and DRVB are opposite-polarity and symmetrical Î no ac coupling capacitor.
This is suitable for push-pull type circuit, e.g. LLC-HB, but NOT for asymmetrical type, e.g.
AHB or active clamp. /
Pay attention to the flux of driver transformer at line/load transient.
•
•
The strong turn off capability is still needed. /
Pay attention to the delay caused by the leakage inductance. Î minimize the leakage
inductance and use dual output windings instead of single output winding.
•
Extra losses caused by voltage drop on Roff. /
The Driver Transformer
• Pros
– A transformer is more robust than a die!
– Less sensitivity to spurious noise and high dV/dt pulses
– Cheap?
• Cons
–
–
–
–
Complicated circuits
Pay attention on extreme line/line condition & off mode ……
Pay attention on the leakage inductance and isolation
Is the sink capability strong enough?
Agenda
•
Topologies using a half-bridge configuration
•
The difference between soft and hard-switching
•
The gate-drive transformer
•
The all-silicon-solution
•
Comparison
•
Conclusions
Silicon Half Bridge Driver Principle
Integrated HB driver
• Principle
LLC converter
Vbulk
Single Input
– Single or dual inputs
– High & low side driver
VBoot
DRV_HI
Vcc
in
out
M1
Gnd
GND_HI
IN
Integrated HB driver
in
in
out
M1
GND_HI
Vcc
DRV_LO
Vcc
in
out
M2
Gnd
GND
Dual Inputs
out
M2
GND
DRV_HI
Gnd
IN_LO
DRV_LO
Gnd
VBoot
IN_HI
Vcc
Vcc
Vbulk
Vcc
Dead
Time
C1
Silicon Solution, What are its Limits?
• High-side isolation – 600 V is reached within the silicon.
• Matched propagation delay between high and low side
drive – Prevents any unbalanced transformer usage.
• High side driver supply – Bootstrap supply is requested.
• Noise immunity – Negative voltage robustness of the high side driver.
Silicon Solution, High Voltage Isolation
Level shifter
sustains up to
600 V
Vbulk
Floating area
VBoot
DRV_HI
Vcc
IN_HI
Pulse
Trigger
Level
Shifter
S Q
in
out
M1
Gnd
GND_HI
R
Vcc
DRV_LO
Vcc
IN_LO
in
M2
out
Gnd
GND
• Pulse trigger: generates pulse on each edge from IN_HI
input.
• Level shifter: shifts pulses from GND reference to GND_HI
reference.
• SR flip flop: latches pulses information from the level shifter.
Silicon Solution, Matched Propagation Delay
Vbulk
VBoot
DRV_HI
Vcc
IN_HI
Pulse
Trigger
Level
Shifter
S Q
in
out
M1
Gnd
GND_HI
R
Vcc
DRV_LO
Vcc
IN_LO
Delay
in
M2
out
Gnd
Delay compensation
GND
• Delay is inserted on the fastest path: Low side driver path
Î to compensate: Pulse trigger + level shifter and SR flip-flop delays.
Silicon Solution, High Side Driver Supply
Bootstrap connected to Vcc
Rboot
Vcc
Dboot
Vbulk
Vboot
DRV_HI
Vcc
in
Cboot
out
M1
Gnd
Bridge
Vcc
Vcc
DRV_LO
Vcc
in
out
CVcc
M2
Gnd
GND
Bootstrap Step:
• Step 1: M2 is closed Î Cboot is
grounded: Cboot is refueled via
Vcc.
• Step 2: M1 & M2 are opened Î
Bridge pin is floating, Dboot is
blocked & Cboot supplies floating
area.
• Step 3: M1 is closed Î bridge pin
moved to bulk level, Dboot is still
blocked & Cboot supplies floating
area.
• Bootstrap technique is used for supplying the high side
driver
Root of High Side Driver Negative Voltage?
• Let’s focus on the half-bridge branch:
– the load connected to a half-bridge branch is inductive:
– like an LLC-HB
– Or with the most simple case in a synchronous buck (where body
diodes of the mosfet are represented).
Vbulk
M1
Dbody1
M2
Dbody2
LLC-HB
Theory: Buck Converter Operation
• 1st step of the buck converter:
Vbulk
IL
M1 ON
IL
Time
VBridge
VBridge
VBulk
M2 OFF
Time
Step 1:
M1 ON
M2 OFF
Step:
1
Theory: Buck Converter Operation
• 2nd step of the buck converter:
Vbulk
IL
M1 OFF
Time
VBridge
IL
VBridge
VBulk
M2 OFF
Time
-Vf
Step 2:
M1 OFF
M2 OFF
Step:
1
2
Theory: Buck Converter Operation
• 3rd step of the buck converter:
Vbulk
IL
M1 OFF
Time
VBridge
IL
VBridge
VBulk
M2 ON
Time
-Vf
Step 3:
M1 OFF
M2 ON
Step:
1
2
3
Theory: Buck Converter Operation
• 4th step of the buck converter:
Vbulk
IL
M1 OFF
Time
VBridge
IL
VBridge
VBulk
M2 OFF
Time
-Vf
Step 4:
M1 OFF
M2 OFF
Step:
1
2
3
4
1
Bench: Buck Converter Operation
• Anywhere but in a ppt file there are parasitic elements:
– True buck converter:
Vbulk
M1
Dbody1
M2
Dbody2
Parasitic
inductances
Parasitic
Capacitors
Bench: Buck Converter Operation
• 1st step of the buck converter:
Vbulk
IL
M1 ON
IL
Time
VBridge
VBridge
VBulk
M2 OFF
Time
Step:
Step 1:
M1 ON
M2 OFF
1
Bench: Buck Converter Operation
• 2nd step of the buck converter:
Vbulk
IL
M1 OFF
Time
VBridge
IL
VBridge
VBulk
M2 OFF
Time
-Vf
Step 2:
M1 OFF
M2 OFF
Step:
31.8V
1
2
20.0V
0V
-10.0V
1.452846ms 1.453000ms
V(BRIDGE)
1.453200ms
Time
1.453400ms
Bench: Buck Converter Operation
• 3rd step of the buck converter:
Vbulk
IL
M1 OFF
Time
VBridge
IL
VBridge
VBulk
M2 ON
Time
-Vf
Step 3:
M1 OFF
M2 ON
Step:
1
2
3
Bench: Buck Converter Operation
• 4th step of the buck converter:
Vbulk
IL
M1 OFF
Time
VBridge
IL
VBridge
VBulk
M2 OFF
Time
-Vf
Step 4:
M1 OFF
M2 OFF
Step:
1
2
3
4
1
Bench: Buck Converter Operation
• Negative voltage on bridge pin will create negative current
injection inside the IC driver.
Floating area
Vbulk
VBoot
DRV_HI
Vcc
IN_HI
Pulse
Trigger
Level
Shifter
S Q
in
out
M1
Gnd
VBridge
Bridge
R
Vcc
DRV_LO
Vcc
IN_LO
Delay
in
out
M2
Gnd
GND
Leaky path when VBridge < 0V
This leakage path could create some trouble inside the driver IC.
How to Characterize the Negative Voltage?
VBridge
VBulk
Time
-Vf
VBridge
Principle:
¾ Negative pulse is added on
bridge pin:
¾ With adjustable
Negative voltage
Time
Vneg
Width
¾ And adjustable Width
At each pulse width the neg. voltage is increased until the driver IC fails.
How the Negative Voltage has Been Created?
IC Driver
VCC
D4
R4
MBR1100
1
2
IN_HI
3
IN_LO
4
U1
NCP5106A
VCC
VBOOT
IN_HI
DRV_HI
IN_LO BRIDGE
GND
C11
100n
10R
DRV_LO
VDC_IN
20V
R2
10R
8
Q1
Q2N2907
7
Q5
FDP3682
R8
47k
Synchronous
Buck
Converter
0
D6
BZX84C18
Vout
L1
6
100uH
5
R1
1R
0
C3
220uF
50V
R3
Sync
10R
Pulse gen.
Q2
Q2N2907
Q4
FDP3682
R9
47k
Adj. pulse
width
1
2
C7
10uF
25V
C19
100nF
D11
D1N4148
C13
0
D14
D1N4148
0
0Vdc to 50V
0
TX1
100V
330uF
C4
100nF
C12
Vneg
Q6
FDP3682
100n
U5
MC33152
Rload1
10R
D5
BZX84C18
VCC
D13
D1N4148
Rload
10R
R10
47k
Negative pulse generation
D7
BZX84C18
Adj. VNeg
Example of Negative Voltage Measurement
VG_LO
When the bridge
pin is released, it
generates some
noise on the hiside driver.
(10 V/div)
VG_HI
(10 V/div)
Vbridge pin
(20 V/div)
Time
Vneg = -18 V
(80 ns/div)
Width = 150 ns
Note: Negative voltage pulse is applied when the bridge pin voltage is
reaching zero.
Negative Voltage Characterization
Negative Voltage versus Neg. pulse duration @
+25°C
0
100
Negative pulse duration (ns)
200
300
400
500
600
Negative pulse voltage
(V)
0
-5
-10
-15
-20
-25
-30
-35
If the negative pulse is inside
this area, the driver will work
properly.
If the negative pulse is inside
this area, the driver will not work
properly or can be damaged.
Negative Voltage Characterization
in Temperature
Negative Voltage versus Neg. pulse duration @ different
Temp
Negative pulse duration (ns)
0
100
200
300
400
500
600
Negative pulse voltage
(V)
0
-5
-40°C
-10
25°C
-15
125°C
-20
-25
-30
-35
• Note: These characterizations will be available in each IC driver datasheet
Driver IC Remarks
• ON Semiconductor defines electrical parameters on overall
temperature range (here -40℃ < Tj < +125 ℃). See
electrical table & characterization curves.
• Competitors define the electrical parameters only at Tamb =
+25℃. Temp characterization is not always available
Î what about min & max over extended temperature
range?
• The competitors values extracted from the curves probably
do not take into account the lot to lot process variations
Î the range variation is probably wider.
ON Semiconductor IC Driver Cross Reference
Drive trise /
tfall typ.
(CL=1 nF)
Propag.
Delay typ.
tON / tOFF
Matching
Delay
Typ / Max
Cross
Conduction
Protection
Pin-Out
Compatibility
40 ns
/ 20 ns
100 ns /
100 ns
20 ns / 35 ns
-
IR2181 –
IRS2181
•3.3 V CMOS/TTL inputs
NCP5181
100 ns /
100 ns
-
IR2106 –
IRS2106,
FAN7382
•3.3 V CMOS/TTL inputs
NCP5106A
85 ns /
35 ns
NCP5106B
85 ns /
35 ns
100 ns /
100 ns
3
IR2106 –
IRS2106,
FAN7382
•3.3 V CMOS/TTL inputs
•Internal fixed dead time 100 ns
NCP5304
85 ns /
35 ns
100 ns /
100 ns
3
IR2304 IRS2304,
L6388/84
FAN7380
•3.3 V CMOS/TTL inputs
•Internal fixed dead time 100 ns
NCP5111
85 ns /
35 ns
750 ns /
100 ns
NA
IR2111 –
IRS2111,
NCP5104
85 ns /
35 ns
620 ns /
100 ns
NA
IR2104 –
IRS2104
20 ns / 35 ns
20 ns / 35 ns
20 ns / 35 ns
30 ns / 60 ns
10 ns /45 ns
Remarks
•3.3 V CMOS/TTL input
•Internal fixed dead time 650 ns
•One pin for creepage
•3.3 V CMOS/TTL input
•Internal fixed dead time 520 ns
Agenda
•
Topologies using a half-bridge configuration
•
The difference between soft and hard-switching
•
The gate-drive transformer
•
The all-silicon-solution
•
Comparison
•
Conclusions
LLC-HB Schematic with Driver Transformer
+400 V
Vcc
41
NCP1395A
R16 75k
29
Vcc
R24 250k
U5A
SFH615-A
FF
3
42
14
R18
1k
C20
39 4
13
6
5
12
1
6
11
31 7
10
150k
D7
1n5818
14
C18
22u
R29
47k
10u
D15
1n5818
Q5
2N2907
Vcc
1
.
C17
0.1u
C16
10u
C14
10n
C13
InB
30
100n
R17
1k
Q2
2N2222
D5
1n5818
6
21
OutA
2
28
Q10
2N2907
33
R4
1k
R30
ETD44
ET4415A
P = 4W
T1
XFMR
L1
11
3
D12
mbr1645
4
27
5
OutB
24
32
R21
1k
Q11
2N2907
out
D11
mbr1645
24 V / 10 A
Irms=5 A
C3b
1mF
D10
1N4148
R20
10
L3
4.7uH
4
26
8
D3
mbr1645
R9
47k
C3c
1mF
Part number = EEUFC1V102
D6
mbr1645
C8
100p
C1
Gnd
C2
680uF
Part number = EEUFC1V681
C3a
1mF
C10
C7
M2
IRFB11N50A
KL195/25,4SW
D17
1n5818
PCV-0-472-20L
int
22
23
Q6
2N2907
R15 540
Heatsink
18°C/W
KL112-25
KL195/25,4SW
VB
5
3
M1
IRFB11N50A
R5
47k
12
47k
15
.
25
.
9
8
2
17
R10
10
34
T2
Q3903-A
20
FF
C15
100n
Q1
2N2222
R19 5.2k
R22
4.7k
BO
R33
5.6k
38
InA
15
C19 10u
timer
C11
10n
2
R11 160k
R25
1.8Meg
R12
R32
33k
37
D8
1N4148
16
1
1 kV
7
19
analog ground
45
D4
1N4148
Gnd
out
int
R23
10k
0V
R1
22k
R14
10k
10
R6
10k
R2
22k
R7
86k
13
C4
10n
C1
22nF
Part number = PHE450MB5220JR06
EVOX RIFA 630 V
LLC controller
NCP1395
Driver
Transformer
0.47uF
Part number = PHE450MF6470JR06L2
C6
470p
U5B
SFH615-A
R3
22k
18
C7
EVOX RIFA 630 V
100uF
Part number = 2222-05737101
C10
Snap-in BC Comp. 450 V
C5
470p
40
U2
TL431
16
L1
PCV-0-274-04
220u
• LLC-HB with 24 V @ 10 A
• NCP1395, the LLC controller with dual DRV outputs.
• Transformer drivers the MOSFETs of LLC converter.
R8
10k
LLC-HB Schematic with Driver IC
+400 V
41
NCP1395A
R16 75k
29
U5A
SFH615-A
R32
33k
FF
39
4
13
6
5
12
1
6
11
31 7
10
14
R12
150k
R28
47k
C20
10u
FF
C15
100n
C18
22u
51
28
D2
1N4148
8
36
2
7
44
M1
IRFB11N50A
Heatsink
18°C/W
KL112-25
KL195/25,4SW
ETD44
ET4415A
R5
47k
C9
100nF
VB
6
4
OutA
2
1
3
17
R26
10
11
P = 4W
T1
XFMR
L1
3
PCV-0-472-20L
C14
10n
9
8
InB
R31
47k
D12
mbr1645
C3b
1mF
OutB
23
C13
30
100n
12
24 V / 10 A
Irms=5 A
4
26
5
R27
10
24
D9
1N4148
D3
mbr1645
KL195/25,4SW
C3c
1mF
Part number = EEUFC1V102
D6
mbr1645
C8
100p
C1
Gnd
15
C2
680uF
Part number = EEUFC1V681
C3a
1mF
8
C10
C7
M2
IRFB11N50A
R9
47k
R15 540
out
D11
mbr1645
5
C12
100n
L3
4.7uH
int
R19 5.2k
R22
4.7k
BO
R33
5.6k
14
42
C19 10u
timer
C11
10n
3
38
R13
10
U1
NCP5181
InA
15
2
R11 160k
R25
1.8Meg
25
D1
1N4937
16
1
R24 250k
37
35
Vcc
1 kV
7
45
analog ground
D4
1N4148
Gnd
out
int
R23
10k
0V
R1
22k
R14
10k
10
R6
10k
R2
22k
R7
86k
13
C4
10n
C1
22nF
Part number = PHE450MB5220JR06
EVOX RIFA 630 V
LLC controller
Driver IC
0.47uF
Part number = PHE450MF6470JR06L2
NCP5181
R3
22k
18
C7
EVOX RIFA 630 V
100uF
Part number = 2222-05737101
NCP1395
C6
470p
U5B
SFH615-A
C10
Snap-in BC Comp. 450 V
C5
470p
40
U2
TL431
16
R8
10k
L1
PCV-0-274-04
220u
• LLC-HB with 24 V @ 10 A
• NCP1395, the LLC controller with dual DRV outputs.
• NCP5181, driver IC drives the MOSFETs of LLC converter.
VGS Waveform
2 µs / div
VGS_ML
(5 V/div)
VGS_MU
(5 V/div)
IMU
(2 A/div)
VDS_ML
(100 V/div)
Driver transformer
• The waveforms seem similar.
Driver IC (NCP5181)
High Side MOSFET Turns Off
Turn-off
comparison
80 ns / div
VGS_ML
(5 V/div)
VGS_MU
(5 V/div)
IMU
(2 A/div)
VDS_ML
(100 V/div)
Driver transformer
Driver IC (NCP5181)
• The driver IC turns off the MOSFETs more vigorously.
• IC turn-off is 70 ns faster, lowering the switching losses
High side MOSFET Turns On
Turn-on
comparison
200 ns / div
VGS_ML
(5 V/div)
VGS_MU
(5 V/div)
IMU
(2 A/div)
VDS_ML
(100 V/div)
Driver transformer
Driver IC (NCP5181)
• The driver IC keeps safe and enough dead time between
high and low side MOSFETs.
The Efficiency Comparison
Input
power
(W)
128.33
257.2
Driver IC
128.34
Driver
Transformer 258.5
Output
power
(W)
119.72
235.46
119.72
236.46
Vout
(V)
23.96
23.57
23.96
23.67
Iout
(A)
5.00
9.99
5.00
9.99
η
93.29%
91.55%
93.29%
91.48%
• There is no efficiency difference between the IC driver and
transformer solutions.
Agenda
•
Topologies using a half-bridge configuration
•
The difference between soft and hard-switching
•
The gate-drive transformer
•
The all-silicon-solution
•
Comparison
•
Conclusions
Conclusion: Transformer or IC?
• Both solutions work if well-trimmed.
• We recommend the IC solution because:
– We don’t sell the transformer.
– Manual insertion for the transformer.
– Ease the layout
– Ease the design
– Free of transformer problems, e.g.:
•
•
•
•
isolation is destroyed,
flux walking away,
unexpected ringing after turn off,
Height of the transformer in low profile PSU
For More Information
•
View the extensive portfolio of power management products from ON
Semiconductor at www.onsemi.com
•
View reference designs, design notes, and other material supporting
the design of highly efficient power supplies at
www.onsemi.com/powersupplies