The integrated circuit has been designed using BYE technology (BiCMOS 0.8
µ m) as from HIT-KIT v3.10. Die area is 2.5x2.5mm
2
and it has to be housed in TQFP44 package.
One chip contains four independent analog chains. Two separate power supplies are foreseen, in order to minimise mutual interference, for the input section (Vcc=5V) and for the output stages (Vdd=2.5V); several pins are reserved for power and for ground that is as well different for the input (GNA) and for the output (GND). The block diagram of the chip is shown here below.
GNA VCC T_OUT T_EN W_CTRL GND D_ENL1 D_ENL2 VDD
In1
A_EN1
A_EN2
In2
GNA
VCC
GNA
In3
A_EN3
A_EN4
In4
PA
PA
PA
PA
SHAPER
BLR
BLR
SHAPER
TEMP
PROBE
SHAPER
BLR
BLR
SHAPER
DISCR LATCH
ONE
SHOT
LVDS
DRIV
DISCR LATCH
ONE
SHOT
LVDS
DRIV
WIDTH
CTRL
BIAS
DISCR LATCH
ONE
SHOT
LVDS
DRIV
DISCR LATCH
ONE
SHOT
LVDS
DRIV
OUTP1
OUTN1
GND
OUTN2
OUTP2
BYP
OUTP3
OUTN3
GND
OUTN4
OUTP4
GNA VCC <T> VTH VREF GND D_ENR1 D_ENR2 VDD
Each channel is made of a low noise charge preamplifier followed by a shaper whose quiescent level is set by a baseline restorer to an external reference voltage (pin
VREF) common to the four chains. A negative charge pulse applied to the input of the preamplifier causes a positive signal at the output of the shaper, superimposed to the reference level, that is compared against an external threshold (pin VTH), common to the four channels, by a fast discriminator; its output is stretched by a latch

enabled by a one-shot, whose pulse width is inversely proportional to the current sunk from W_CTRL pin, again shared by all channels.
The non retriggerable pulse so produced is then buffered by a differential voltage driver and the outputs (pins OUTP(1-4)
& OUTN(1-4)) are able to feed a 120
Ω
load placed across them with LVDS compatible levels.
Each channel can be disabled by a TTL high level applied to pins A_EN(1-4), recovery to normal operation requires about
10
µ s. Channels 1 & 2 (left channels) can be enabled/disabled in about 30ns by a differential signal applied to pins
D_ENL(1-2), the same for right channels 3 & 4 via pins
D_ENR(1-2).
An absolute temperature sensor is included in the chip, having an output of
7.5mV/ o
K that is available at pin <T> and at pin T_OUT (22k
Ω
external resistor to ground) after a unity gain buffer enabled by a TTL high level applied to pin T_EN.
An internal generator biases the whole chip, its output is connected to pin BYP for bypassing with a capacitor to GNA.
The table below lists all pins of the chip and their use; the pinouts is shown in the right top of the page.
GNA
GND
VCC
VDD
BYP
VTH
VREF
In(1-4)
T_OUT
<T>
T_EN
A_EN(1-4)
D_ENR(1,2)
Analog ground
Digital ground
+5V power supply
+2.5V power supply
Internal reference voltage output
Threshold voltage
Signal reference baseline voltage
4 input channels
Temperature probe output, externally enabled with pin T_EN
Temperature probe output
T_OUT enable (logic level high, internally pull up)
4 analog masks enable (logic level high, internally pull down)
Digital right mask enable (D_ENR1 high, D_ENR2 low)
D_ENL(1,2) Digital left mask enable (D_ENL1 high, D_ENL2 low)
W_CTRL Output time width control, common to all channels
OUTN1, OUTP1 Differential output channel 1, LVDS compatible levels
OUTN2, OUTP2 Differential output channel 2, LVDS compatible levels
OUTN3, OUTP3 Differential output channel 3, LVDS compatible levels
OUTN4, OUTP4 Differential output channel 4, LVDS compatible levels
O
O
O
-
O
I
I
-
-
-
I
O
O
I
I
I
I
I
O
A
A
A
-
A
A
A
-
-
-
A
A
A
D
D
A
A
A
A
-
-
Capacitor of 100nF to ground
Capacitor of 100nF to ground
Capacitor of 100nF to ground
VREF + threshold (3mV/fC)
Usually 1.5V
-
About 7.5mV/°K, low Z out
22K
Ω
resistor to ground
About 7.5mV/°K, high Z out
TTL level
TTL level
High: 1.5-1.6 V
Low: 1.2-1.3 V
High: 1.5-1.6 V
Low: 1.2-1.3 V
Usually resistor to ground
120
Ω
terminating resistor between
120
Ω
terminating resistor between
120
Ω
terminating resistor between
120
Ω
terminating resistor between
Two test phases are foreseen for this integrated circuit: the first one, at wafer level, is thought to select good dices working within predefined tolerances (derived from corner analysis).

The second phase, that applies to finished parts, aims to detect problems arisen during bonding or packaging.
All tests should be performed at T
A
= 25±1°C. For the first phase please note that, since no test pads are included in the chip, all tests are performed through I/O pads.
Also note that for dynamic or ac tests all power and ground pins must be connected, and that GNA and GND should be connected together with the lowest possible resistance/inductance path.
All numeric values given in this test description are derived from simulations and from tests on a similar circuit; refinements of acceptance limits for some measurements (due to characteristics of the test setup) will be eventually discussed on the basis of experience on engineering samples.
The figures in this page present the simulated behaviour of one electronic chain of the ASIC excited by a voltage pulse generator. In this simulation the pulse generator is started at 10ns from time origin with an amplitude of 10mV (note that we are interested in negative charges, so the trigger time has to be taken at the falling edge of the generator pulse).
The figures show the voltage across the generator, the preamplifier input current and the output differential signals across a 120
Ω
resistor load; the duration of the output signals is set at about 100ns by a current sinking generator of 20
µ
A (the same width can be obtain with a 200K
Ω
resistor to ground).

The ASIC has some control signals for setting the threshold/reference voltages, enabling digital and analog masks and the temperature probe output:
•
2 control voltages for threshold and baseline reference:
•
VREF: shaper output baseline voltage, range from 1 to 3 V and usually set at 1.5V
•
VTH: discriminator threshold voltage, VREF plus threshold value (about
3mV/fC)
•
1 digital control input for enabling temperature probe output T_OUT
(internally pull up), T_EN:
•
T_OUT enable: TTL level high
•
T_OUT disable: TTL level low
•
4 digital control inputs for analog masks (internally pull down), A_EN(1-4):
• mask enable (channel disable): TTL level high
• mask disable (channel enable): TTL level low
•
2 differential control inputs for digital masks, D_ENR(1,2) and D_ENL(1,2):
• mask enable (channel disable): D_EN(R/L)1 high, D_EN(R/L)2 low
• mask disable (channel enable): D_EN(R/L)1 low, D_EN(R/L)2 high
The figures below show the characteristics of the control signals for masks and temperature probe features. Note that even if high levels of analog mask and temperature probe are set to 5V, actually only a TTL compatibility is required.

This test is intended to discover all possible die problems, so static and dynamic measurements are foreseen.
Chips have to pass all listed tests for qualification.
Test setup
The figure below shows the test setup, the voltage generators and passive components required and their connections.
•
Required voltage generators
•
5V power generator (5±0.1 V, ripple below 1%)
•
2.5V power generator (2.5±0.05 V, ripple below 1%)
• reference voltage generator (1.5V, low noise)
• threshold voltage generator (1490 to 1530 mV, low noise)
•
100fC and 1pC charge generator (
≥
100 pulses, rate 1MHz and 20% charge tolerance):
– either a current pulse generator; width
≤
3ns and current resolution
≤
5uA
– or a voltage pulse generator with series capacitor of about 2pF (charge generated is equal to the product of pulse amplitude times series capacitor); with tr, tf
≤
3ns and Vout resolution
≤
10mV. A parasitic capacitance of up to 10pF to ground is allowed, anyhow this can affect some performances.

•
5 digital signal sources, TTL level:
•
4 analog masks
•
1 temperature probe enable
•
2 differential signal sources (high: 1.6-1.5 V, low: 1.2-1.3 V; rise and fall times
≤
5ns):
• right channels digital mask, D_ENR(1,2)
• left channels digital mask, D_ENL(1,2)
•
Other pins
• all differential output pins are connected with 120
Ω
terminating resistors
(one for each channel) across OUTN and OUTP
•
W_CTRL: resistor to ground or current sinking generator
•
T_OUT: 22K
Ω
(1%) to ground.
•
GNA and GND to common ground with the lowest possible resistance/inductance path
Warm up
•
VCC and VDD power on:
•
VCC = 5 ± 0.1 V
•
VDD = 2.5 ± 0.05 V
•
Set threshold and reference voltage:
•
VTH = 1530±1mV
•
VREF = 1500±1mV
•
Disable all masks and disable temperature probe output:
•
T_EN low
•
A_EN(1-4) low
•
D_EN(R/L)1 low, D_EN(R/L)2 high
Warm up time
≥
10ms after power on of all generators
Static tests
•
VDD and VCC current drain (see table below for corner values)
•
Check operating points voltages be within assigned windows (see table below for corner values):
•
8 outputs, OUTN(1-4) and OUTP(1-4)
•
4 inputs, In(1-4)
•
1 internal reference, BYP
•
1 temperature probe output, <T>
•
1 temperature probe output, T_OUT
VDD and VCC current drawn (T
A
= 25°C)
VDD (sum of all VDD pins)
VCC (sum of all VCC pins)
16mA 24mA
8.5mA 14.5mA
Operating points voltages (T
A
= 25°C)

BYP
In(1-4)
<T>
T_OUT
OUTP(1-4)
OUTN(1-4)
2.100V 2.200V
740mV 780mV
2.2V 2.3V
0 500mV
970mV 1050mV
1350mV 1450mV