Agilent Technologies
Diode Modeling Strategy
From DC -> CV -> Spar -> Spectrum
Franz.Sischka@agilent.com
Agilent Technologies
1
forward
What we are going to model:
reverse
DC forward
DC reverse
... a real, measured diode which cannot be
modeled with a simple SPICE diode model ...
CV
S-Parameter
Spectrum
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Introducing the SPICE Diode DC model
RS
BV
IBV
slope ~ 1/N
IS
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Unfortunately, this is not the reality !!!
3
Therefore, we will use a
sub-circuit for modeling the diode, consisting
of several diode *LEGO* pieces
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DC forward Parameter Extraction
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applied to a diode DC characteristic:
higher current at a given vD means a parallel diode
RS
AI
N
DMAIN
DM
DLOW
OW
L
D
ΔI
vD
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... and a higher voltage at a given iD means a series diode
RS
ΔV
DSAT
RS
iD
DM
AI
N
DMAIN
AT
S
D
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Developing the customized DC forward Model
stepping from low
to high voltage bias,
a real diode exhibits a
1.
DL
OW
DMAIN
T
4. RS
2. D
DSAT
DLOW
3
MA
IN
RS
SA
.D
ideal diode model:
⎡
⎛ ia ⎞ ⎤
ia ( v a ) = IS ⋅ ⎢ exp ⎜
⎟ − 1⎥
⎝ vt ⋅ N ⎠ ⎦
⎣
->
->
->
->
recombination range
MAIN diode range
transition to ohmic
ohmic range
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This leads to the "DC forward" subcircuit
-> The subcircuit is based
on the measurements.
.SUBCKT LED 1=A 2=C
*forward bias modeling
RS
1 11 1m
DSAT
DMAIN
DLOW
*model
.MODEL
.MODEL
.MODEL
11 12
12 2
12 2
cards
DLOW
DMAIN
DSAT
DSAT
DMAIN
DLOW
D
D
D
IS=1E-20
IS=1E-27
IS=.01
-> The extraction strategy follows
out of that.
-> The parameters of the 3 diodes
are extracted from the individual
diode sub-range
N=3
N=1
N=.7
1
.ENDS
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12
2
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DC Forward Modeling step-by-step
recombination
diode modeled
serial
diode modeled
MAIN
diode modeled
series resistor
modeled
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DC reverse Modeling
ohm
in negative biased mode
from low to high current,
our diode exhibits a
-> MAIN diode range,
-> transition to ohmic,
-> ohmic range
ic
M
N
AI
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This enhances the subcircuit further to:
.SUBCKT LED 1=A 2=C
*forward bias modeling
RS
1 11 1m
DSAT
11 12 DSAT
DMAIN
12 2 DMAIN
DLOW
12 2 DLOW
1
cards
DLOW
DMAIN
DSAT
DREV
D
D
D
D
IS=1E-20
IS=1E-27
IS=.01
IS=1E-15
12
2
21
*reverse bias modeling
DREV
2 21 DREV
RSREV
21
1 1m
*model
.MODEL
.MODEL
.MODEL
.MODEL
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N=3
N=3
N=.7
N=5
corresponding to the
measurements,
the subcircuit
i.e. THE MODEL
is enhanced
and the model parameters
are extracted.
.ENDS
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DC reverse Parameter Extraction
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DC Reverse
Modeling step-by-step
reverse MAIN
diode modeled
(pA range ignored,
meas.resolution!)
reverse
series resistor
modeled
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Cac ( v ac ) =
CV Modeling
CJO
C JO
⎛⎜ 1 −
⎝
v ac
VJ
⎞⎟
⎠
M
Parameter CJO
corresponds to
CV(Vac=0V).
M models the CV slope
in the OFF state
M
VJ models the CV slope
in the ON state
VJ
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Junction Capacitance Formula
Cs (pF)
LCRZ
meter
1.6p
For vD < FC * VJ there is :
Cj
C s (vD ) =
Mj
v
⎛
⎞
⎜ 1 − VD ⎟
j ⎠
⎝
and else :
1.2p
slope: MJ
0.8p
CJ
-3
⎡
vD ⎤
Cs ( v D ) =
* 1 − FC * (1 + MJ ) + MJ *
⎥
(
1+MJ ) ⎢
V
(1 − FC )
J⎦
⎣
-1
0
1 vD (V)
CJ
FC*VJ
VJ
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Linearizing the CV formula (for vD < FC*VJ):
CV curve
Cs =
CJ
⎛
v ⎞
⎜⎜1 − D ⎟⎟
VJ ⎠
⎝
MJ
(1)
A logarithmic conversion of equation (1) yields
ln(Cs) = ln(CJ) - MJ ln[1 - vD / VJ ]
(2)
This equation can be linearized following
ylin
= b
+ m xlin
when substituting:
ylin = ln(Cs)
b = ln(CJ)
m = - MJ
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xlin = ln[1 - vD / VJ]
(3)
(4a)
(4b)
(4c)
(4d)
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This enhances the subcircuit further to:
.SUBCKT LED 1=A 2=C
*forward bias modeling
RS
1 11 1m
DSAT
11 12 DSAT
DMAIN
12 2 DMAIN
DLOW
12 2 DLOW
1
cards
DLOW
DMAIN
DSAT
DREV
D
D
D
D
2
12
21
*reverse bias modeling
DREV
2 21 DREV
RSREV
21 1 1m
*model
.MODEL
.MODEL
.MODEL
.MODEL
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IS=1E-20
IS=1E-27
IS=.01
IS=1E-15
N=3
N=3
N=.7
N=5
CJO=1f
CJO=1m
M=.4
VJ=2
FC=.5
.ENDS
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QUIZ: explain why a DSAT.CJO=1m is required !!!
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CV Parameter Extraction
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CV Modeling step-by-step
Click a box around those
meas. data which are below
the expected FC*VJ. This is
typically a ‘vac‘ which
corresponds to a ‘cac.m‘ not
bigger than 2-3 times CJO
(y-axis intersect of ‘cac.m‘),
and execute Transform
‘br_CJO_VJ_M‘.
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- the starting points
are determined by
the DC fitting
S-parameter Modeling
- the traces vs.
frequency are
determined by the
capacitance
freq
vd
-> usually, only
fine-tuning is
required for the DC
and CV
(not loosing DC and CV
accuracy of course !!)
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QUIZ:
-> where is the locus curve for neg.DC bias ?
-> what explains the shift of the curves starting points
to the right ?
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S-Parameter DC-Off
Modeling
The parasitic Anode-Ground
and Cathode-Ground
capacitors show up
and will be modeled,
together with their
tan-delta losses (RA0, RC0).
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The Off-State S-parameters
have been converted to Y-pars,
and the paras. caps CC0 and
CA0 are fitted
CC0
CA0
CAC
NOTE: CAC was modeled in the CV-modeling section, at 1MHz.
Therefore, it matches nicely (at low freq.).
The C(freq) curve from S-pars, however, exhibits an increase of
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capacitance vs. freq. This is an indicatation for the presence of a
series inductor (see S-par On-State-modeling in the next slides).
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The capacitor losses (RA0 and RC0)
are fitted too,
from S->Y converted S-params
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S-Parameter DC-On
Modeling
The diode Transit Time
and Series Inductor (Package)
show up and will be modeled.
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The screenshot above:
see the Transform README in Setup ‘Spar_mdlg/off_state‘
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Converting S-parameters to CV plots:
The influence of the diode transit time TT to the CV curve
TT=1p
Diffusion Capacitance:
CD = TT * gD
with
gD =
∂ iD
∂ vD
TT=0
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VJ
Quiz: what causes the CV curve to collapse at pos. DC bias ?
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influence of diode conductivity on CV curve
the parallel
diode conductance
'kills' the
capacitance
RS
rdiode
CV
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The influence of the diode transit time TT to S-parameters
TT=0
TT=0
TT=1p
TT=1p
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DISCUSSION:
-> TT shifts Sxx and Sxy for medium DC bias
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This enhances the diode subcircuit further to:
.SUBCKT LED 1=A 2=C
*forward bias modeling
RS
1 11 1m
DSAT
11 12 DSAT
DMAIN
12 2 DMAIN
DLOW
12 2 DLOW
1
11
*reverse bias modeling
DREV
2 21 DREV
RSREV
21
1 1m
*model
.MODEL
.MODEL
.MODEL
.MODEL
cards
DLOW
DMAIN
DSAT
DREV
D
D
D
D
IS=1E-20
IS=1E-27
IS=.01
IS=1E-15
2
12
21
N=3
N=3 CJO=1f
N=.7 CJO=1m
N=5
M=.4
VJ=2
FC=.5
TT=1p
.ENDS
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Package Modeling
- the additional phase shift stems from the package series inductance
freq
LS
vd
freq
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blue: without LS
red: including LS
LS
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This gives the final DC-CV-Spar-Modeling subcircuit:
.SUBCKT LED 1=A 2=C
LS
1 10 1p
*forward bias modeling
RS
10 11 1m
DSAT
11 12 DSAT
DMAIN
12
2 DMAIN
DLOW
12
2 DLOW
1
11
10
*reverse bias modeling
DREV
2 21 DREV
RSREV
21 10 1m
*model
.MODEL
.MODEL
.MODEL
.MODEL
cards
DLOW
DMAIN
DSAT
DREV
D
D
D
D
IS=1E-20
IS=1E-27
IS=.01
IS=1E-15
2
12
21
N=3
N=3
N=.7
N=5
CJO=1f
CJO=1m
M=.4
VJ=2
FC=.5
TT=1p
.ENDS
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Large-Signal RF Modeling
fine-tuning the model by spectrum modeling
• Measurement setup for harmonic distortion (HD) characteristics
(fundamental, 2nd, 3rd and 4th harmonics) for the PIN diodes
• in the ON state (ID= 10mA), the power levels are swept
between -20dBm and +20dBm
• same power levels for the HD characteristics in OFF state (VD= -3V to 0V).
DC
Source
Controller
Diode
Synthesized
Source
PA
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Bias
‘T’
Bias
‘T’
ZS
Spectrum
Analyzer
ZL
50Ω matching to be
checked carefully
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OFF State Spectrum Modeling @ -1.5V
-20dBm .. 20dBm power range
CJO
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M
CJO models the level of the fundamental
M and VJ model the level of the harmonics
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OFF-state time domain locus curve @ -1.5V
-20dBm
ia
ia
va
+20dBm
va
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ON state spectrum modeling @ 0.9V
-20dBm .. 20dBm power range
DC params
TT and LS
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The fundamental is modeled by the DC params
TT and LS model the level of the harmonics
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ON-state time domain locus curve @ 0.9V
-20dBm
+20dBm
ia
va
va
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THE FINAL RESULT
DC – CV – Spar - LargeSignalRF:
DC forward
DC reverse
1
11
10
12
2
21
CV
S-Parameter
Spectrum
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CONCLUSIONS
With the example of a diode,
a typical device modeling sequence from
DC -> CV -> Spar -> Spectrum
was demonstrated.
Such strategies can be applied also to
- all kinds of transistors
- and passive components like
spiral inductors
varactor diodes
resistors
etc.
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The open architecture of IC-CAP, together
with ADS, is an ideal tool for modeling
engineers to successfully develop
accurate models quickly.
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