Home Work 2 Solution
4.8 In the saturation mode also, iD is directly proportional to W . So, if W is halved, then i D would
also be halved. The vertical axis should thereforefore be scaled by 0.5.
For VOV = 1.5V, by looking at the corresponding curve, we observe that i D = 0.5625 mA.
4.15 The NMOS transistor is operating in the linear resistance region (within the triode region), for
which:
0
iD = k n W
L (vGS − Vt )vDS
When vDS = 0.1V, for vGS = 2V, iD = 60 µA, and for vGS = 4V, iD = 160 µA
60µA
160µA
=
(2V − Vt )×0.1V
(4V − Vt )×0.1V
=⇒ Vt = 0.8V
Substituting Vt = 0.8 V in the above equation, we get W/L = 10.
0
Substituting vGS = 3 V, vDS = 0.15 V, and kn = 50 µA/V 2 in the above equation,
we get iD = 0.165 mA.
In the pinch-off region, vDS = vGS − Vt = 3 V - 0.8 V = 2.2 V.
0
2
iD = k n W
L ((vGS − Vt )vDS − 0.5vDS ) = 1.21 mA
4.38 All three transistors are in saturation, as their drains are connected to their respective gates,
guaranteeing that the individual v DS s > their vGS − Vt s. While in saturation, the drain current
is given by:
0
2iD L
2 =⇒ W =
iD = 12 kn W
L (VGS − Vt )
k 0 (V −V )2
n
GS
t
Transistor Q1: VGS = 1.5 V =⇒ W = 8µm
Transistor Q2: VGS = 2 V =⇒ W = 2µm
Transistor Q3: VGS = 1.5 V =⇒ W = 8µm
4.49
a Point A: VIA = Vt = 1 V; VOA = VDD = 5 V.
Point B: This is the boundary between the saturation and triode regions.
i.e., VOB = VIB − Vt .
0
2
Also, IDB = 21 kn W
L (VIB − Vt ) .
VDD −VOB
IDB is also given by IDB =
RD
Solving these two equations together, we get V OB = 0.605 V or −0.688 V, of which only
the former one can be correct. Thus, V OB = 0.605 V.
Then, VIB = VOB + Vt = 0.605 V + 1 V = 1.605 V.
1
b VOV Q = 0.5 V =⇒ VIQ = VOV Q + Vt = 0.5 V + 1 V = 1.5 V.
0
2
IDQ = 21 kn W
L (VIQ − Vt ) = 0.125 mA
VOQ = VDD − IDQ RD = 2 V.
0
Incremental gain at bias point, Av = − RD kn W
L VOV Q = −12V/V.
c The MOSFET will be in saturation for v I ranging from 1 V to 1.605 V. If the bias point
input is 1.5 V, it allows for only a 0.105 V input sine wave.
The amplitude of the output voltage signal that results is approximately equal to V OQ −VOB
= 2 V − 0.605 V = 1.39 V.
amplitude
1.39V
Gain = Output
Input amplitude = 0.105V = 13.29 V/V.
= 10.75% more than the incremental gain calculated in part (b).
This gain is 13.29−12
12
This difference is because the segment of the voltage transfer curve considered here is not
perfectly linear.
4.55 We plan to design the biasing circuit such that the transistor is in saturation mode.
We shall design RD and RS such that roughly one-third of the voltage drop
(i.e., 15 V / 3 = 5 V) occurs across each of these resistors. Then
RD = R S =
1 0 W
2 kn L
In saturation mode, ID =
5V
2mA
= 2.5KΩ
(VGS − Vt )2
0
Substituting ID = 2 mA, kn = 80 µA/V 2 , W/L = 40, and Vt = 1.2 V in this equation, we get
VGS = 2.32 V or 0.487 V, of which only the former is correct.
Thus, VGS = 2.32 V.
Voltage at the gate, VG = VS + VGS = ID RS + VGS = 2mA . 2.5KΩ + 2.32V = 7.32V
From the figure, we can see that VG is obtained by the RG1 -RG2 voltage divider arrangement.
And, because the gate current is zero,
G2
VG = 15V RG1R+R
G2
As VG = 7.32 V is less than 15 V / 2, RG2 < RG1 . Therefore, RG1 = 22MΩ.
Substituting in the above equation, we get R G2 = 20.97MΩ.
With this biasing arrangement, VDS = 5 V. If it is designed to be at the edge of saturation,
VDS = VGS − Vt = 2.32 V − 1.2 V = 1.12 V, which is 5 V − 1.12 V = 3.88 V away from the
edge of saturation.
4.68 In saturation mode, ID =
1 0 W
2 kn L
(VOV )2 = 0.5 × 2mA/V 2 × 1V 2 = 1mA
When a +0.1 V signal is superimposed on V GS , iD = 0.5 × 2mA/V 2 × 1.12 = 1.21mA
Increment in drain current, id = 1.21mA − 1mA = 0.21mA
2
When a −0.1 V signal is superimposed on V GS , iD = 0.5 × 2mA/V 2 × 0.92 = 0.81mA
Decrement in drain current, id = 1mA − 0.81mA = 0.19mA
gm =
id
vgs
=
0.21mA+0.19mA
0.1V +0.1V
=
0.4mA
0.2V
= 2mA/V
0
From Equation 4.62, gm = kn W
L VOV = 2mA/V
The gm values are the same in both cases.
4.75 Because the gate current is zero, V G = VD . Therefore, the transistor is in saturation.
ro =
VA
ID
=
50V
0.5mA
= 100KΩ
VG = VD = 2V
gm =
Voltage gain,
vo
vi
2ID
VGS −Vt
=
2×0.5mA
2V −0.9V
= 0.91mA/V
= − gm (ro k RL ) = − 0.91mA/V (100KΩ k 10KΩ) = −8.3V/V
When I is increased to 1 mA, VGS can be calculated to be 2.5V.
Therefore, VD = VGS = 2.5 V.
50V
New ro = 1mA
= 50KΩ.
gm =
Voltage gain,
vo
vi
2ID
VGS −Vt
=
2×1mA
2.5V −0.9V
= 1.3mA/V
= − gm (ro k RL ) = − 1.3mA/V (50KΩ k 10KΩ) = −10.8V/V
3