CMPEN 411
VLSI Digital Circuits
Lecture 03: MOS Transistor
Kyusun Choi
[Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003
J. Rabaey, A. Chandrakasan, B. Nikolic]
CMPEN 411 L03 S.1
Review: Design Abstraction Levels
SYSTEM
MODULE
+
GATE
CIRCUIT
Vin
Vout
DEVICE
G
S
n+
CMPEN 411 L03 S.2
D
n+
The NMOS Transistor Cross Section
n areas have been doped with donor ions
(arsenic) of concentration ND - electrons
are the majority carriers
Polysilicon
W
Gate
Source
n+
L
Gate oxide
Drain
n+
Field-Oxide
(SiO2)
p substrate
Bulk (Body)
p areas have been doped with acceptor
ions (boron) of concentration NA - holes
are the majority carriers
CMPEN 411 L03 S.3
The MOS Transistor
Polysilicon
CMPEN 411 L03 S.4
Aluminum
Switch Model of NMOS Transistor
| VGS |
Source
(of carriers)
Open (off) (Gate = ‘0’)
Gate
Drain
(of carriers)
Closed (on) (Gate = ‘1’)
Ron
| VGS | < | VT |
CMPEN 411 L03 S.5
| VGS | > | VT |
Switch Model of PMOS Transistor
| VGS |
Source
(of carriers)
Open (off) (Gate = ‘1’)
Gate
Drain
(of carriers)
Closed (on) (Gate = ‘0’)
Ron
| VGS | > | VDD – | VT | |
CMPEN 411 L03 S.6
| VGS | < | VDD – |VT| |
Threshold Voltage Concept
VGS
G
+
D
S
-
n+
n channel
n+
p substrate
depletion
region
B
The value of VGS where strong inversion occurs is called
the threshold voltage, VT
CMPEN 411 L03 S.7
The Threshold Voltage
where
VT = VT0 + (|-2F + VSB| - |-2F|)
VT0 is the threshold voltage at VSB = 0 and is mostly a
function of the manufacturing process

Difference in work-function between gate and substrate
material, oxide thickness, Fermi voltage, charge of impurities
trapped at the surface, dosage of implanted ions, etc.
VSB is the source-bulk voltage
F = -Tln(NA/ni) is the Fermi potential (T = kT/q = 26mV at
300K is the thermal voltage; NA is the acceptor ion concentration;
ni  1.5x1010 cm-3 at 300K is the intrinsic carrier concentration in
pure silicon)
 = (2qsiNA)/Cox is the body-effect coefficient (impact of
changes in VSB) (si=1.053x10-10F/m is the permittivity of silicon;
Cox = ox/tox is the gate oxide capacitance with ox=3.5x10-11F/m)
CMPEN 411 L03 S.8
The Body Effect
0.9
0.85
0.8
VSB is the substrate
bias voltage (normally
positive for n-channel
devices with the body
tied to ground)

0.75
0.7
0.65
0.6
0.55
A negative bias Vbs
causes VT to increase
from 0.45V to 0.85V

0.5
0.45
0.4
-2.5
CMPEN 411 L03 S.9
-2
-1.5
-1
VBS (V)
-0.5
0
Transistor in Linear Mode
Assuming VGS > VT
VGS
VDS
G
S
D
n+
ID
n+
- V(x) +
x
B
The current is a linear function of both VGS and VDS
CMPEN 411 L03 S.10
Voltage-Current Relation: Linear Mode
For long-channel devices (L > 0.25 micron)

When VDS  VGS – VT
ID = k’n W/L [(VGS – VT)VDS – VDS2/2]
where
k’n = nCox = nox/tox = is the process
transconductance parameter (n is the carrier mobility
(m2/Vsec))
kn = k’n W/L is the gain factor of the device
For small VDS, there is a linear dependence between VDS
and ID, hence the name resistive or linear region
CMPEN 411 L03 S.11
Transistor in Saturation Mode
Assuming VGS > VT
VGS
VDS
G
S
D
n+
VDS > VGS - VT
ID
n+
- V -V +
GS
T
Pinch-off
B
The current remains constant (transistor saturates)
CMPEN 411 L03 S.12
Voltage-Current Relation: Saturation Mode
For long channel devices

When VDS  VGS – VT
ID’ = k’n/2 W/L [(VGS – VT) 2]
since the voltage difference over the induced channel
(from the pinch-off point to the source) remains fixed at
VGS – VT

However, the effective length of the conductive channel
is modulated by the applied VDS, so
ID = ID’ (1 + VDS)
where  is the channel-length modulation (varies with the
inverse of the channel length)
CMPEN 411 L03 S.13
Current Determinates
 For
of
a fixed VDS and VGS (> VT), IDS is a function
the distance between the source and drain – L
 the channel width – W
 the threshold voltage – VT

the thickness of the SiO2 – tox
 the dielectric of the gate insulator (e.g., SiO2) – ox
 the carrier mobility

- for nfets: n = 500 cm2/V-sec
- for pfets: p = 180 cm2/V-sec
CMPEN 411 L03 S.14
Long Channel I-V Plot (NMOS)
6
X 10-4
VDS = VGS - VT
5
VGS = 2.5V
2.07V
4
1.57V
VGS = 2.0V
3
Linear
Saturation
2
VGS = 1.5V
1.07V
1
VGS = 1.0V
0
cut-off
0.57V
0
0.5
1
1.5
2
2.5
VDS (V)
NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.43V
CMPEN 411 L03 S.16
Short Channel Effects

10
Behavior of short channel device mainly due to
5
Velocity saturation
– the velocity of the
carriers saturates due
to scattering (collisions
suffered by the
carriers)

0
0
c= 1.5
3
(V/m)

For an NMOS device with L of .25m, only a couple of volts
difference between D and S are needed to reach velocity
saturation
CMPEN 411 L03 S.17
Voltage-Current Relation: Velocity Saturation
For short channel devices

Linear: When VDS  VGS – VT
ID = (VDS) k’n W/L [(VGS – VT)VDS – VDS2/2]
where
(V) = 1/(1 + (V/cL)) is a measure of the degree of
velocity saturation

Saturation: When VDS = VDSAT  VGS – VT
IDSat = (VDSAT) k’n W/L [(VGS – VT)VDSAT – VDSAT2/2]
CMPEN 411 L03 S.18
Velocity Saturation Effects
For short channel devices
and large enough VGS – VT
10
VDSAT < VGS – VT so
the device enters
saturation before VDS
reaches VGS – VT and
operates more often in
saturation

0
IDSAT has a linear dependence wrt VGS so a reduced
amount of current is delivered for a given control
voltage

CMPEN 411 L03 S.19
Short Channel I-V Plot (NMOS)
2.5
X 10-4
Early Velocity
Saturation
VGS = 2.5V
2
VGS = 2.0V
1.5
Linear
1
Saturation
VGS = 1.5V
VGS = 1.0V
0.5
0
0
0.5
1
1.5
2
2.5
VDS (V)
NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.43V
CMPEN 411 L03 S.20
Long Channel I-V Plot (NMOS)
6
X 10-4
VDS = VGS - VT
5
VGS = 2.5V
2.07V
4
1.57V
VGS = 2.0V
3
Linear
Saturation
2
VGS = 1.5V
1.07V
1
VGS = 1.0V
0
cut-off
0.57V
0
0.5
1
1.5
2
2.5
VDS (V)
NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.43V
CMPEN 411 L03 S.21
MOS ID-VGS Characteristics
Linear (short-channel)
versus quadratic (longchannel) dependence of
ID on VGS in saturation

X 10-4
6
5
4
3
2
1
0
Velocity-saturation
causes the shortchannel device to
saturate at substantially
smaller values of VDS
2.5 resulting in a substantial
drop in current drive

0
0.5
1
1.5
VGS (V)
(for VDS = 2.5V, W/L = 1.5)
CMPEN 411 L03 S.22
2
Short Channel I-V Plot (PMOS)

All polarities of all voltages and currents are reversed
-2
VDS (V)
-1
0
0
VGS = -1.0V
-0.2
VGS = -1.5V
-0.4
-0.6
VGS = -2.0V
-0.8
VGS = -2.5V
-1 X 10-4
PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V
CMPEN 411 L03 S.23
The MOS Current-Source Model
ID = 0 for VGS – VT  0
G
ID
S
D
ID = k’ W/L [(VGS – VT)Vmin–Vmin2/2](1+VDS)
for VGS – VT  0
with Vmin = min(VGS – VT, VDS, VDSAT)
and VGT = VGS - VT
B
Determined by the voltages at the four terminals and
a set of five device parameters

NMOS
PMOS
CMPEN 411 L03 S.24
VT0(V)
0.43
-0.4
(V0.5)
0.4
-0.4
VDSAT(V)
0.63
-1
k’(A/V2)
115 x 10-6
-30 x 10-6
(V-1)
0.06
-0.1
Other (Submicon) MOS Transistor Concerns

Velocity saturation

Subthreshold conduction (aka weak inversion)


Threshold variations



In long-channel devices, the threshold is a function of the length
(for low VDS)
In short-channel devices, there is a drain-induced threshold
barrier lowering (DIBL) at the upper end of the VDS range (for
small L)
G
Parasitic resistances


Transistor is already partially conducting for voltages below VT
resistances associated with the
source and drain contacts
Latch-up
CMPEN 411 L03 S.25
S
D
RS
RD
Subthreshold Conductance
10-2
Transition from ON to
OFF is gradual (decays
exponentially)
 Current roll-off (slope
factor) is also affected by
increase in temperature

Linear region
Quadratic region
Subthreshold
exponential
region
10-12
VT
0
0.5
S = n (kT/q) ln (10)
(typical values 60 to 100
mV/decade)
1
1.5
2
VGS (V)
ID ~ IS e (qVGS/nkT) where n  1
CMPEN 411 L03 S.26
2.5
Has repercussions in
dynamic circuits and for
power consumption

Subthreshold ID vs VGS
ID = IS e (qVGS/nkT) (1 - e –(qVDS/kT))(1 + VDS)
VGS from 0 to 0.5V
CMPEN 411 L03 S.27
Subthreshold ID vs VDS
ID = IS e (qVGS/nkT) (1 - e –(qVDS/kT))(1 + VDS)
VDS from 0 to 0.3V
CMPEN 411 L03 S.28
Threshold Variations
VT
VT
Long channel
threshold
L
Threshold varies as a
function of the length of the
transistor (for low VDS)
CMPEN 411 L03 S.29
Low VDS
threshold
VDS
For short channel devices, the
threshold varies as a function of
VDS - drain-induced barrier
lowering (DIBL)
DIBL
10-2

For high VDS, the drain
depletion region
interacts with the
source near the
channel surface
lowering the source
potential barrier. The
source then injects
carriers into the
channel without the
gate playing a role.

DIBL is enhanced at
higher VDS and shorter
L.
increasing VDS
10-12
0
0.5
1
1.5
VGS (V)
CMPEN 411 L03 S.30
2
2.5
Next Time: The CMOS Inverter

Next lecture

CMOS inverter – a static view
- Reading assignment – Rabaey, et al, 5.1-5.3
VDD
Vin
Vout
CL
CMPEN 411 L03 S.31